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/Linux-v6.1/Documentation/devicetree/bindings/interconnect/
Dqcom,sm6350-rpmh.yaml66 reg = <0x01500000 0x28000>;
73 reg = <0x01620000 0x17080>;
/Linux-v6.1/arch/arm/boot/dts/
Ddra7-evm-common.dtsi90 #size-cells = <0>;
123 <&dra7_pmx_core 0x3e0>;
138 flash@0 {
141 reg = <0>;
152 partition@0 {
154 reg = <0x00000000 0x000010000>;
158 reg = <0x00010000 0x00010000>;
162 reg = <0x00020000 0x00010000>;
166 reg = <0x00030000 0x00010000>;
170 reg = <0x00040000 0x00100000>;
[all …]
Dam57xx-idk-common.dtsi64 gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
111 hdmi0: connector@0 {
124 tpd12s015: encoder@0 {
127 gpios = <0>, /* optional CT_CP_HPD */
128 <0>, /* optional LS_OE */
133 #size-cells = <0>;
135 port@0 {
136 reg = <0>;
138 tpd12s015_in: endpoint@0 {
146 tpd12s015_out: endpoint@0 {
[all …]
Ddra72-evm-common.dtsi129 #size-cells = <0>;
131 port@0 {
132 reg = <0>;
194 #clock-cells = <0>;
202 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
203 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
209 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
210 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
221 reg = <0x20>;
230 reg = <0x21>;
[all …]
Dqcom-sdx65.dtsi18 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
23 reg = <0 0>;
31 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0>;
113 reg = <0x8fcad000 0x40000>;
118 reg = <0x8fcfd000 0x1000>;
[all …]
/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dsm6350.dtsi25 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
63 reg = <0x0 0x100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x200>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc7180.dtsi61 #clock-cells = <0>;
67 #clock-cells = <0>;
77 reg = <0x0 0x80000000 0x0 0x600000>;
82 reg = <0x0 0x80600000 0x0 0x200000>;
87 reg = <0x0 0x80800000 0x0 0x20000>;
92 reg = <0x0 0x80820000 0x0 0x20000>;
98 reg = <0x0 0x808ff000 0x0 0x1000>;
103 reg = <0x0 0x80900000 0x0 0x200000>;
108 reg = <0x0 0x80b00000 0x0 0x3900000>;
113 reg = <0 0x8b700000 0 0x10000>;
[all …]
Dsm8150.dtsi29 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
73 reg = <0x0 0x100>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
95 reg = <0x0 0x200>;
100 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsdm845.dtsi75 reg = <0 0x80000000 0 0>;
84 reg = <0 0x85700000 0 0x600000>;
89 reg = <0 0x85e00000 0 0x100000>;
94 reg = <0 0x85fc0000 0 0x20000>;
100 reg = <0x0 0x85fe0000 0 0x20000>;
106 reg = <0x0 0x86000000 0 0x200000>;
112 reg = <0 0x86200000 0 0x2d00000>;
118 reg = <0 0x88f00000 0 0x200000>;
126 reg = <0 0x8ab00000 0 0x1400000>;
131 reg = <0 0x8bf00000 0 0x500000>;
[all …]
Dsm8250.dtsi80 #clock-cells = <0>;
88 #clock-cells = <0>;
94 #size-cells = <0>;
96 CPU0: cpu@0 {
99 reg = <0x0 0x0>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
123 reg = <0x0 0x100>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
144 reg = <0x0 0x200>;
151 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]