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/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_6_1_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
Dnbio_7_0_offset.h27 // base address: 0x0
28 …NB_NBCFG0_NB_VENDOR_ID 0x0000
29 …NB_NBCFG0_NB_DEVICE_ID 0x0002
30 …NB_NBCFG0_NB_COMMAND 0x0004
31 …NB_NBCFG0_NB_STATUS 0x0006
32 …NB_NBCFG0_NB_REVISION_ID 0x0008
33 …NB_NBCFG0_NB_REGPROG_INF 0x0009
34 …NB_NBCFG0_NB_SUB_CLASS 0x000a
35 …NB_NBCFG0_NB_BASE_CODE 0x000b
36 …NB_NBCFG0_NB_CACHE_LINE 0x000c
[all …]
Dnbio_7_4_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
Dnbio_2_3_offset.h27 // base address: 0x0
28 …BIF_BX_PF_MM_INDEX 0x0000
29 …ne mmBIF_BX_PF_MM_INDEX_BASE_IDX 0
30 …BIF_BX_PF_MM_DATA 0x0001
31 …ne mmBIF_BX_PF_MM_DATA_BASE_IDX 0
32 …BIF_BX_PF_MM_INDEX_HI 0x0006
33 …ne mmBIF_BX_PF_MM_INDEX_HI_BASE_IDX 0
37 // base address: 0x0
38 …SYSHUB_INDEX_OVLP 0x0008
39 …ne mmSYSHUB_INDEX_OVLP_BASE_IDX 0
[all …]
Dnbio_4_3_0_offset.h29 // base address: 0x0
30 …BIF_BX0_PCIE_INDEX 0x000c
31 …e regBIF_BX0_PCIE_INDEX_BASE_IDX 0
32 …BIF_BX0_PCIE_DATA 0x000d
33 …e regBIF_BX0_PCIE_DATA_BASE_IDX 0
34 …BIF_BX0_PCIE_INDEX2 0x000e
35 …e regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
36 …BIF_BX0_PCIE_DATA2 0x000f
37 …e regBIF_BX0_PCIE_DATA2_BASE_IDX 0
38 …BIF_BX0_PCIE_INDEX_HI 0x0010
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
/Linux-v6.1/drivers/clk/mediatek/
Dclk-mt8195-apmixedsys.c15 .set_ofs = 0x8,
16 .clr_ofs = 0x8,
17 .sta_ofs = 0x8,
60 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
61 0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0, 0x0398, 0, 9),
62 PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
63 0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0, 0x0198, 0, 9),
64 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
65 0, 0, 22, 0x0368, 24, 0, 0, 0, 0x0368, 0, 0x0368, 0, 9),
66 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
[all …]
Dclk-mt8186-topckgen.c506 0x0040, 0x0044, 0x0048, 0, 2, 7, 0x0004, 0,
509 0x0040, 0x0044, 0x0048, 8, 3, 15, 0x0004, 1,
512 mfg_parents, 0x0040, 0x0044, 0x0048, 16, 2, 23, 0x0004, 2),
514 camtg_parents, 0x0040, 0x0044, 0x0048, 24, 3, 31, 0x0004, 3),
517 camtg_parents, 0x0050, 0x0054, 0x0058, 0, 3, 7, 0x0004, 4),
519 camtg_parents, 0x0050, 0x0054, 0x0058, 8, 3, 15, 0x0004, 5),
521 camtg_parents, 0x0050, 0x0054, 0x0058, 16, 3, 23, 0x0004, 6),
523 camtg_parents, 0x0050, 0x0054, 0x0058, 24, 3, 31, 0x0004, 7),
526 camtg_parents, 0x0060, 0x0064, 0x0068, 0, 3, 7, 0x0004, 8),
528 camtg_parents, 0x0060, 0x0064, 0x0068, 8, 3, 15, 0x0004, 9),
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
/Linux-v6.1/arch/s390/include/asm/
Dlowcore.h25 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */
26 __u32 ipl_parmblock_ptr; /* 0x0014 */
27 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
28 __u32 ext_params; /* 0x0080 */
31 __u16 ext_cpu_addr; /* 0x0084 */
32 __u16 ext_int_code; /* 0x0086 */
36 __u32 svc_int_code; /* 0x0088 */
39 __u16 pgm_ilc; /* 0x008c */
40 __u16 pgm_code; /* 0x008e */
44 __u32 data_exc_code; /* 0x0090 */
[all …]
/Linux-v6.1/include/linux/
Di8042.h12 #define I8042_CMD_CTL_RCTR 0x0120
13 #define I8042_CMD_CTL_WCTR 0x1060
14 #define I8042_CMD_CTL_TEST 0x01aa
16 #define I8042_CMD_KBD_DISABLE 0x00ad
17 #define I8042_CMD_KBD_ENABLE 0x00ae
18 #define I8042_CMD_KBD_TEST 0x01ab
19 #define I8042_CMD_KBD_LOOP 0x11d2
21 #define I8042_CMD_AUX_DISABLE 0x00a7
22 #define I8042_CMD_AUX_ENABLE 0x00a8
23 #define I8042_CMD_AUX_TEST 0x01a9
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dintel,lgm-emmc-phy.yaml31 const: 0
55 reg = <0xe0200000 0x100>;
61 reg = <0x00a8 0x10>;
63 #phy-cells = <0>;
70 reg = <0x20290000 0x54>;
73 #phy-cells = <0>;
/Linux-v6.1/sound/pci/ymfpci/
Dymfpci.h22 #define YDSXGR_INTFLAG 0x0004
23 #define YDSXGR_ACTIVITY 0x0006
24 #define YDSXGR_GLOBALCTRL 0x0008
25 #define YDSXGR_ZVCTRL 0x000A
26 #define YDSXGR_TIMERCTRL 0x0010
27 #define YDSXGR_TIMERCOUNT 0x0012
28 #define YDSXGR_SPDIFOUTCTRL 0x0018
29 #define YDSXGR_SPDIFOUTSTATUS 0x001C
30 #define YDSXGR_EEPROMCTRL 0x0020
31 #define YDSXGR_SPDIFINCTRL 0x0034
[all …]
/Linux-v6.1/arch/powerpc/include/asm/
Dcell-regs.h28 #define HID0_CBE_THERM_WAKEUP 0x0000020000000000ul
29 #define HID0_CBE_SYSERR_WAKEUP 0x0000008000000000ul
30 #define HID0_CBE_THERM_INT_EN 0x0000000400000000ul
31 #define HID0_CBE_SYSERR_INT_EN 0x0000000200000000ul
57 u64 pad_0x0000; /* 0x0000 */
59 u64 group_control; /* 0x0008 */
61 u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */
63 u64 debug_bus_control; /* 0x00a8 */
65 u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */
67 u64 trace_aux_data; /* 0x0100 */
[all …]
/Linux-v6.1/drivers/media/cec/platform/s5p/
Dregs-cec.h16 #define S5P_CEC_STATUS_0 (0x0000)
17 #define S5P_CEC_STATUS_1 (0x0004)
18 #define S5P_CEC_STATUS_2 (0x0008)
19 #define S5P_CEC_STATUS_3 (0x000C)
20 #define S5P_CEC_IRQ_MASK (0x0010)
21 #define S5P_CEC_IRQ_CLEAR (0x0014)
22 #define S5P_CEC_LOGIC_ADDR (0x0020)
23 #define S5P_CEC_DIVISOR_0 (0x0030)
24 #define S5P_CEC_DIVISOR_1 (0x0034)
25 #define S5P_CEC_DIVISOR_2 (0x0038)
[all …]
/Linux-v6.1/drivers/gpu/drm/rockchip/
Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
/Linux-v6.1/arch/arm/mach-omap2/
Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
Dprm3xxx.h33 #define OMAP3_PRM_REVISION_OFFSET 0x0004
34 #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
35 #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
36 #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
38 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
39 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
40 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
41 #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
44 #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
45 #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
[all …]
/Linux-v6.1/include/linux/platform_data/
Dgpio-omap.h18 #define OMAP1_MPUIO_BASE 0xfffb5000
24 #define OMAP_MPUIO_INPUT_LATCH 0x00
25 #define OMAP_MPUIO_OUTPUT 0x04
26 #define OMAP_MPUIO_IO_CNTL 0x08
27 #define OMAP_MPUIO_KBR_LATCH 0x10
28 #define OMAP_MPUIO_KBC 0x14
29 #define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
30 #define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
31 #define OMAP_MPUIO_KBD_INT 0x20
32 #define OMAP_MPUIO_GPIO_INT 0x24
[all …]
/Linux-v6.1/drivers/gpu/drm/tests/
Ddrm_format_helper_test.c61 .clip = DRM_RECT_INIT(0, 0, 1, 1),
62 .xrgb8888 = { 0x01FF0000 },
64 .dst_pitch = 0,
65 .expected = { 0x4C },
68 .dst_pitch = 0,
69 .expected = { 0xE0 },
72 .dst_pitch = 0,
73 .expected = { 0xF800 },
74 .expected_swab = { 0x00F8 },
77 .dst_pitch = 0,
[all …]
/Linux-v6.1/arch/s390/kernel/
Dperf_cpum_cf_events.c14 CPUMF_EVENT_ATTR(cf_fvn1, CPU_CYCLES, 0x0000);
15 CPUMF_EVENT_ATTR(cf_fvn1, INSTRUCTIONS, 0x0001);
16 CPUMF_EVENT_ATTR(cf_fvn1, L1I_DIR_WRITES, 0x0002);
17 CPUMF_EVENT_ATTR(cf_fvn1, L1I_PENALTY_CYCLES, 0x0003);
18 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES, 0x0020);
19 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
20 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022);
21 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023);
22 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024);
23 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025);
[all …]
/Linux-v6.1/drivers/media/usb/gspca/
Dspca501.c29 #define Arowana300KCMOSCamera 0
53 .priv = 0},
56 #define SPCA50X_REG_USB 0x2 /* spca505 501 */
65 #define SPCA501_SNAPBIT 0x80
66 #define SPCA501_SNAPCTRL 0x10
78 #define SPCA501_PROP_SNAP(d) ((d) & 0x40)
79 #define SPCA501_PROP_SNAP_CTRL(d) ((d) & 0x10)
80 #define SPCA501_PROP_COMP_THRESH(d) (((d) & 0x0e) >> 1)
81 #define SPCA501_PROP_COMP_QUANT(d) (((d) & 0x70) >> 4)
84 #define SPCA501_REG_CCDSP 0x01
[all …]
/Linux-v6.1/drivers/video/fbdev/
Dcarminefb_regs.h5 #define CARMINE_OVERLAY_EXT_MODE (0x00000002)
6 #define CARMINE_GRAPH_REG (0x00000000)
7 #define CARMINE_DISP0_REG (0x00100000)
8 #define CARMINE_DISP1_REG (0x00140000)
9 #define CARMINE_WB_REG (0x00180000)
10 #define CARMINE_DCTL_REG (0x00300000)
11 #define CARMINE_CTL_REG (0x00400000)
12 #define CARMINE_WINDOW_MODE (0x00000001)
19 #define CARMINE_EXT_CMODE_DIRECT24_RGBA (0xC0000000)
20 #define CARMINE_DCTL_REG_MODE_ADD (0x00)
[all …]
/Linux-v6.1/sound/soc/sof/mediatek/mt8195/
Dmt8195.h15 #define DSP_REG_BASE 0x10803000
16 #define SCP_CFGREG_BASE 0x10724000
17 #define DSP_SYSAO_BASE 0x1080C000
22 #define DSP_JTAGMUX 0x0000
23 #define DSP_ALTRESETVEC 0x0004
24 #define DSP_PDEBUGDATA 0x0008
25 #define DSP_PDEBUGBUS0 0x000c
26 #define PDEBUG_ENABLE BIT(0)
27 #define DSP_PDEBUGBUS1 0x0010
28 #define DSP_PDEBUGINST 0x0014
[all …]

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