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/Linux-v5.15/drivers/gpu/drm/ast/
Dast_dram_tables.h12 { 0x0108, 0x00000000 },
13 { 0x0120, 0x00004a21 },
14 { 0xFF00, 0x00000043 },
15 { 0x0000, 0xFFFFFFFF },
16 { 0x0004, 0x00000089 },
17 { 0x0008, 0x22331353 },
18 { 0x000C, 0x0d07000b },
19 { 0x0010, 0x11113333 },
20 { 0x0020, 0x00110350 },
21 { 0x0028, 0x1e0828f0 },
[all …]
/Linux-v5.15/arch/arm/mach-omap2/
Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
Dcm33xx.h25 #define AM33XX_CM_BASE 0x44e00000
31 #define AM33XX_CM_PER_MOD 0x0000
32 #define AM33XX_CM_WKUP_MOD 0x0400
33 #define AM33XX_CM_DPLL_MOD 0x0500
34 #define AM33XX_CM_MPU_MOD 0x0600
35 #define AM33XX_CM_DEVICE_MOD 0x0700
36 #define AM33XX_CM_RTC_MOD 0x0800
37 #define AM33XX_CM_GFX_MOD 0x0900
38 #define AM33XX_CM_CEFUSE_MOD 0x0A00
43 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
Dprm3xxx.h33 #define OMAP3_PRM_REVISION_OFFSET 0x0004
34 #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
35 #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
36 #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
38 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
39 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
40 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
41 #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
44 #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
45 #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
[all …]
Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
Dcm1_54xx.h22 #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
28 #define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300
31 #define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400
32 #define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500
33 #define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00
34 #define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00
37 #define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
38 #define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000
[all …]
Dcm1_44xx.h26 #define OMAP4430_CM1_BASE 0x4a004000
32 #define OMAP4430_CM1_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM1_CKGEN_INST 0x0100
34 #define OMAP4430_CM1_MPU_INST 0x0300
35 #define OMAP4430_CM1_TESLA_INST 0x0400
36 #define OMAP4430_CM1_ABE_INST 0x0500
37 #define OMAP4430_CM1_RESTORE_INST 0x0e00
38 #define OMAP4430_CM1_INSTR_INST 0x0f00
41 #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
42 #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
[all …]
Dcm1_7xx.h23 #define DRA7XX_CM_CORE_AON_BASE 0x4a005000
29 #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
31 #define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
32 #define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
33 #define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
34 #define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
35 #define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
36 #define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
37 #define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_6_1_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
Dnbio_7_0_offset.h27 // base address: 0x0
28 …NB_NBCFG0_NB_VENDOR_ID 0x0000
29 …NB_NBCFG0_NB_DEVICE_ID 0x0002
30 …NB_NBCFG0_NB_COMMAND 0x0004
31 …NB_NBCFG0_NB_STATUS 0x0006
32 …NB_NBCFG0_NB_REVISION_ID 0x0008
33 …NB_NBCFG0_NB_REGPROG_INF 0x0009
34 …NB_NBCFG0_NB_SUB_CLASS 0x000a
35 …NB_NBCFG0_NB_BASE_CODE 0x000b
36 …NB_NBCFG0_NB_CACHE_LINE 0x000c
[all …]
Dnbio_7_4_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
Dimx6ull-pinfunc-snvs.h13 #define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0
14 #define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0
15 #define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0
16 #define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0
17 #define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0
18 #define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0
19 #define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0
20 #define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0
21 #define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0
22 #define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/clock/
Ddove-divider-clock.txt11 0 AXI bus clock
19 Control 0 register. This will cover that register, as well as the
26 reg = <0x0064 0x8>;
/Linux-v5.15/drivers/dma/dw-edma/
Ddw-edma-v0-regs.h15 #define EDMA_V0_VIEWPORT_MASK GENMASK(2, 0)
16 #define EDMA_V0_DONE_INT_MASK GENMASK(7, 0)
18 #define EDMA_V0_WRITE_CH_COUNT_MASK GENMASK(3, 0)
21 #define EDMA_V0_DOORBELL_CH_MASK GENMASK(2, 0)
22 #define EDMA_V0_LINKED_LIST_ERR_MASK GENMASK(7, 0)
25 #define EDMA_V0_CH_EVEN_MSI_DATA_MASK GENMASK(15, 0)
28 u32 ch_control1; /* 0x0000 */
29 u32 ch_control2; /* 0x0004 */
30 u32 transfer_size; /* 0x0008 */
32 u64 reg; /* 0x000c..0x0010 */
[all …]
/Linux-v5.15/arch/arm/mach-mmp/
Dregs-timers.h11 #define TIMERS1_VIRT_BASE (APB_VIRT_BASE + 0x14000)
12 #define TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x16000)
14 #define TMR_CCR (0x0000)
15 #define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2))
16 #define TMR_CR(n) (0x0028 + ((n) << 2))
17 #define TMR_SR(n) (0x0034 + ((n) << 2))
18 #define TMR_IER(n) (0x0040 + ((n) << 2))
19 #define TMR_PLVR(n) (0x004c + ((n) << 2))
20 #define TMR_PLCR(n) (0x0058 + ((n) << 2))
21 #define TMR_WMER (0x0064)
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce/
Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu7_powertune.h26 #define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xfffc0000
27 #define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x12
28 #define DIDT_TD_CTRL0__UNUSED_0_MASK 0xfffc0000
29 #define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x12
30 #define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xfffc0000
31 #define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x12
32 #define DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK 0xc0000000
33 #define DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e
34 #define DIDT_TD_TUNING_CTRL__UNUSED_0_MASK 0xc0000000
35 #define DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/df/
Ddf_3_6_offset.h24 #define mmFabricConfigAccessControl 0x0410
25 #define mmFabricConfigAccessControl_BASE_IDX 0
27 #define mmDF_PIE_AON0_DfGlobalClkGater 0x00fc
28 #define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX 0
30 #define mmDF_CS_UMC_AON0_DfGlobalCtrl 0x00fe
31 #define mmDF_CS_UMC_AON0_DfGlobalCtrl_BASE_IDX 0
33 #define mmDF_CS_UMC_AON0_DramBaseAddress0 0x0044
34 #define mmDF_CS_UMC_AON0_DramBaseAddress0_BASE_IDX 0
36 #define mmDF_GCM_AON0_DramMegaBaseAddress0 0x0064
37 #define mmDF_GCM_AON0_DramMegaBaseAddress0_BASE_IDX 0
[all …]
/Linux-v5.15/drivers/gpu/drm/exynos/
Dregs-vp.h19 #define VP_ENABLE 0x0000
20 #define VP_SRESET 0x0004
21 #define VP_SHADOW_UPDATE 0x0008
22 #define VP_FIELD_ID 0x000C
23 #define VP_MODE 0x0010
24 #define VP_IMG_SIZE_Y 0x0014
25 #define VP_IMG_SIZE_C 0x0018
26 #define VP_PER_RATE_CTRL 0x001C
27 #define VP_TOP_Y_PTR 0x0028
28 #define VP_BOT_Y_PTR 0x002C
[all …]
/Linux-v5.15/sound/soc/bcm/
Dbcm63xx-i2s.h10 #define I2S_MISC_CFG (0x003C)
19 #define I2S_TX_CLOCK_ENABLE (1 << 0)
22 #define I2S_TX_DESC_OFF_LEVEL_MASK (0x0F << I2S_TX_DESC_OFF_LEVEL_SHIFT)
24 #define I2S_TX_DESC_IFF_LEVEL_MASK (0x0F << I2S_TX_DESC_IFF_LEVEL_SHIFT)
28 #define I2S_TX_CFG (0x0000)
29 #define I2S_TX_IRQ_CTL (0x0004)
30 #define I2S_TX_IRQ_EN (0x0008)
31 #define I2S_TX_IRQ_IFF_THLD (0x000c)
32 #define I2S_TX_IRQ_OFF_THLD (0x0010)
33 #define I2S_TX_DESC_IFF_ADDR (0x0014)
[all …]
/Linux-v5.15/drivers/media/cec/platform/s5p/
Dregs-cec.h16 #define S5P_CEC_STATUS_0 (0x0000)
17 #define S5P_CEC_STATUS_1 (0x0004)
18 #define S5P_CEC_STATUS_2 (0x0008)
19 #define S5P_CEC_STATUS_3 (0x000C)
20 #define S5P_CEC_IRQ_MASK (0x0010)
21 #define S5P_CEC_IRQ_CLEAR (0x0014)
22 #define S5P_CEC_LOGIC_ADDR (0x0020)
23 #define S5P_CEC_DIVISOR_0 (0x0030)
24 #define S5P_CEC_DIVISOR_1 (0x0034)
25 #define S5P_CEC_DIVISOR_2 (0x0038)
[all …]
/Linux-v5.15/include/media/
Ddvb-usb-ids.h14 #define USB_VID_ADSTECH 0x06e1
15 #define USB_VID_AFATECH 0x15a4
16 #define USB_VID_ALCOR_MICRO 0x058f
17 #define USB_VID_ALINK 0x05e3
18 #define USB_VID_AMT 0x1c73
19 #define USB_VID_ANCHOR 0x0547
20 #define USB_VID_ANSONIC 0x10b9
21 #define USB_VID_ANUBIS_ELECTRONIC 0x10fd
22 #define USB_VID_ASUS 0x0b05
23 #define USB_VID_AVERMEDIA 0x07ca
[all …]
/Linux-v5.15/arch/mips/include/asm/mach-lantiq/xway/
Dlantiq_soc.h15 #define SOC_ID_DANUBE1 0x129
16 #define SOC_ID_DANUBE2 0x12B
17 #define SOC_ID_TWINPASS 0x12D
18 #define SOC_ID_AMAZON_SE_1 0x152 /* 50601 */
19 #define SOC_ID_AMAZON_SE_2 0x153 /* 50600 */
20 #define SOC_ID_ARX188 0x16C
21 #define SOC_ID_ARX168_1 0x16D
22 #define SOC_ID_ARX168_2 0x16E
23 #define SOC_ID_ARX182 0x16F
24 #define SOC_ID_GRX188 0x170
[all …]

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