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12

/Linux-v6.1/arch/arm/boot/dts/
Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "1", "0",
102 "0", "0", "-1";
107 mount-matrix = "0", "-1", "0",
108 "-1", "0", "0",
109 "0", "0", "1";
[all …]
Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
Dtegra30-asus-tf700t.dts18 port@0 {
92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "0",
119 "0", "0", "-1";
124 mount-matrix = "0", "-1", "0",
125 "-1", "0", "0",
[all …]
Dtegra30-pegatron-chagall.dts41 reg = <0x80000000 0x40000000>;
51 alloc-ranges = <0x80000000 0x30000000>;
52 size = <0x10000000>; /* 256MiB */
59 reg = <0xbeb00000 0x10000>; /* 64kB */
60 console-size = <0x8000>; /* 32kB */
61 record-size = <0x400>; /* 1kB */
66 reg = <0xbfe00000 0x200000>; /* 2MB */
92 pinctrl-0 = <&state_default>;
136 nvidia,lock = <0>;
137 nvidia,ioreset = <0>;
[all …]
Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "0",
90 "0", "0", "-1";
95 mount-matrix = "1", "0", "0",
96 "0", "-1", "0",
97 "0", "0", "1";
[all …]
Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
Dtegra30-ouya.dts30 reg = <0x80000000 0x40000000>;
40 alloc-ranges = <0x80000000 0x30000000>;
41 size = <0x10000000>; /* 256MiB */
48 reg = <0xbfdf0000 0x10000>; /* 64kB */
49 console-size = <0x8000>; /* 32kB */
50 record-size = <0x400>; /* 1kB */
55 reg = <0xbfe00000 0x200000>;
73 pinctrl-0 = <&state_default>;
2002 nvidia,adjust-baud-rates = <0 9600 100>,
2022 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
[all …]
Dtegra124-nyan-blaze-emc.dtsi89 0x40040001
90 0x8000000a
91 0x00000001
92 0x00000001
93 0x00000002
94 0x00000000
95 0x00000002
96 0x00000001
97 0x00000002
98 0x00000008
[all …]
Dtegra124-apalis-emc.dtsi106 0x40040001 0x8000000a
107 0x00000001 0x00000001
108 0x00000002 0x00000000
109 0x00000002 0x00000001
110 0x00000003 0x00000008
111 0x00000003 0x00000002
112 0x00000003 0x00000006
113 0x06030203 0x000a0502
114 0x77e30303 0x70000f03
115 0x001f0000
[all …]
Dtegra124-jetson-tk1-emc.dtsi101 0x40040001
102 0x8000000a
103 0x00000001
104 0x00000001
105 0x00000002
106 0x00000000
107 0x00000002
108 0x00000001
109 0x00000003
110 0x00000008
[all …]
Dtegra124-nyan-big-emc.dtsi260 0x40040001 /* MC_EMEM_ARB_CFG */
261 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
262 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
263 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
264 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
265 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
266 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
267 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
268 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
269 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-emc.yaml33 const: 0
51 "^emc-timings-[0-9]+$":
61 "^timing-[0-9]+$":
92 minimum: 0
155 minimum: 0
355 reg = <0x70019000 0x1000>;
368 reg = <0x7001b000 0x1000>;
376 #interconnect-cells = <0>;
378 emc-timings-0 {
381 timing-0 {
[all …]
/Linux-v6.1/include/linux/
Dfsl_ifc.h26 #define FSL_IFC_VERSION_MASK 0x0F0F0000
27 #define FSL_IFC_VERSION_1_0_0 0x01000000
28 #define FSL_IFC_VERSION_1_1_0 0x01010000
29 #define FSL_IFC_VERSION_2_0_0 0x02000000
37 #define CSPR_BA 0xFFFF0000
39 #define CSPR_PORT_SIZE 0x00000180
42 #define CSPR_PORT_SIZE_8 0x00000080
44 #define CSPR_PORT_SIZE_16 0x00000100
46 #define CSPR_PORT_SIZE_32 0x00000180
48 #define CSPR_WP 0x00000040
[all …]
/Linux-v6.1/drivers/net/wireless/realtek/rtl8xxxu/
Drtl8xxxu_8192c.c37 .reg_0e00 = 0x07090c0c,
38 .reg_0e04 = 0x01020405,
39 .reg_0e08 = 0x00000000,
40 .reg_086c = 0x00000000,
42 .reg_0e10 = 0x0b0c0c0e,
43 .reg_0e14 = 0x01030506,
44 .reg_0e18 = 0x0b0c0d0e,
45 .reg_0e1c = 0x01030509,
47 .reg_0830 = 0x07090c0c,
48 .reg_0834 = 0x01020405,
[all …]
Drtl8xxxu_8723a.c36 .reg_0e00 = 0x0a0c0c0c,
37 .reg_0e04 = 0x02040608,
38 .reg_0e08 = 0x00000000,
39 .reg_086c = 0x00000000,
41 .reg_0e10 = 0x0a0c0d0e,
42 .reg_0e14 = 0x02040608,
43 .reg_0e18 = 0x0a0c0d0e,
44 .reg_0e1c = 0x02040608,
46 .reg_0830 = 0x0a0c0c0c,
47 .reg_0834 = 0x02040608,
[all …]
/Linux-v6.1/drivers/thermal/qcom/
Dtsens-v0_1.c10 #define SROT_CTRL_OFF 0x0000
13 #define TM_INT_EN_OFF 0x0000
14 #define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004
15 #define TM_Sn_STATUS_OFF 0x0030
16 #define TM_TRDY_OFF 0x005c
19 #define MSM8916_BASE0_MASK 0x0000007f
20 #define MSM8916_BASE1_MASK 0xfe000000
21 #define MSM8916_BASE0_SHIFT 0
24 #define MSM8916_S0_P1_MASK 0x00000f80
25 #define MSM8916_S1_P1_MASK 0x003e0000
[all …]
/Linux-v6.1/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
Dtable.c7 0x024, 0x0011800f,
8 0x028, 0x00ffdb83,
9 0x800, 0x80040002,
10 0x804, 0x00000003,
11 0x808, 0x0000fc00,
12 0x80c, 0x0000000a,
13 0x810, 0x10005388,
14 0x814, 0x020c3d10,
15 0x818, 0x02200385,
16 0x81c, 0x00000000,
[all …]
/Linux-v6.1/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/
Dtable.c7 0x024, 0x0011800f,
8 0x028, 0x00ffdb83,
9 0x800, 0x80040002,
10 0x804, 0x00000003,
11 0x808, 0x0000fc00,
12 0x80c, 0x0000000a,
13 0x810, 0x10000330,
14 0x814, 0x020c3d10,
15 0x818, 0x02200385,
16 0x81c, 0x00000000,
[all …]
/Linux-v6.1/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
Dtable.c7 0x800, 0x80040000,
8 0x804, 0x00000003,
9 0x808, 0x0000fc00,
10 0x80c, 0x0000000a,
11 0x810, 0x10005388,
12 0x814, 0x020c3d10,
13 0x818, 0x02200385,
14 0x81c, 0x00000000,
15 0x820, 0x01000100,
16 0x824, 0x00390004,
[all …]
/Linux-v6.1/drivers/net/ethernet/intel/ice/
Dice_hw_autogen.h9 #define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4))
10 #define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4))
11 #define QTX_COMM_HEAD_HEAD_S 0
12 #define QTX_COMM_HEAD_HEAD_M ICE_M(0x1FFF, 0)
13 #define PF_FW_ARQBAH 0x00080180
14 #define PF_FW_ARQBAL 0x00080080
15 #define PF_FW_ARQH 0x00080380
16 #define PF_FW_ARQH_ARQH_M ICE_M(0x3FF, 0)
17 #define PF_FW_ARQLEN 0x00080280
18 #define PF_FW_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0)
[all …]
/Linux-v6.1/drivers/net/ethernet/sun/
Dsunhme.h15 #define GREG_SWRESET 0x000UL /* Software Reset */
16 #define GREG_CFG 0x004UL /* Config Register */
17 #define GREG_STAT 0x100UL /* Status */
18 #define GREG_IMASK 0x104UL /* Interrupt Mask */
19 #define GREG_REG_SIZE 0x108UL
22 #define GREG_RESET_ETX 0x01
23 #define GREG_RESET_ERX 0x02
24 #define GREG_RESET_ALL 0x03
27 #define GREG_CFG_BURSTMSK 0x03
28 #define GREG_CFG_BURST16 0x00
[all …]
/Linux-v6.1/drivers/gpu/drm/msm/adreno/
Da6xx.xml.h52 TILE6_LINEAR = 0,
194 DEPTH6_NONE = 0,
293 PERF_CP_ALWAYS_COUNT = 0,
346 PERF_RBBM_ALWAYS_COUNT = 0,
363 PERF_PC_BUSY_CYCLES = 0,
408 PERF_VFD_BUSY_CYCLES = 0,
434 PERF_HLSQ_BUSY_CYCLES = 0,
458 PERF_VPC_BUSY_CYCLES = 0,
489 PERF_TSE_BUSY_CYCLES = 0,
512 PERF_RAS_BUSY_CYCLES = 0,
[all …]
/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxnv40.c31 * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state"
35 * opcode 0x60000d is called before resuming normal operation.
37 * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001))
38 * and calls 0x60000d before resuming normal operation.
40 * and if true 0x800001 is called with count=0, pos=0, the flag is cleared
44 * flag 10. If it's set, they only transfer the small 0x300 byte block
50 * - There's a number of places where context offset 0 (where we place
51 * the PRAMIN offset of the context) is loaded into either 0x408000,
52 * 0x408004 or 0x408008. Not sure what's up there either.
53 * - The ctxprogs for some cards save 0x400a00 again during the cleanup
[all …]
/Linux-v6.1/drivers/net/wireless/ath/ath5k/
Dreg.h46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
52 #define AR5K_CR 0x0008 /* Register Address */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
54 #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
55 #define AR5K_CR_RXE 0x00000004 /* RX Enable */
56 #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
57 #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
58 #define AR5K_CR_RXD 0x00000020 /* RX Disable */
59 #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */
[all …]
/Linux-v6.1/drivers/net/wireless/ath/ath10k/
Drx_desc.h13 RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0),
57 * 0. The PPDU start status will only be valid when this bit
66 * address 1 bit 0 is set indicating mcast/bcast and the BSSID
227 * ring 0. Field is filled in by the RX_DMA.
243 HTT_RX_MPDU_ENCRYPT_WEP40 = 0,
256 #define RX_MPDU_START_INFO0_PEER_IDX_MASK 0x000007ff
257 #define RX_MPDU_START_INFO0_PEER_IDX_LSB 0
258 #define RX_MPDU_START_INFO0_SEQ_NUM_MASK 0x0fff0000
260 #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000
268 #define RX_MPDU_START_INFO1_TID_MASK 0xf0000000
[all …]

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