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/Linux-v5.10/arch/arm/mach-ep93xx/
Dsoc.h19 * the synchronous boot mode is selected. When ASDO is "0" (i.e
23 * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
24 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
25 * decoded at 0xf0000000.
34 #define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
35 #define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
36 #define EP93XX_CS1_PHYS_BASE 0x10000000
37 #define EP93XX_CS2_PHYS_BASE 0x20000000
38 #define EP93XX_CS3_PHYS_BASE 0x30000000
39 #define EP93XX_PCMCIA_PHYS_BASE 0x40000000
[all …]
/Linux-v5.10/arch/x86/include/asm/e820/
Dtypes.h37 E820_TYPE_SOFT_RESERVED = 0xefffffff,
102 #define ISA_START_ADDRESS 0x000a0000
103 #define ISA_END_ADDRESS 0x00100000
105 #define BIOS_BEGIN 0x000a0000
106 #define BIOS_END 0x00100000
108 #define HIGH_MEMORY 0x00100000
110 #define BIOS_ROM_BASE 0xffe00000
111 #define BIOS_ROM_END 0xffffffff
/Linux-v5.10/arch/arm/boot/dts/
Dbcm958522er.dts48 reg = <0x60000000 0x80000000>;
78 nandcs@0 {
80 reg = <0>;
91 partition@0 {
93 reg = <0x00000000 0x00200000>;
98 reg = <0x00200000 0x00400000>;
102 reg = <0x00600000 0x00a00000>;
106 reg = <0x01000000 0x03000000>;
110 reg = <0x04000000 0x3c000000>;
129 pinctrl-0 = <&nand_sel>;
[all …]
Dbcm958525er.dts48 reg = <0x60000000 0x80000000>;
78 nandcs@0 {
80 reg = <0>;
91 partition@0 {
93 reg = <0x00000000 0x00200000>;
98 reg = <0x00200000 0x00400000>;
102 reg = <0x00600000 0x00a00000>;
106 reg = <0x01000000 0x03000000>;
110 reg = <0x04000000 0x3c000000>;
129 pinctrl-0 = <&nand_sel>;
[all …]
Dbcm958525xmc.dts48 reg = <0x60000000 0x40000000>;
78 reg = <0x4c>;
83 reg = <0x52>;
89 reg = <0x68>;
94 nandcs@0 {
96 reg = <0>;
107 partition@0 {
109 reg = <0x00000000 0x00200000>;
114 reg = <0x00200000 0x00400000>;
118 reg = <0x00600000 0x00a00000>;
[all …]
Dbcm958622hr.dts48 reg = <0x60000000 0x80000000>;
82 nandcs@0 {
84 reg = <0>;
95 partition@0 {
97 reg = <0x00000000 0x00200000>;
102 reg = <0x00200000 0x00400000>;
106 reg = <0x00600000 0x00a00000>;
110 reg = <0x01000000 0x03000000>;
114 reg = <0x04000000 0x3c000000>;
133 pinctrl-0 = <&nand_sel>;
[all …]
Dbcm958623hr.dts48 reg = <0x60000000 0x80000000>;
82 nandcs@0 {
84 reg = <0>;
95 partition@0 {
97 reg = <0x00000000 0x00200000>;
102 reg = <0x00200000 0x00400000>;
106 reg = <0x00600000 0x00a00000>;
110 reg = <0x01000000 0x03000000>;
114 reg = <0x04000000 0x3c000000>;
133 pinctrl-0 = <&nand_sel>;
[all …]
Dbcm958625hr.dts48 reg = <0x60000000 0x20000000>;
93 nandcs@0 {
95 reg = <0>;
106 partition@0 {
108 reg = <0x00000000 0x00200000>;
113 reg = <0x00200000 0x00400000>;
117 reg = <0x00600000 0x00a00000>;
121 reg = <0x01000000 0x03000000>;
125 reg = <0x04000000 0x3c000000>;
144 pinctrl-0 = <&nand_sel>;
[all …]
Dbcm988312hr.dts48 reg = <0x60000000 0x80000000>;
78 nandcs@0 {
80 reg = <0>;
91 partition@0 {
93 reg = <0x00000000 0x00200000>;
98 reg = <0x00200000 0x00400000>;
102 reg = <0x00600000 0x00a00000>;
106 reg = <0x01000000 0x03000000>;
110 reg = <0x04000000 0x3c000000>;
129 pinctrl-0 = <&nand_sel>;
[all …]
Dbcm958625k.dts47 reg = <0x60000000 0x80000000>;
72 nandcs@0 {
74 reg = <0>;
85 partition@0 {
87 reg = <0x00000000 0x00200000>;
92 reg = <0x00200000 0x00400000>;
96 reg = <0x00600000 0x00a00000>;
100 reg = <0x01000000 0x03000000>;
104 reg = <0x04000000 0x3c000000>;
127 pinctrl-0 = <&nand_sel>, <&gpiobs>, <&pwmc>;
[all …]
Domap5-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]
Domap4-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]
/Linux-v5.10/arch/arm64/boot/dts/broadcom/northstar2/
Dns2-svk.dts50 bootargs = "earlycon=uart8250,mmio32,0x66130000";
55 reg = <0x000000000 0x80000000 0x00000000 0x40000000>;
110 slic@0 {
112 reg = <0>;
116 pl022,hierarchy = <0>;
117 pl022,interface = <0>;
118 pl022,slave-tx-disable = <0>;
119 pl022,com-mode = <0>;
123 pl022,wait-state = <0>;
124 pl022,duplex = <0>;
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/spi/
Dbrcm,spi-bcm-qspi.txt22 Must be <0>, also as required by generic SPI binding.
89 #address-cells = <0x1>;
90 #size-cells = <0x0>;
92 reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;
94 interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
95 interrupt-parent = <0x1c>;
107 m25p80@0 {
108 #size-cells = <0x2>;
109 #address-cells = <0x2>;
111 reg = <0x0>;
[all …]
/Linux-v5.10/arch/x86/include/uapi/asm/
De820.h4 #define E820MAP 0x2d0 /* our map */
29 #define E820NR 0x1e8 /* # entries in E820MAP */
70 #define ISA_START_ADDRESS 0xa0000
71 #define ISA_END_ADDRESS 0x100000
73 #define BIOS_BEGIN 0x000a0000
74 #define BIOS_END 0x00100000
76 #define BIOS_ROM_BASE 0xffe00000
77 #define BIOS_ROM_END 0xffffffff
/Linux-v5.10/arch/arm/mach-footbridge/
Debsa285.c22 #define XBUS_AMBER_L BIT(0)
84 for (i = 0; i < ARRAY_SIZE(ebsa285_leds); i++) { in ebsa285_leds_init()
97 if (led_classdev_register(NULL, &led->cdev) < 0) { in ebsa285_leds_init()
103 return 0; in ebsa285_leds_init()
115 .atag_offset = 0x100,
116 .video_start = 0x000a0000,
117 .video_end = 0x000bffff,
Ddc21285.c38 unsigned long addr = 0; in dc21285_base_address()
40 if (bus->number == 0) { in dc21285_base_address()
41 if (PCI_SLOT(devfn) == 0) in dc21285_base_address()
43 * For devfn 0, point at the 21285 in dc21285_base_address()
49 if (devfn < PCI_DEVFN(MAX_SLOTS, 0)) in dc21285_base_address()
50 addr = PCICFG0_BASE | 0xc00000 | (devfn << 8); in dc21285_base_address()
63 u32 v = 0xffffffff; in dc21285_read_config()
68 asm("ldrb %0, [%1, %2]" in dc21285_read_config()
72 asm("ldrh %0, [%1, %2]" in dc21285_read_config()
76 asm("ldr %0, [%1, %2]" in dc21285_read_config()
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/thermal/
Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/Linux-v5.10/arch/powerpc/boot/dts/
Duc101.dts75 phy0: ethernet-phy@0 {
77 reg = <0>;
91 reg = <0x2c>;
95 reg = <0x51>;
105 ranges = <0 0 0xff800000 0x00800000
106 1 0 0x80000000 0x00800000
107 3 0 0x80000000 0x00800000>;
109 flash@0,0 {
111 reg = <0 0 0x00800000>;
117 partition@0 {
[all …]
/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dregsnv04.h5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
20 #define NV40_PFIFO_RAMFC 0x00002220
[all …]
/Linux-v5.10/drivers/mtd/maps/
Dcfi_flagadm.c36 * 1: bootloader first 128k (0x00000000 - 0x0001FFFF) size 0x020000
37 * 2: kernel 640k (0x00020000 - 0x000BFFFF) size 0x0A0000
38 * 3: compressed 1536k root ramdisk (0x000C0000 - 0x0023FFFF) size 0x180000
39 * 4: writeable diskpartition (jffs)(0x00240000 - 0x003FFFFF) size 0x1C0000
42 #define FLASH_PHYS_ADDR 0x40000000
43 #define FLASH_SIZE 0x400000
45 #define FLASH_PARTITION0_ADDR 0x00000000
46 #define FLASH_PARTITION0_SIZE 0x00020000
48 #define FLASH_PARTITION1_ADDR 0x00020000
49 #define FLASH_PARTITION1_SIZE 0x000A0000
[all …]
/Linux-v5.10/drivers/net/wireless/ath/ath5k/
Drfbuffer.h108 AR5K_RF_TURBO = 0,
165 #define AR5K_RF5111_RF_TURBO { 1, 3, 0 }
168 #define AR5K_RF5111_OB_2GHZ { 3, 119, 0 }
169 #define AR5K_RF5111_DB_2GHZ { 3, 122, 0 }
171 #define AR5K_RF5111_OB_5GHZ { 3, 104, 0 }
172 #define AR5K_RF5111_DB_5GHZ { 3, 107, 0 }
174 #define AR5K_RF5111_PWD_XPD { 1, 95, 0 }
175 #define AR5K_RF5111_XPD_GAIN { 4, 96, 0 }
181 #define AR5K_RF5111_GAIN_I { 6, 29, 0 }
182 #define AR5K_RF5111_PLO_SEL { 1, 4, 0 }
[all …]
/Linux-v5.10/arch/mips/include/asm/txx9/
Djmr3927.h18 #define JMR3927_ROMCE0 0x1fc00000 /* 4M */
19 #define JMR3927_ROMCE1 0x1e000000 /* 4M */
20 #define JMR3927_ROMCE2 0x14000000 /* 16M */
21 #define JMR3927_ROMCE3 0x10000000 /* 64M */
22 #define JMR3927_ROMCE5 0x1d000000 /* 4M */
23 #define JMR3927_SDCS0 0x00000000 /* 32M */
24 #define JMR3927_SDCS1 0x02000000 /* 32M */
27 #define JMR3927_PCIMEM 0x08000000
28 #define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */
29 #define JMR3927_PCIIO 0x15000000
[all …]
/Linux-v5.10/arch/arm/mach-ixp4xx/
Domixp-setup.c40 .size = 0x00020000,
41 .offset = 0,
44 .size = 0x00020000,
45 .offset = 0x00020000,
48 .size = 0x00020000,
49 .offset = 0x00040000,
52 .size = 0x00020000,
53 .offset = 0x00060000,
56 .size = 0x00020000,
57 .offset = 0x00080000,
[all …]
/Linux-v5.10/drivers/scsi/dpt/
Ddpti_i2o.h30 #define I2O_EVT_CAPABILITY_OTHER 0x01
31 #define I2O_EVT_CAPABILITY_CHANGED 0x02
33 #define I2O_EVT_SENSOR_STATE_CHANGED 0x01
126 struct i2o_sys_tbl_entry iops[0];
136 #define I2O_CLASS_VERSION_10 0x00
137 #define I2O_CLASS_VERSION_11 0x01
143 #define I2O_CLASS_EXECUTIVE 0x000
144 #define I2O_CLASS_DDM 0x001
145 #define I2O_CLASS_RANDOM_BLOCK_STORAGE 0x010
146 #define I2O_CLASS_SEQUENTIAL_STORAGE 0x011
[all …]

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