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/Linux-v5.15/drivers/gpu/drm/etnaviv/
Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/
Dpcm032.dts24 reg = <0x00000000 0x08000000>; // 128MB
30 cell-index = <0>;
61 phy0: ethernet-phy@0 {
62 reg = <0>;
69 reg = <0x51>;
73 reg = <0x52>;
80 interrupt-map-mask = <0xf800 0 0 7>;
81 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
82 0xc000 0 0 2 &mpc5200_pic 1 1 3
83 0xc000 0 0 3 &mpc5200_pic 1 2 3
[all …]
Dmpc5121ads.dts21 nand@0 {
23 reg = <0x00000000 0x40000000>; /* 512MB + 512MB */
28 ranges = <0x0 0x0 0xfc000000 0x04000000
29 0x2 0x0 0x82000000 0x00008000>;
31 flash@0,0 {
33 reg = <0 0x0 0x4000000>;
39 protected@0 {
41 reg = <0x00000000 0x00040000>; // first sector is protected
46 reg = <0x00040000 0x03c00000>; // 60M for filesystem
50 reg = <0x03c40000 0x00280000>; // 2.5M for kernel
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/fsl/
Dmpc8572ds.dts19 reg = <0 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
22 0x1 0x0 0x0 0xe0000000 0x08000000
23 0x2 0x0 0x0 0xffa00000 0x00040000
24 0x3 0x0 0x0 0xffdf0000 0x00008000
25 0x4 0x0 0x0 0xffa40000 0x00040000
26 0x5 0x0 0x0 0xffa80000 0x00040000
27 0x6 0x0 0x0 0xffac0000 0x00040000>;
31 ranges = <0x0 0 0xffe00000 0x100000>;
35 reg = <0 0xffe08000 0 0x1000>;
[all …]
Dmpc8572ds_36b.dts19 reg = <0xf 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
22 0x1 0x0 0xf 0xe0000000 0x08000000
23 0x2 0x0 0xf 0xffa00000 0x00040000
24 0x3 0x0 0xf 0xffdf0000 0x00008000
25 0x4 0x0 0xf 0xffa40000 0x00040000
26 0x5 0x0 0xf 0xffa80000 0x00040000
27 0x6 0x0 0xf 0xffac0000 0x00040000>;
31 ranges = <0x0 0xf 0xffe00000 0x100000>;
35 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
Dp2020ds.dts19 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
20 0x1 0x0 0x0 0xe0000000 0x08000000
21 0x2 0x0 0x0 0xffa00000 0x00040000
22 0x3 0x0 0x0 0xffdf0000 0x00008000
23 0x4 0x0 0x0 0xffa40000 0x00040000
24 0x5 0x0 0x0 0xffa80000 0x00040000
25 0x6 0x0 0x0 0xffac0000 0x00040000>;
26 reg = <0 0xffe05000 0 0x1000>;
30 ranges = <0x0 0x0 0xffe00000 0x100000>;
34 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
[all …]
Dp2020rdb.dts29 reg = <0 0xffe05000 0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
33 0x1 0x0 0x0 0xffa00000 0x00040000
34 0x2 0x0 0x0 0xffb00000 0x00020000>;
36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
61 reg = <0x00080000 0x00380000>;
[all …]
Dp1021rdb-pc.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
60 reg = <0x00080000 0x00380000>;
66 reg = <0x00400000 0x00ac0000>;
73 reg = <0x00ec0000 0x00040000>;
82 reg = <0x00f00000 0x00100000>;
87 nand@1,0 {
[all …]
/Linux-v5.15/sound/pci/
Dsis7019.h17 #define SIS_GCR 0x00
18 #define SIS_GCR_MACRO_POWER_DOWN 0x80000000
19 #define SIS_GCR_MODEM_ENABLE 0x00010000
20 #define SIS_GCR_SOFTWARE_RESET 0x00000001
23 #define SIS_GIER 0x04
24 #define SIS_GIER_MODEM_TIMER_IRQ_ENABLE 0x00100000
25 #define SIS_GIER_MODEM_RX_DMA_IRQ_ENABLE 0x00080000
26 #define SIS_GIER_MODEM_TX_DMA_IRQ_ENABLE 0x00040000
27 #define SIS_GIER_AC97_GPIO1_IRQ_ENABLE 0x00020000
28 #define SIS_GIER_AC97_GPIO0_IRQ_ENABLE 0x00010000
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dat91-sama5d27_som1.dtsi38 pinctrl-0 = <&pinctrl_qspi1_default>;
40 flash@0 {
44 reg = <0>;
50 at91bootstrap@0 {
52 reg = <0x00000000 0x00040000>;
57 reg = <0x00040000 0x000c0000>;
62 reg = <0x00100000 0x00040000>;
67 reg = <0x00140000 0x00040000>;
72 reg = <0x00180000 0x00080000>;
77 reg = <0x00200000 0x00600000>;
[all …]
Dtegra20.dtsi17 memory@0 {
19 reg = <0 0>;
24 reg = <0x40000000 0x40000>;
27 ranges = <0 0x40000000 0x40000>;
30 reg = <0x400 0x3fc00>;
37 reg = <0x50000000 0x00024000>;
49 ranges = <0x54000000 0x54000000 0x04000000>;
53 reg = <0x54040000 0x00040000>;
62 reg = <0x54080000 0x00040000>;
71 reg = <0x540c0000 0x00040000>;
[all …]
Dr8a73a4-ape6evm.dts28 reg = <0 0x40000000 0 0x40000000>;
33 reg = <2 0x00000000 0 0x40000000>;
104 pinctrl-0 = <&keyboard_pins>;
149 reg = <0x1b>;
166 flash@0 {
168 reg = <0x0 0x08000000>;
176 partition@0 {
178 reg = <0x00000000 0x00040000>;
183 reg = <0x00040000 0x00040000>;
188 reg = <0x00080000 0x07f80000>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-host1x.txt91 - reg: csi port number. Valid port numbers are 0 through 5.
105 port@0 with single child 'endpoint' node always a sink.
108 port@0 (required node)
110 - reg: 0
405 reg = <0x50000000 0x00024000>;
406 interrupts = <0 65 0x04 /* mpcore syncpt */
407 0 67 0x04>; /* mpcore general */
415 ranges = <0x54000000 0x54000000 0x04000000>;
419 reg = <0x54040000 0x00040000>;
420 interrupts = <0 68 0x04>;
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_0_default.h26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/sdma1/
Dsdma1_4_0_default.h26 #define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA1_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
/Linux-v5.15/drivers/net/ethernet/qlogic/qed/
Dqed_init_ops.c25 0,
26 0,
27 0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */
28 0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */
29 0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */
30 0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */
31 0x1d02, /* win 6: addr=0x1d02000, size=4096 bytes */
32 0x1d80, /* win 7: addr=0x1d80000, size=4096 bytes */
33 0x1d81, /* win 8: addr=0x1d81000, size=4096 bytes */
34 0x1d82, /* win 9: addr=0x1d82000, size=4096 bytes */
[all …]
/Linux-v5.15/arch/powerpc/platforms/8xx/
Dmpc86xads.h20 #define BCSR1_ETHEN ((uint)0x20000000)
21 #define BCSR1_IRDAEN ((uint)0x10000000)
22 #define BCSR1_RS232EN_1 ((uint)0x01000000)
23 #define BCSR1_PCCEN ((uint)0x00800000)
24 #define BCSR1_PCCVCC0 ((uint)0x00400000)
25 #define BCSR1_PCCVPP0 ((uint)0x00200000)
26 #define BCSR1_PCCVPP1 ((uint)0x00100000)
28 #define BCSR1_RS232EN_2 ((uint)0x00040000)
29 #define BCSR1_PCCVCC1 ((uint)0x00010000)
32 #define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
[all …]
Dmpc885ads.h22 #define BCSR1_ETHEN ((uint)0x20000000)
23 #define BCSR1_IRDAEN ((uint)0x10000000)
24 #define BCSR1_RS232EN_1 ((uint)0x01000000)
25 #define BCSR1_PCCEN ((uint)0x00800000)
26 #define BCSR1_PCCVCC0 ((uint)0x00400000)
27 #define BCSR1_PCCVPP0 ((uint)0x00200000)
28 #define BCSR1_PCCVPP1 ((uint)0x00100000)
30 #define BCSR1_RS232EN_2 ((uint)0x00040000)
31 #define BCSR1_PCCVCC1 ((uint)0x00010000)
34 #define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
[all …]
/Linux-v5.15/arch/powerpc/include/uapi/asm/
Dcputable.h6 #define PPC_FEATURE_32 0x80000000
7 #define PPC_FEATURE_64 0x40000000
8 #define PPC_FEATURE_601_INSTR 0x20000000
9 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10 #define PPC_FEATURE_HAS_FPU 0x08000000
11 #define PPC_FEATURE_HAS_MMU 0x04000000
12 #define PPC_FEATURE_HAS_4xxMAC 0x02000000
13 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14 #define PPC_FEATURE_HAS_SPE 0x00800000
15 #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
[all …]
/Linux-v5.15/arch/sparc/include/asm/
Ddma.h11 #define MAX_DMA_ADDRESS (~0UL)
18 #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
19 #define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
20 #define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
21 #define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
25 #define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
26 #define DMA_VERS0 0x00000000 /* Sunray DMA version */
27 #define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
28 #define DMA_VERS1 0x80000000 /* DMA rev 1 */
29 #define DMA_VERS2 0xa0000000 /* DMA rev 2 */
[all …]
Dpcr.h19 #define PCR_PIC_PRIV 0x00000001 /* PIC access is privileged */
20 #define PCR_STRACE 0x00000002 /* Trace supervisor events */
21 #define PCR_UTRACE 0x00000004 /* Trace user events */
22 #define PCR_N2_HTRACE 0x00000008 /* Trace hypervisor events */
23 #define PCR_N2_TOE_OV0 0x00000010 /* Trap if PIC 0 overflows */
24 #define PCR_N2_TOE_OV1 0x00000020 /* Trap if PIC 1 overflows */
25 #define PCR_N2_MASK0 0x00003fc0
27 #define PCR_N2_SL0 0x0003c000
29 #define PCR_N2_OV0 0x00040000
30 #define PCR_N2_MASK1 0x07f80000
[all …]
/Linux-v5.15/arch/arm/mach-pxa/
Dxcep.c34 #define XCEP_ETH_PHYS (PXA_CS3_PHYS + 0x00000300)
35 #define XCEP_ETH_PHYS_END (PXA_CS3_PHYS + 0x000fffff)
36 #define XCEP_ETH_ATTR (PXA_CS3_PHYS + 0x02000000)
37 #define XCEP_ETH_ATTR_END (PXA_CS3_PHYS + 0x020fffff)
41 #define XCEP_CPLD_BASE 0xf0000000
49 .size = 0x00040000,
50 .offset = 0,
54 .size = 0x00040000,
55 .offset = 0x00040000,
59 .size = 0x00100000,
[all …]
/Linux-v5.15/arch/arm64/boot/dts/nvidia/
Dtegra194.dtsi19 bus@0 {
23 ranges = <0x0 0x0 0x0 0x40000000>;
27 reg = <0x00100000 0xf000>,
28 <0x0010f000 0x1000>;
34 reg = <0x2200000 0x10000>,
35 <0x2210000 0x10000>;
52 reg = <0x02490000 0x10000>;
70 snps,burst-map = <0x7>;
84 ranges = <0x02900000 0x02900000 0x200000>;
90 reg = <0x02930000 0x20000>;
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/
Damd_pcie.h27 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000
28 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000
29 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000
30 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000
31 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5 0x00100000
32 #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000
36 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001
37 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002
38 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004
39 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008
[all …]
/Linux-v5.15/arch/mips/include/asm/mach-au1x00/
Dau1100_mmc.h52 #define SD0_BASE 0xB0600000
53 #define SD1_BASE 0xB0680000
59 #define SD_TXPORT (0x0000)
60 #define SD_RXPORT (0x0004)
61 #define SD_CONFIG (0x0008)
62 #define SD_ENABLE (0x000C)
63 #define SD_CONFIG2 (0x0010)
64 #define SD_BLKSIZE (0x0014)
65 #define SD_STATUS (0x0018)
66 #define SD_DEBUG (0x001C)
[all …]

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