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/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_default.h26 #define mmGRBM_CNTL_DEFAULT 0x00000018
27 #define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020
28 #define mmGRBM_STATUS2_DEFAULT 0x00000000
29 #define mmGRBM_PWR_CNTL_DEFAULT 0x00000000
30 #define mmGRBM_STATUS_DEFAULT 0x00000000
31 #define mmGRBM_STATUS_SE0_DEFAULT 0x00000000
32 #define mmGRBM_STATUS_SE1_DEFAULT 0x00000000
33 #define mmGRBM_SOFT_RESET_DEFAULT 0x00000000
34 #define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100
35 #define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008
[all …]
Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
[all …]
Dgc_10_1_0_default.h26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
[all …]
/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dhdmigt215.c31 const u32 ctrl = 0x40000000 * enable | in gt215_hdmi_ctrl()
32 0x1f000000 /* ??? */ | in gt215_hdmi_ctrl()
42 if (!(ctrl & 0x40000000)) { in gt215_hdmi_ctrl()
43 nvkm_mask(device, 0x61c5a4 + soff, 0x40000000, 0x00000000); in gt215_hdmi_ctrl()
44 nvkm_mask(device, 0x61c53c + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
45 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
46 nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
51 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
53 nvkm_wr32(device, 0x61c528 + soff, avi_infoframe.header); in gt215_hdmi_ctrl()
54 nvkm_wr32(device, 0x61c52c + soff, avi_infoframe.subpack0_low); in gt215_hdmi_ctrl()
[all …]
Dhdmig84.c31 const u32 ctrl = 0x40000000 * enable | in g84_hdmi_ctrl()
32 0x1f000000 /* ??? */ | in g84_hdmi_ctrl()
35 const u32 hoff = head * 0x800; in g84_hdmi_ctrl()
42 if (!(ctrl & 0x40000000)) { in g84_hdmi_ctrl()
43 nvkm_mask(device, 0x6165a4 + hoff, 0x40000000, 0x00000000); in g84_hdmi_ctrl()
44 nvkm_mask(device, 0x61653c + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
45 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
46 nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
51 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
53 nvkm_wr32(device, 0x616528 + hoff, avi_infoframe.header); in g84_hdmi_ctrl()
[all …]
Dhdmigk104.c31 const u32 ctrl = 0x40000000 * enable | in gk104_hdmi_ctrl()
34 const u32 hoff = head * 0x800; in gk104_hdmi_ctrl()
35 const u32 hdmi = head * 0x400; in gk104_hdmi_ctrl()
42 if (!(ctrl & 0x40000000)) { in gk104_hdmi_ctrl()
43 nvkm_mask(device, 0x616798 + hoff, 0x40000000, 0x00000000); in gk104_hdmi_ctrl()
44 nvkm_mask(device, 0x690100 + hdmi, 0x00000001, 0x00000000); in gk104_hdmi_ctrl()
45 nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000000); in gk104_hdmi_ctrl()
46 nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000000); in gk104_hdmi_ctrl()
51 nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000000); in gk104_hdmi_ctrl()
53 nvkm_wr32(device, 0x690008 + hdmi, avi_infoframe.header); in gk104_hdmi_ctrl()
[all …]
Dhdmigf119.c31 const u32 ctrl = 0x40000000 * enable | in gf119_hdmi_ctrl()
34 const u32 hoff = head * 0x800; in gf119_hdmi_ctrl()
41 if (!(ctrl & 0x40000000)) { in gf119_hdmi_ctrl()
42 nvkm_mask(device, 0x616798 + hoff, 0x40000000, 0x00000000); in gf119_hdmi_ctrl()
43 nvkm_mask(device, 0x616730 + hoff, 0x00000001, 0x00000000); in gf119_hdmi_ctrl()
44 nvkm_mask(device, 0x6167a4 + hoff, 0x00000001, 0x00000000); in gf119_hdmi_ctrl()
45 nvkm_mask(device, 0x616714 + hoff, 0x00000001, 0x00000000); in gf119_hdmi_ctrl()
50 nvkm_mask(device, 0x616714 + hoff, 0x00000001, 0x00000000); in gf119_hdmi_ctrl()
52 nvkm_wr32(device, 0x61671c + hoff, avi_infoframe.header); in gf119_hdmi_ctrl()
53 nvkm_wr32(device, 0x616720 + hoff, avi_infoframe.subpack0_low); in gf119_hdmi_ctrl()
[all …]
Dhdmigv100.c29 const u32 ctrl = 0x40000000 * enable | in gv100_hdmi_ctrl()
32 const u32 hoff = head * 0x800; in gv100_hdmi_ctrl()
33 const u32 hdmi = head * 0x400; in gv100_hdmi_ctrl()
40 if (!(ctrl & 0x40000000)) { in gv100_hdmi_ctrl()
41 nvkm_mask(device, 0x6165c0 + hoff, 0x40000000, 0x00000000); in gv100_hdmi_ctrl()
42 nvkm_mask(device, 0x6f0100 + hdmi, 0x00000001, 0x00000000); in gv100_hdmi_ctrl()
43 nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000000); in gv100_hdmi_ctrl()
44 nvkm_mask(device, 0x6f0000 + hdmi, 0x00000001, 0x00000000); in gv100_hdmi_ctrl()
49 nvkm_mask(device, 0x6f0000 + hdmi, 0x00000001, 0x00000000); in gv100_hdmi_ctrl()
51 nvkm_wr32(device, 0x6f0008 + hdmi, avi_infoframe.header); in gv100_hdmi_ctrl()
[all …]
/Linux-v5.10/drivers/net/ethernet/altera/
Daltera_msgdmahw.h19 * bit 15:0 sequence number
22 * bit 15:0 read stride
31 #define MSGDMA_DESC_CTL_SET_CH(x) ((x) & 0xff)
40 #define MSGDMA_DESC_CTL_TR_ERR_IRQ (0xff << 16)
72 #define MSGDMA_DESC_TX_STRIDE (0x00010001)
73 #define MSGDMA_DESC_RX_STRIDE (0x00010001)
81 * bit 15:0 - read fill level
83 u32 resp_fill_level; /* bit 15:0 */
85 * bit 15:0 - read sequence number
92 #define MSGDMA_CSR_STAT_BUSY BIT(0)
[all …]
Daltera_msgdma.c15 return 0; in msgdma_initialize()
36 counter = 0; in msgdma_reset()
58 counter = 0; in msgdma_reset()
108 /* return 0 to indicate transmit is pending */
115 csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_lo)); in msgdma_tx_buffer()
116 csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_hi)); in msgdma_tx_buffer()
118 csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(burst_seq_num)); in msgdma_tx_buffer()
123 return 0; in msgdma_tx_buffer()
128 u32 ready = 0; in msgdma_tx_completions()
134 & 0xffff; in msgdma_tx_completions()
[all …]
/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxgf110.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x0000a9, 1, 0x01, 0x0000ffff },
34 { 0x000038, 1, 0x01, 0x0fac6881 },
35 { 0x00003d, 1, 0x01, 0x00000001 },
36 { 0x0000e8, 8, 0x01, 0x00000400 },
37 { 0x000078, 8, 0x01, 0x00000300 },
38 { 0x000050, 1, 0x01, 0x00000011 },
39 { 0x000058, 8, 0x01, 0x00000008 },
40 { 0x000208, 8, 0x01, 0x00000001 },
41 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
Dctxgf119.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x0000a9, 1, 0x01, 0x0000ffff },
34 { 0x000038, 1, 0x01, 0x0fac6881 },
35 { 0x00003d, 1, 0x01, 0x00000001 },
36 { 0x0000e8, 8, 0x01, 0x00000400 },
37 { 0x000078, 8, 0x01, 0x00000300 },
38 { 0x000050, 1, 0x01, 0x00000011 },
39 { 0x000058, 8, 0x01, 0x00000008 },
40 { 0x000208, 8, 0x01, 0x00000001 },
41 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
Dctxgf108.c34 { 0x001000, 1, 0x01, 0x00000004 },
35 { 0x0000a9, 1, 0x01, 0x0000ffff },
36 { 0x000038, 1, 0x01, 0x0fac6881 },
37 { 0x00003d, 1, 0x01, 0x00000001 },
38 { 0x0000e8, 8, 0x01, 0x00000400 },
39 { 0x000078, 8, 0x01, 0x00000300 },
40 { 0x000050, 1, 0x01, 0x00000011 },
41 { 0x000058, 8, 0x01, 0x00000008 },
42 { 0x000208, 8, 0x01, 0x00000001 },
43 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
/Linux-v5.10/sound/soc/amd/renoir/
Drn_acp3x.h11 #define ACP_PHY_BASE_ADDRESS 0x1240000
12 #define ACP_REG_START 0x1240000
13 #define ACP_REG_END 0x1250200
15 #define ACP_DEVICE_ID 0x15E2
16 #define ACP_POWER_ON 0x00
17 #define ACP_POWER_ON_IN_PROGRESS 0x01
18 #define ACP_POWER_OFF 0x02
19 #define ACP_POWER_OFF_IN_PROGRESS 0x03
20 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
22 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dsdma_v4_0.c74 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
75 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
[all …]
/Linux-v5.10/drivers/media/pci/cx18/
Dcx18-firmware.c17 #define CX18_PROC_SOFT_RESET 0xc70010
18 #define CX18_DDR_SOFT_RESET 0xc70014
19 #define CX18_CLOCK_SELECT1 0xc71000
20 #define CX18_CLOCK_SELECT2 0xc71004
21 #define CX18_HALF_CLOCK_SELECT1 0xc71008
22 #define CX18_HALF_CLOCK_SELECT2 0xc7100C
23 #define CX18_CLOCK_POLARITY1 0xc71010
24 #define CX18_CLOCK_POLARITY2 0xc71014
25 #define CX18_ADD_DELAY_ENABLE1 0xc71018
26 #define CX18_ADD_DELAY_ENABLE2 0xc7101C
[all …]
/Linux-v5.10/arch/alpha/include/asm/
Djensen.h34 #define EISA_INTA (IDENT_ADDR + 0x100000000UL)
39 #define EISA_FEPROM0 (IDENT_ADDR + 0x180000000UL)
40 #define EISA_FEPROM1 (IDENT_ADDR + 0x1A0000000UL)
45 #define EISA_VL82C106 (IDENT_ADDR + 0x1C0000000UL)
50 #define EISA_HAE (IDENT_ADDR + 0x1D0000000UL)
55 #define EISA_SYSCTL (IDENT_ADDR + 0x1E0000000UL)
60 #define EISA_SPARE (IDENT_ADDR + 0x1F0000000UL)
65 #define EISA_MEM (IDENT_ADDR + 0x200000000UL)
70 #define EISA_IO (IDENT_ADDR + 0x300000000UL)
84 * hae needs to be set to 0).
[all …]
/Linux-v5.10/sound/soc/amd/raven/
Dacp3x.h10 #define I2S_SP_INSTANCE 0x01
11 #define I2S_BT_INSTANCE 0x02
14 #define TDM_DISABLE 0
17 #define ACP3x_PHY_BASE_ADDRESS 0x1240000
18 #define ACP3x_I2S_MODE 0
19 #define ACP3x_REG_START 0x1240000
20 #define ACP3x_REG_END 0x1250200
21 #define ACP3x_I2STDM_REG_START 0x1242400
22 #define ACP3x_I2STDM_REG_END 0x1242410
23 #define ACP3x_BT_TDM_REG_START 0x1242800
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/thermal/
Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/Linux-v5.10/include/linux/platform_data/x86/
Dasus-wmi.h9 #define ASUS_WMI_METHODID_SPEC 0x43455053 /* BIOS SPECification */
10 #define ASUS_WMI_METHODID_SFBD 0x44424653 /* Set First Boot Device */
11 #define ASUS_WMI_METHODID_GLCD 0x44434C47 /* Get LCD status */
12 #define ASUS_WMI_METHODID_GPID 0x44495047 /* Get Panel ID?? (Resol) */
13 #define ASUS_WMI_METHODID_QMOD 0x444F4D51 /* Quiet MODe */
14 #define ASUS_WMI_METHODID_SPLV 0x4C425053 /* Set Panel Light Value */
15 #define ASUS_WMI_METHODID_AGFN 0x4E464741 /* Atk Generic FuNction */
16 #define ASUS_WMI_METHODID_SFUN 0x4E554653 /* FUNCtionalities */
17 #define ASUS_WMI_METHODID_SDSP 0x50534453 /* Set DiSPlay output */
18 #define ASUS_WMI_METHODID_GDSP 0x50534447 /* Get DiSPlay output */
[all …]
/Linux-v5.10/include/soc/bcm2835/
Draspberrypi-firmware.h15 RPI_FIRMWARE_STATUS_REQUEST = 0,
16 RPI_FIRMWARE_STATUS_SUCCESS = 0x80000000,
17 RPI_FIRMWARE_STATUS_ERROR = 0x80000001,
37 RPI_FIRMWARE_PROPERTY_END = 0,
38 RPI_FIRMWARE_GET_FIRMWARE_REVISION = 0x00000001,
40 RPI_FIRMWARE_SET_CURSOR_INFO = 0x00008010,
41 RPI_FIRMWARE_SET_CURSOR_STATE = 0x00008011,
43 RPI_FIRMWARE_GET_BOARD_MODEL = 0x00010001,
44 RPI_FIRMWARE_GET_BOARD_REVISION = 0x00010002,
45 RPI_FIRMWARE_GET_BOARD_MAC_ADDRESS = 0x00010003,
[all …]
/Linux-v5.10/sound/pci/ice1712/
Dhoontech.h19 #define ICE1712_SUBDEVICE_STDSP24 0x12141217 /* Hoontech SoundTrack Audio DSP 24 */
20 #define ICE1712_SUBDEVICE_STDSP24_VALUE 0x00010010 /* A dummy id for Hoontech SoundTrack Audio DSP…
21 #define ICE1712_SUBDEVICE_STDSP24_MEDIA7_1 0x16141217 /* Hoontech ST Audio DSP24 Media 7.1 */
22 #define ICE1712_SUBDEVICE_EVENT_EZ8 0x00010001 /* A dummy id for EZ8 */
23 #define ICE1712_SUBDEVICE_STAUDIO_ADCIII 0x00010002 /* A dummy id for STAudio ADCIII */
30 #define ICE1712_STDSP24_0_BOX(r, x) r[0] = ((r[0] & ~3) | ((x)&3))
31 #define ICE1712_STDSP24_0_DAREAR(r, x) r[0] = ((r[0] & ~4) | (((x)&1)<<2))
41 #define ICE1712_STDSP24_SET_ADDR(r, a) r[a&3] = ((r[a&3] & ~0x18) | (((a)&3)<<3))
42 #define ICE1712_STDSP24_CLOCK(r, a, c) r[a&3] = ((r[a&3] & ~0x20) | (((c)&1)<<5))
47 #define ICE1712_STDSP24_DAREAR (1<<0)
[all …]
/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
Dnv50.c35 while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) { in nv50_gpio_reset()
36 static const u32 regs[] = { 0xe100, 0xe28c }; in nv50_gpio_reset()
38 u8 line = (data & 0x0000001f); in nv50_gpio_reset()
39 u8 func = (data & 0x0000ff00) >> 8; in nv50_gpio_reset()
40 u8 defs = !!(data & 0x01000000); in nv50_gpio_reset()
41 u8 unk0 = !!(data & 0x02000000); in nv50_gpio_reset()
42 u8 unk1 = !!(data & 0x04000000); in nv50_gpio_reset()
45 u32 lsh = line & 0x0f; in nv50_gpio_reset()
51 nvkm_gpio_set(gpio, 0, func, line, defs); in nv50_gpio_reset()
53 nvkm_mask(device, reg, 0x00010001 << lsh, val << lsh); in nv50_gpio_reset()
[all …]
/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dnv50.c32 if (*line == 0x04) { in pwm_info()
33 *ctrl = 0x00e100; in pwm_info()
35 *indx = 0; in pwm_info()
37 if (*line == 0x09) { in pwm_info()
38 *ctrl = 0x00e100; in pwm_info()
42 if (*line == 0x10) { in pwm_info()
43 *ctrl = 0x00e28c; in pwm_info()
44 *line = 0; in pwm_info()
45 *indx = 0; in pwm_info()
51 return 0; in pwm_info()
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_default.h26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
35 #define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
[all …]

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