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/Linux-v5.15/arch/arm/boot/dts/
Dbcm5301x.dtsi24 ranges = <0x00000000 0x18000000 0x00001000>;
30 reg = <0x0300 0x100>;
38 reg = <0x0400 0x100>;
42 pinctrl-0 = <&pinmux_uart1>;
49 ranges = <0x00000000 0x19000000 0x00023000>;
53 a9pll: arm_clk@0 {
54 #clock-cells = <0>;
57 reg = <0x00000 0x1000>;
62 reg = <0x20000 0x100>;
67 reg = <0x20200 0x100>;
[all …]
Dmstar-v7.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0x0>;
52 #clock-cells = <0>;
58 #clock-cells = <0>;
65 #clock-cells = <0>;
77 ranges = <0x16001000 0x16001000 0x00007000>,
78 <0x1f000000 0x1f000000 0x00400000>,
79 <0xa0000000 0xa0000000 0x20000>;
83 reg = <0x16001000 0x1000>,
[all …]
Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
/Linux-v5.15/arch/sparc/include/uapi/asm/
Dperfctr.h58 #define PRIV 0x00000001
59 #define SYS 0x00000002
60 #define USR 0x00000004
63 #define CYCLE_CNT 0x00000000
64 #define INSTR_CNT 0x00000010
65 #define DISPATCH0_IC_MISS 0x00000020
66 #define DISPATCH0_STOREBUF 0x00000030
67 #define IC_REF 0x00000080
68 #define DC_RD 0x00000090
69 #define DC_WR 0x000000A0
[all …]
/Linux-v5.15/include/linux/bcma/
Dbcma_driver_arm_c9.h6 #define BCMA_DMU_CRU_USB2_CONTROL 0x0164
7 #define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_MASK 0x00000FFC
9 #define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK 0x00007000
11 #define BCMA_DMU_CRU_CLKSET_KEY 0x0180
12 #define BCMA_DMU_CRU_STRAPS_CTRL 0x02A0
13 #define BCMA_DMU_CRU_STRAPS_CTRL_USB3 0x00000010
14 #define BCMA_DMU_CRU_STRAPS_CTRL_4BYTE 0x00008000
/Linux-v5.15/drivers/gpu/drm/mga/
Dmga_state.c55 MGA_LEN + MGA_EXEC, 0x80000000, in mga_emit_clip_rect()
57 MGA_LEN + MGA_EXEC, 0x80000000); in mga_emit_clip_rect()
59 DMA_BLOCK(MGA_DMAPAD, 0x00000000, in mga_emit_clip_rect()
83 MGA_DMAPAD, 0x00000000, in mga_g200_emit_context()
84 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); in mga_g200_emit_context()
111 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); in mga_g400_emit_context()
119 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; in mga_g200_emit_tex0()
138 MGA_TEXTRANS, 0x0000ffff, in mga_g200_emit_tex0()
139 MGA_TEXTRANSHIGH, 0x0000ffff, MGA_DMAPAD, 0x00000000); in mga_g200_emit_tex0()
147 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; in mga_g400_emit_tex0()
[all …]
/Linux-v5.15/include/uapi/linux/
Dvbox_vmmdev_types.h24 VMMDEVREQ_INVALID_REQUEST = 0,
39 VMMDEVREQ_REPORT_GUEST_INFO2 = 58, /* since version 3.2.0 */
64 VMMDEVREQ_VIDEMODE_SUPPORTED2 = 57, /* since version 3.2.0 */
99 VMMDEVREQ_SIZEHACK = 0x7fffffff
111 #define VMMDEV_REQUESTOR_USR_NOT_GIVEN 0x00000000
113 #define VMMDEV_REQUESTOR_USR_DRV 0x00000001
115 #define VMMDEV_REQUESTOR_USR_DRV_OTHER 0x00000002
117 #define VMMDEV_REQUESTOR_USR_ROOT 0x00000003
119 #define VMMDEV_REQUESTOR_USR_USER 0x00000006
121 #define VMMDEV_REQUESTOR_USR_MASK 0x00000007
[all …]
/Linux-v5.15/drivers/media/pci/cx88/
Dcx88-tvaudio.c52 "Radio deemphasis time constant, 0=None, 1=50us (elsewhere), 2=75us (USA)");
58 } while (0)
96 for (i = 0; l[i].reg; i++) { in set_audio_registers()
120 cx_write(AUD_INIT_LD, 0x0001); in set_audio_start()
121 cx_write(AUD_SOFT_RESET, 0x0001); in set_audio_start()
130 cx_write(AUD_RATE_THRES_DMD, 0x000000C0); in set_audio_finish()
142 cx_write(AUD_I2SCNTL, 0); in set_audio_finish()
143 /* cx_write(AUD_APB_IN_RATE_ADJ, 0); */ in set_audio_finish()
151 cx_write(AUD_SOFT_RESET, 0x0000); in set_audio_finish()
166 {AUD_AFE_12DB_EN, 0x00000001}, in set_audio_standard_BTSC()
[all …]
/Linux-v5.15/drivers/gpu/drm/mcde/
Dmcde_drm.h13 #define MCDE_CR 0x00000000
14 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_SHIFT 0
15 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_MASK 0x0000003F
22 #define MCDE_CONF0 0x00000004
23 #define MCDE_CONF0_SYNCMUX0 BIT(0)
32 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000
34 #define MCDE_CONF0_OUTMUX0_MASK 0x00070000
36 #define MCDE_CONF0_OUTMUX1_MASK 0x00380000
38 #define MCDE_CONF0_OUTMUX2_MASK 0x01C00000
40 #define MCDE_CONF0_OUTMUX3_MASK 0x0E000000
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/ata/
Dnvidia,tegra-ahci.yaml67 - const: sata-0
164 reg = <0x70027000 0x00002000>, /* AHCI */
165 <0x70020000 0x00007000>, /* SATA */
166 <0x70001100 0x00010000>; /* SATA AUX */
/Linux-v5.15/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
Dgp102.c36 return 0; in gp102_sec2_nofw()
55 return 0; in gp102_sec2_acr_bootstrap_falcon_callback()
82 falcon->func->emem_addr, sizeof(args), 0); in gp102_sec2_acr_boot()
84 return 0; in gp102_sec2_acr_boot()
146 for (i = 0; i < ARRAY_SIZE(msg.queue_info); i++) { in gp102_sec2_initmsg()
160 return 0; in gp102_sec2_initmsg()
168 u32 disp = nvkm_falcon_rd32(falcon, 0x01c); in gp102_sec2_intr()
169 u32 intr = nvkm_falcon_rd32(falcon, 0x008) & disp & ~(disp >> 16); in gp102_sec2_intr()
171 if (intr & 0x00000040) { in gp102_sec2_intr()
173 nvkm_falcon_wr32(falcon, 0x004, 0x00000040); in gp102_sec2_intr()
[all …]
/Linux-v5.15/drivers/net/ethernet/intel/iavf/
Diavf_register.h7 #define IAVF_VF_ARQBAH1 0x00006000 /* Reset: EMPR */
8 #define IAVF_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */
9 #define IAVF_VF_ARQH1 0x00007400 /* Reset: EMPR */
10 #define IAVF_VF_ARQH1_ARQH_SHIFT 0
11 #define IAVF_VF_ARQH1_ARQH_MASK IAVF_MASK(0x3FF, IAVF_VF_ARQH1_ARQH_SHIFT)
12 #define IAVF_VF_ARQLEN1 0x00008000 /* Reset: EMPR */
14 #define IAVF_VF_ARQLEN1_ARQVFE_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQVFE_SHIFT)
16 #define IAVF_VF_ARQLEN1_ARQOVFL_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQOVFL_SHIFT)
18 #define IAVF_VF_ARQLEN1_ARQCRIT_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQCRIT_SHIFT)
20 #define IAVF_VF_ARQLEN1_ARQENABLE_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQENABLE_SHIFT)
[all …]
/Linux-v5.15/arch/arm/nwfpe/
Dfpsr.h32 #define MASK_SYSID 0xff000000
33 #define BIT_HARDWARE 0x80000000
34 #define FP_EMULATOR 0x01000000 /* System ID for emulator */
35 #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */
40 #define MASK_TRAP_ENABLE 0x00ff0000
41 #define MASK_TRAP_ENABLE_STRICT 0x001f0000
42 #define BIT_IXE 0x00100000 /* inexact exception enable */
43 #define BIT_UFE 0x00080000 /* underflow exception enable */
44 #define BIT_OFE 0x00040000 /* overflow exception enable */
45 #define BIT_DZE 0x00020000 /* divide by zero exception enable */
[all …]
/Linux-v5.15/arch/powerpc/sysdev/
Dfsl_rio.h32 #define RIO_MAINT_WIN_SIZE 0x400000
33 #define RIO_LTLEDCSR 0x0608
35 #define DOORBELL_ROWAR_EN 0x80000000
36 #define DOORBELL_ROWAR_TFLOWLV 0x08000000 /* highest priority level */
37 #define DOORBELL_ROWAR_PCI 0x02000000 /* PCI window */
38 #define DOORBELL_ROWAR_NREAD 0x00040000 /* NREAD */
39 #define DOORBELL_ROWAR_MAINTRD 0x00070000 /* maintenance read */
40 #define DOORBELL_ROWAR_RES 0x00002000 /* wrtpy: reserved */
41 #define DOORBELL_ROWAR_MAINTWD 0x00007000
42 #define DOORBELL_ROWAR_SIZE 0x0000000b /* window size is 4k */
[all …]
/Linux-v5.15/include/soc/fsl/qe/
Dqe.h32 QE_CLK_NONE = 0,
131 return 0; in cpm_muram_dma()
226 return 0; in qe_alive_during_sleep()
270 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
283 __be32 traps[16]; /* Trap addresses, 0 == ignore */
327 #define BD_STATUS_MASK 0xffff0000
328 #define BD_LENGTH_MASK 0x0000ffff
336 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
337 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
338 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
[all …]
/Linux-v5.15/arch/powerpc/include/asm/
Ddcr-regs.h29 #define DCRN_CPR0_CONFIG_ADDR 0xc
30 #define DCRN_CPR0_CONFIG_DATA 0xd
33 #define DCRN_SDR0_CONFIG_ADDR 0xe
34 #define DCRN_SDR0_CONFIG_DATA 0xf
36 #define SDR0_PFC0 0x4100
37 #define SDR0_PFC1 0x4101
38 #define SDR0_PFC1_EPS 0x1c00000
40 #define SDR0_PFC1_RMII 0x02000000
41 #define SDR0_MFR 0x4300
42 #define SDR0_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
[all …]
D8xx_immap.h29 char res2[0xc];
31 char res3[0x4c];
53 char res1[0x20];
83 char res1[0x24];
92 char res3[0x80];
98 #define BR_BA_MSK 0xffff8000 /* Base Address Mask */
99 #define BR_AT_MSK 0x00007000 /* Address Type Mask */
100 #define BR_PS_MSK 0x00000c00 /* Port Size Mask */
101 #define BR_PS_32 0x00000000 /* 32 bit port size */
102 #define BR_PS_16 0x00000800 /* 16 bit port size */
[all …]
/Linux-v5.15/arch/powerpc/boot/
Ddcr.h8 asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
12 asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
16 asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
21 asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
25 #define DCRN_SDRAM0_CFGADDR 0x010
26 #define DCRN_SDRAM0_CFGDATA 0x011
35 #define SDRAM0_B0CR 0x40
36 #define SDRAM0_B1CR 0x44
37 #define SDRAM0_B2CR 0x48
38 #define SDRAM0_B3CR 0x4c
[all …]
/Linux-v5.15/arch/mips/include/asm/txx9/
Drbtx4939.h19 #define RBTX4939_IOC_REG_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
20 #define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
21 #define RBTX4939_IOC_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000002)
22 #define RBTX4939_CONFIG1_ADDR (IO_BASE + TXX9_CE(1) + 0x00000004)
23 #define RBTX4939_CONFIG2_ADDR (IO_BASE + TXX9_CE(1) + 0x00000006)
24 #define RBTX4939_CONFIG3_ADDR (IO_BASE + TXX9_CE(1) + 0x00000008)
25 #define RBTX4939_CONFIG4_ADDR (IO_BASE + TXX9_CE(1) + 0x0000000a)
26 #define RBTX4939_USTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00001000)
27 #define RBTX4939_UDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001002)
28 #define RBTX4939_BDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001004)
[all …]
Drbtx4938.h19 #define RBTX4938_FPGA_REG_ADDR (IO_BASE + TXX9_CE(2) + 0x00000000)
20 #define RBTX4938_FPGA_REV_ADDR (IO_BASE + TXX9_CE(2) + 0x00000002)
21 #define RBTX4938_CONFIG1_ADDR (IO_BASE + TXX9_CE(2) + 0x00000004)
22 #define RBTX4938_CONFIG2_ADDR (IO_BASE + TXX9_CE(2) + 0x00000006)
23 #define RBTX4938_CONFIG3_ADDR (IO_BASE + TXX9_CE(2) + 0x00000008)
24 #define RBTX4938_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
25 #define RBTX4938_DIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001002)
26 #define RBTX4938_BDIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001004)
27 #define RBTX4938_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
28 #define RBTX4938_IMASK2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002002)
[all …]
/Linux-v5.15/arch/powerpc/platforms/52xx/
Dlite5200.c60 cdm = of_iomap(np, 0); in lite5200_fix_clock_config()
69 out_8(&cdm->ext_48mhz_en, 0x00); in lite5200_fix_clock_config()
70 out_8(&cdm->fd_enable, 0x01); in lite5200_fix_clock_config()
71 if (in_be32(&cdm->rstcfg) & 0x40) /* Assumes 33Mhz clock */ in lite5200_fix_clock_config()
72 out_be16(&cdm->fd_counters, 0x0001); in lite5200_fix_clock_config()
74 out_be16(&cdm->fd_counters, 0x5555); in lite5200_fix_clock_config()
95 gpio = of_iomap(np, 0); in lite5200_fix_port_config()
106 port_config &= ~0x00800000; /* 48Mhz internal, pin is GPIO */ in lite5200_fix_port_config()
108 port_config &= ~0x00007000; /* USB port : Differential mode */ in lite5200_fix_port_config()
109 port_config |= 0x00001000; /* USB 1 only */ in lite5200_fix_port_config()
[all …]
/Linux-v5.15/drivers/net/wireless/ath/ath9k/
Dreg_mci.h20 #define AR_MCI_COMMAND0 0x1800
21 #define AR_MCI_COMMAND0_HEADER 0xFF
22 #define AR_MCI_COMMAND0_HEADER_S 0
23 #define AR_MCI_COMMAND0_LEN 0x1f00
25 #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000
28 #define AR_MCI_COMMAND1 0x1804
30 #define AR_MCI_COMMAND2 0x1808
31 #define AR_MCI_COMMAND2_RESET_TX 0x01
32 #define AR_MCI_COMMAND2_RESET_TX_S 0
33 #define AR_MCI_COMMAND2_RESET_RX 0x02
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/
Dcyan_skillfish_ip_offset.h39 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0 } } } };
45 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0, 0, 0, 0 } },
46 { { 0x00016E00, 0, 0, 0, 0 } },
47 { { 0x00017000, 0, 0, 0, 0 } },
48 { { 0x00017200, 0, 0, 0, 0 } },
[all …]
/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dintel_renderstate.c46 } while (0)
52 unsigned int i = 0, reloc_index = 0; in render_state_setup()
69 rodata->batch[i + 1] != 0) in render_state_setup()
107 * 1 3 subslices enabled (3x6) - 0x00777000 (9+9) in render_state_setup()
108 * 2 ss0 disabled (2x6) - 0x00777000 (3+9) in render_state_setup()
109 * 3 ss1 disabled (2x6) - 0x00770000 (6+6) in render_state_setup()
110 * 4 ss2 disabled (2x6) - 0x00007000 (9+3) in render_state_setup()
112 u32 eu_pool_config = 0x00777000; in render_state_setup()
117 OUT_BATCH(d, i, 0); in render_state_setup()
118 OUT_BATCH(d, i, 0); in render_state_setup()
[all …]
/Linux-v5.15/drivers/gpu/drm/msm/dsi/
Ddsi.xml.h58 NON_BURST_SYNCH_PULSE = 0,
64 VID_DST_FORMAT_RGB565 = 0,
71 SWAP_RGB = 0,
80 TRIGGER_NONE = 0,
89 CMD_DST_FORMAT_RGB111 = 0,
98 LANE_SWAP_0123 = 0,
109 VIDEO_CONFIG_18BPP = 0,
114 VID_PRBS = 0,
121 CMD_MDP_PRBS = 0,
128 CMD_DMA_PRBS = 0,
[all …]

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