/Linux-v5.10/arch/arm/boot/dts/ |
D | tegra20-acer-a500-picasso.dts | 36 memory@0 { 37 reg = <0x00000000 0x40000000>; 47 reg = <0x2ffe0000 0x10000>; /* 64kB */ 48 console-size = <0x8000>; /* 32kB */ 49 record-size = <0x400>; /* 1kB */ 55 alloc-ranges = <0x30000000 0x10000000>; 56 size = <0x10000000>; /* 256MiB */ 67 port@0 { 91 pinctrl-0 = <&state_default>; 406 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; [all …]
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D | tegra124-nyan-blaze-emc.dtsi | 78 nvidia,emc-auto-cal-config = <0xa1430000>; 79 nvidia,emc-auto-cal-config2 = <0x00000000>; 80 nvidia,emc-auto-cal-config3 = <0x00000000>; 81 nvidia,emc-auto-cal-interval = <0x001fffff>; 82 nvidia,emc-bgbias-ctl0 = <0x00000008>; 83 nvidia,emc-cfg = <0x73240000>; 84 nvidia,emc-cfg-2 = <0x000008c5>; 85 nvidia,emc-ctt-term-ctrl = <0x00000802>; 86 nvidia,emc-mode-1 = <0x80100003>; 87 nvidia,emc-mode-2 = <0x80200008>; [all …]
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D | tegra124-apalis-emc.dtsi | 94 nvidia,emc-auto-cal-config = <0xa1430000>; 95 nvidia,emc-auto-cal-config2 = <0x00000000>; 96 nvidia,emc-auto-cal-config3 = <0x00000000>; 97 nvidia,emc-auto-cal-interval = <0x001fffff>; 98 nvidia,emc-bgbias-ctl0 = <0x00000008>; 99 nvidia,emc-cfg = <0x73240000>; 100 nvidia,emc-cfg-2 = <0x000008c5>; 101 nvidia,emc-ctt-term-ctrl = <0x00000802>; 102 nvidia,emc-mode-1 = <0x80100003>; 103 nvidia,emc-mode-2 = <0x80200008>; [all …]
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D | tegra124-jetson-tk1-emc.dtsi | 89 nvidia,emc-auto-cal-config = <0xa1430000>; 90 nvidia,emc-auto-cal-config2 = <0x00000000>; 91 nvidia,emc-auto-cal-config3 = <0x00000000>; 92 nvidia,emc-auto-cal-interval = <0x001fffff>; 93 nvidia,emc-bgbias-ctl0 = <0x00000008>; 94 nvidia,emc-cfg = <0x73240000>; 95 nvidia,emc-cfg-2 = <0x000008c5>; 96 nvidia,emc-ctt-term-ctrl = <0x00000802>; 97 nvidia,emc-mode-1 = <0x80100003>; 98 nvidia,emc-mode-2 = <0x80200008>; [all …]
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D | tegra20-colibri.dtsi | 11 memory@0 { 17 reg = <0x00000000 0x10000000>; 32 pinctrl-0 = <&state_default>; 424 <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>; 426 <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; 440 nand@0 { 441 reg = <0>; 449 wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; 477 reg = <0x34>; 506 regulator-name = "VDD_CPU_1.0V"; [all …]
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D | tegra124-nyan-big-emc.dtsi | 229 nvidia,emc-auto-cal-config = <0xa1430000>; 230 nvidia,emc-auto-cal-config2 = <0x00000000>; 231 nvidia,emc-auto-cal-config3 = <0x00000000>; 232 nvidia,emc-auto-cal-interval = <0x001fffff>; 233 nvidia,emc-bgbias-ctl0 = <0x00000008>; 234 nvidia,emc-cfg = <0x73240000>; 235 nvidia,emc-cfg-2 = <0x000008c5>; 236 nvidia,emc-ctt-term-ctrl = <0x00000802>; 237 nvidia,emc-mode-1 = <0x80100003>; 238 nvidia,emc-mode-2 = <0x80200008>; [all …]
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D | tegra30-asus-nexus7-grouper-memory-timings.dtsi | 5 emc-timings-0 { 6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */ 12 0x00020001 /* MC_EMEM_ARB_CFG */ 13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ 17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ 19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ [all …]
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D | tegra20-paz00.dts | 24 memory@0 { 25 reg = <0x00000000 0x20000000>; 51 pinctrl-0 = <&state_default>; 287 reg = <0x1e>; 300 reg = <0x7000c500 0x100>; 303 #size-cells = <0>; 317 emc-tables@0 { 318 nvidia,ram-code = <0x0>; 320 #size-cells = <0>; 326 nvidia,emc-registers = <0x0000000a 0x00000016 [all …]
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/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/bif/ |
D | bif_3_0_sh_mask.h | 26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L 27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007 28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L 29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001 30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L 31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000 32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L 33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005 34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L 35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002 [all …]
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/Linux-v5.10/drivers/gpu/drm/amd/include/ |
D | vega10_enum.h | 51 GDS_PERF_SEL_DS_ADDR_CONFL = 0, 184 NO_FORCE_REQUEST = 0x00000000, 185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 187 FORCE_SHUT_DOWN_REQUEST = 0x00000003, 195 NO_FORCE_REQ = 0x00000000, 196 FORCE_LIGHT_SLEEP_REQ = 0x00000001, 204 ENABLE_MEM_PWR_CTRL = 0x00000000, 205 DISABLE_MEM_PWR_CTRL = 0x00000001, 213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, [all …]
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D | navi10_enum.h | 51 GDS_PERF_SEL_DS_ADDR_CONFL = 0, 184 GATCL1_TYPE_NORMAL = 0x00000000, 185 GATCL1_TYPE_SHOOTDOWN = 0x00000001, 186 GATCL1_TYPE_BYPASS = 0x00000002, 194 UTCL1_TYPE_NORMAL = 0x00000000, 195 UTCL1_TYPE_SHOOTDOWN = 0x00000001, 196 UTCL1_TYPE_BYPASS = 0x00000002, 204 UTCL1_XNACK_SUCCESS = 0x00000000, 205 UTCL1_XNACK_RETRY = 0x00000001, 206 UTCL1_XNACK_PRT = 0x00000002, [all …]
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/Linux-v5.10/tools/testing/selftests/powerpc/vphn/ |
D | test-vphn.c | 29 0xffffffffffffffff, 30 0xffffffffffffffff, 31 0xffffffffffffffff, 32 0xffffffffffffffff, 33 0xffffffffffffffff, 34 0xffffffffffffffff, 37 0x00000000 43 0x8001ffffffffffff, 44 0xffffffffffffffff, 45 0xffffffffffffffff, [all …]
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/Linux-v5.10/drivers/gpu/drm/nouveau/include/nvhw/class/ |
D | cla0b5.h | 27 #define NVA0B5_SET_SRC_PHYS_MODE (0x00000260) 28 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0 29 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) 30 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) 31 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) 32 #define NVA0B5_SET_DST_PHYS_MODE (0x00000264) 33 #define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0 34 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) 35 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) 36 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) [all …]
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D | cl837d.h | 28 #define NV837D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0… 29 #define NV837D_SOR_SET_CONTROL_OWNER 3:0 30 #define NV837D_SOR_SET_CONTROL_OWNER_NONE (0x00000000) 31 #define NV837D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) 32 #define NV837D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) 34 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) 35 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) 36 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) 37 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) 39 #define NV837D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) [all …]
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D | cl507d.h | 27 #define NV_DISP_CORE_NOTIFIER_1 0x00000000 28 #define NV_DISP_CORE_NOTIFIER_1_SIZEOF 0x00000054 29 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0 0x00000000 30 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE 0:0 31 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE 0x00000000 32 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE 0x00000001 35 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1 0x00000001 36 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE 0:0 37 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE 0x00000000 38 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE 0x00000001 [all …]
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D | clc37e.h | 28 #define NVC37E_UPDATE (0x00000200) 30 #define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) 31 #define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) 32 #define NVC37E_SET_SEMAPHORE_CONTROL (0x0000020C) 33 #define NVC37E_SET_SEMAPHORE_CONTROL_OFFSET 7:0 34 #define NVC37E_SET_SEMAPHORE_ACQUIRE (0x00000210) 35 #define NVC37E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 36 #define NVC37E_SET_SEMAPHORE_RELEASE (0x00000214) 37 #define NVC37E_SET_SEMAPHORE_RELEASE_VALUE 31:0 38 #define NVC37E_SET_CONTEXT_DMA_SEMAPHORE (0x00000218) [all …]
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D | cl5039.h | 26 …_SET_OBJECT 0x0000 27 …_SET_OBJECT_POINTER 15:0 29 …_NO_OPERATION 0x0100 30 …_NO_OPERATION_V 31:0 32 …_SET_CONTEXT_DMA_NOTIFY 0x0180 33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0 35 …_SET_CONTEXT_DMA_BUFFER_IN 0x0184 36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0 38 …_SET_CONTEXT_DMA_BUFFER_OUT 0x0188 39 …_SET_CONTEXT_DMA_BUFFER_OUT_HANDLE 31:0 [all …]
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/Linux-v5.10/drivers/gpu/drm/ast/ |
D | ast_dram_tables.h | 12 { 0x0108, 0x00000000 }, 13 { 0x0120, 0x00004a21 }, 14 { 0xFF00, 0x00000043 }, 15 { 0x0000, 0xFFFFFFFF }, 16 { 0x0004, 0x00000089 }, 17 { 0x0008, 0x22331353 }, 18 { 0x000C, 0x0d07000b }, 19 { 0x0010, 0x11113333 }, 20 { 0x0020, 0x00110350 }, 21 { 0x0028, 0x1e0828f0 }, [all …]
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/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/ |
D | tonga_sdma_pkt_open.h | 26 #define SDMA_OP_NOP 0 41 #define SDMA_SUBOP_TIMESTAMP_SET 0 44 #define SDMA_SUBOP_COPY_LINEAR 0 50 #define SDMA_SUBOP_WRITE_LINEAR 0 54 #define SDMA_PKT_HEADER_op_offset 0 55 #define SDMA_PKT_HEADER_op_mask 0x000000FF 56 #define SDMA_PKT_HEADER_op_shift 0 60 #define SDMA_PKT_HEADER_sub_op_offset 0 61 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF 71 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 [all …]
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D | iceland_sdma_pkt_open.h | 26 #define SDMA_OP_NOP 0 41 #define SDMA_SUBOP_TIMESTAMP_SET 0 44 #define SDMA_SUBOP_COPY_LINEAR 0 50 #define SDMA_SUBOP_WRITE_LINEAR 0 54 #define SDMA_PKT_HEADER_op_offset 0 55 #define SDMA_PKT_HEADER_op_mask 0x000000FF 56 #define SDMA_PKT_HEADER_op_shift 0 60 #define SDMA_PKT_HEADER_sub_op_offset 0 61 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF 71 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 [all …]
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D | navi10_sdma_pkt_open.h | 26 #define SDMA_OP_NOP 0 44 #define SDMA_SUBOP_TIMESTAMP_SET 0 47 #define SDMA_SUBOP_COPY_LINEAR 0 60 #define SDMA_SUBOP_WRITE_LINEAR 0 63 #define SDMA_SUBOP_PTEPDE_GEN 0 73 #define SDMA_OP_AQL_COPY 0 74 #define SDMA_OP_AQL_BARRIER_OR 0 77 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16) 81 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11) 89 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2) [all …]
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/Linux-v5.10/drivers/video/fbdev/nvidia/ |
D | nv_dma.h | 51 #define SURFACE_FORMAT 0x00000300 52 #define SURFACE_FORMAT_DEPTH8 0x00000001 53 #define SURFACE_FORMAT_DEPTH15 0x00000002 54 #define SURFACE_FORMAT_DEPTH16 0x00000004 55 #define SURFACE_FORMAT_DEPTH24 0x00000006 56 #define SURFACE_PITCH 0x00000304 57 #define SURFACE_PITCH_SRC 15:0 59 #define SURFACE_OFFSET_SRC 0x00000308 60 #define SURFACE_OFFSET_DST 0x0000030C 62 #define ROP_SET 0x00002300 [all …]
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/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
D | ramnv49.c | 30 u32 size = nvkm_rd32(device, 0x10020c) & 0xff000000; in nv49_ram_new() 31 u32 fb914 = nvkm_rd32(device, 0x100914); in nv49_ram_new() 35 switch (fb914 & 0x00000003) { in nv49_ram_new() 36 case 0x00000000: type = NVKM_RAM_TYPE_DDR1 ; break; in nv49_ram_new() 37 case 0x00000001: type = NVKM_RAM_TYPE_DDR2 ; break; in nv49_ram_new() 38 case 0x00000002: type = NVKM_RAM_TYPE_GDDR3; break; in nv49_ram_new() 39 case 0x00000003: break; in nv49_ram_new() 46 (*pram)->parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1; in nv49_ram_new() 47 return 0; in nv49_ram_new()
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/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
D | gmc_6_0_sh_mask.h | 26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L 27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008 28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L 29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010 30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L 31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000 32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L 33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002 34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L 35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001 [all …]
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/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
D | uvd_4_0_sh_mask.h | 26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L 27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000 28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L 29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001 30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL 31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002 32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL 33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002 34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L 35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006 [all …]
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