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/Linux-v6.1/drivers/gpu/drm/nouveau/include/nvhw/class/
Dcl502d.h2 * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_WAIT_FOR_IDLE 0x0110
30 …_WAIT_FOR_IDLE_V 31:0
32 …_SET_DST_CONTEXT_DMA 0x0184
33 …_SET_DST_CONTEXT_DMA_HANDLE 31:0
35 …_SET_SRC_CONTEXT_DMA 0x0188
36 …_SET_SRC_CONTEXT_DMA_HANDLE 31:0
38 …_SET_SEMAPHORE_CONTEXT_DMA 0x018c
[all …]
Dcl902d.h2 * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_CLASS_ID 15:0
30 …_WAIT_FOR_IDLE 0x0110
31 …_WAIT_FOR_IDLE_V 31:0
33 …_SET_DST_FORMAT 0x0200
34 …_SET_DST_FORMAT_V 7:0
35 …_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF
36 …_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0
37 …_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF
[all …]
Dcl5039.h2 * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_NO_OPERATION 0x0100
30 …_NO_OPERATION_V 31:0
32 …_SET_CONTEXT_DMA_NOTIFY 0x0180
33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
35 …_SET_CONTEXT_DMA_BUFFER_IN 0x0184
36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
38 …_SET_CONTEXT_DMA_BUFFER_OUT 0x0188
[all …]
/Linux-v6.1/arch/powerpc/lib/
Dfeature-fixups-test.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 #include <asm/feature-fixups.h>
9 #include <asm/asm-compat.h>
10 #include <asm/ppc-opcode.h>
48 or 31,31,31
52 or 31,31,31
68 or 31,31,31
69 or 31,31,31
83 or 31,31,31
84 or 31,31,31
[all …]
/Linux-v6.1/drivers/net/ethernet/mellanox/mlx5/core/steering/
Ddr_ste_v2.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
7 DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_0 = 0x00,
8 DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_1 = 0x01,
9 DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_2 = 0x02,
10 DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_0 = 0x08,
11 DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_1 = 0x09,
12 DR_STE_V2_ACTION_MDFY_FLD_L3_OUT_0 = 0x0e,
13 DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0 = 0x18,
14 DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_1 = 0x19,
15 DR_STE_V2_ACTION_MDFY_FLD_IPV4_OUT_0 = 0x40,
[all …]
/Linux-v6.1/arch/powerpc/xmon/
Dppc-opc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
27 inserting operands into instructions and vice-versa is kept in this
135 #define UNUSED 0
136 { 0, 0, NULL, NULL, 0 },
142 #define BI_MASK (0x1f << 16)
143 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
148 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
152 #define BB_MASK (0x1f << 11)
[all …]
/Linux-v6.1/drivers/net/dsa/sja1105/
Dsja1105_ethtool.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
90 /* MAC-Level Diagnostic Counters */
94 .offset = 0,
95 .start = 31,
101 .offset = 0x0,
108 .offset = 0x0,
115 .offset = 0x0,
117 .end = 0,
119 /* MAC-Level Diagnostic Flags */
[all …]
/Linux-v6.1/Documentation/userspace-api/media/v4l/
Dpixfmt-meta-vsp1-hgo.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
[all …]
Dpixfmt-meta-vsp1-hgt.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgt:
9 Renesas R-Car VSP1 2-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1
16 2-D Histogram (HGT) engine.
28 The Saturation position **n** (0 - 31) of the bucket in the matrix is
33 The Hue position **m** (0 - 5) of the bucket in the matrix depends on
43 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5
50 5U 0L 0U 1L 1U 2L 2U 3L 3U 4L 4U 5L 5U 0L
51 <0..............................Hue Value............................255>
[all …]
/Linux-v6.1/drivers/video/fbdev/nvidia/
Dnv_dma.h8 |* hereby granted a nonexclusive, royalty-free copyright license to *|
11 |* Any use of this source code must include, in the user documenta- *|
19 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
21 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
23 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
24 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
33 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
35 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
42 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
43 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
[all …]
/Linux-v6.1/drivers/net/wireless/mediatek/mt76/
Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
23 MT_HIF0 = 0x0,
25 MT_LMAC_AC00 = 0x0,
29 MT_LMAC_ALTX0 = 0x10,
35 #define MT_TXD0_Q_IDX GENMASK(31, 25)
38 #define MT_TXD0_TX_BYTES GENMASK(15, 0)
40 #define MT_TXD1_LONG_FORMAT BIT(31)
50 #define MT_TXD1_WLAN_IDX GENMASK(9, 0)
52 #define MT_TXD2_FIX_RATE BIT(31)
66 #define MT_TXD2_SUB_TYPE GENMASK(3, 0)
[all …]
/Linux-v6.1/arch/mips/include/asm/octeon/
Dcvmx-ciu2-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 …ine CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * …
32 …ine CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * …
33 … CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * …
34 …CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * …
35 …CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * …
36 …_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * …
37 …_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * …
[all …]
Dcvmx-pexp-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31…
32 #define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
33 #define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
34 #define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
35 #define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
36 #define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
37 #define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
[all …]
/Linux-v6.1/drivers/net/ipa/reg/
Dipa_reg-v3.1.c1 // SPDX-License-Identifier: GPL-2.0
11 [COMP_CFG_ENABLE] = BIT(0),
16 /* Bits 5-31 reserved */
19 IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
22 [CLKON_RX] = BIT(0),
39 /* Bits 17-31 reserved */
42 IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
45 [ROUTE_DIS] = BIT(0),
50 /* Bits 22-23 reserved */
52 /* Bits 25-31 reserved */
[all …]
Dipa_reg-v3.5.1.c1 // SPDX-License-Identifier: GPL-2.0
11 [COMP_CFG_ENABLE] = BIT(0),
16 /* Bits 5-31 reserved */
19 IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
22 [CLKON_RX] = BIT(0),
44 /* Bits 22-31 reserved */
47 IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
50 [ROUTE_DIS] = BIT(0),
55 /* Bits 22-23 reserved */
57 /* Bits 25-31 reserved */
[all …]
Dipa_reg-v4.2.c1 // SPDX-License-Identifier: GPL-2.0
11 /* Bit 0 reserved */
29 /* Bits 21-31 reserved */
32 IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
35 [CLKON_RX] = BIT(0),
65 /* Bits 30-31 reserved */
68 IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
71 [ROUTE_DIS] = BIT(0),
76 /* Bits 22-23 reserved */
78 /* Bits 25-31 reserved */
[all …]
Dipa_reg-v4.11.c1 // SPDX-License-Identifier: GPL-2.0
11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
34 /* Bits 24-29 reserved */
36 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
39 IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
42 [CLKON_RX] = BIT(0),
73 [DRBIP] = BIT(31),
76 IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
79 [ROUTE_DIS] = BIT(0),
84 /* Bits 22-23 reserved */
[all …]
Dipa_reg-v4.5.c1 // SPDX-License-Identifier: GPL-2.0
11 /* Bit 0 reserved */
30 /* Bits 22-31 reserved */
33 IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
36 [CLKON_RX] = BIT(0),
67 /* Bit 31 reserved */
70 IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
73 [ROUTE_DIS] = BIT(0),
78 /* Bits 22-23 reserved */
80 /* Bits 25-31 reserved */
[all …]
Dipa_reg-v4.9.c1 // SPDX-License-Identifier: GPL-2.0
11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
33 /* Bits 25-29 reserved */
35 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
38 IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
41 [CLKON_RX] = BIT(0),
72 [DRBIP] = BIT(31),
75 IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
78 [ROUTE_DIS] = BIT(0),
83 /* Bits 22-23 reserved */
[all …]
/Linux-v6.1/arch/arc/include/asm/
Dbitops.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
23 * This is a pure count, so (1-32) or (0-31) doesn't apply
24 * It could be 0 to 32, based on num of 0's in there
25 * clz(0x8000_0000) = 0, clz(0xFFFF_FFFF)=0, clz(0) = 32, clz(1) = 31
32 " norm.f %0, %1 \n" in clz()
33 " mov.n %0, 0 \n" in clz()
34 " add.p %0, %0, 1 \n" in clz()
47 return 0; in constant_fls()
48 if (!(x & 0xffff0000u)) { in constant_fls()
[all …]
/Linux-v6.1/arch/alpha/include/asm/
Dxor.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-alpha/xor.h
5 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
51 .prologue 0 \n\
55 ldq $0,0($17) \n\
56 ldq $1,0($18) \n\
73 xor $0,$1,$0 # 7 cycles from $1 load \n\
77 stq $0,0($17) \n\
106 .prologue 0 \n\
110 ldq $0,0($17) \n\
[all …]
/Linux-v6.1/drivers/net/wireless/mediatek/mt76/mt7615/
Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_LENGTH GENMASK(15, 0)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
34 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
36 #define MT_RXD1_FIRST_AMSDU_FRAME GENMASK(1, 0)
38 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
51 #define MT_RXD1_NORMAL_HTC_VLD BIT(0)
53 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
71 #define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)
73 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
[all …]
/Linux-v6.1/drivers/net/wireless/mediatek/mt76/mt7603/
Dmac.h1 /* SPDX-License-Identifier: ISC */
6 #define MT_RXD0_LENGTH GENMASK(15, 0)
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
18 PKT_TYPE_TXS = 0,
27 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
39 #define MT_RXD1_NORMAL_HTC_VLD BIT(0)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
59 #define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)
61 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
70 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
[all …]
Dregs.h1 /* SPDX-License-Identifier: ISC */
6 #define MT_HW_REV 0x1000
7 #define MT_HW_CHIPID 0x1008
8 #define MT_TOP_MISC2 0x1134
10 #define MT_MCU_BASE 0x2000
13 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
14 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
17 #define MT_MCU_PCIE_REMAP_2 MT_MCU(0x504)
18 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
[all …]
/Linux-v6.1/drivers/infiniband/hw/irdma/
Ddefs.h1 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
17 #define IRDMA_IRD_HW_SIZE_4 0
24 IRDMA_ANY_PROTOCOL = 0,
29 #define IRDMA_QP_STATE_INVALID 0
54 #define RDMA_OPCODE_M 0x0f
57 #define CQE_MAJOR_DRV 0x8000
68 #define IRDMA_AE_SOURCE_RSVD 0x0
69 #define IRDMA_AE_SOURCE_RQ 0x1
70 #define IRDMA_AE_SOURCE_RQ_0011 0x3
[all …]

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