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/Linux-v5.15/arch/x86/platform/ce4100/
Dfalconfalls.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "intel,ce4100-cp";
32 ioapic1: interrupt-controller@fec00000 {
[all …]
/Linux-v5.15/arch/xtensa/variants/de212/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
40 /* Save area for non-coprocessor optional and custom (TIE) state: */
45 #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
58 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
59 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
62 * galign = group byte alignment (power of 2) (galign >= align)
63 * align = register byte alignment (power of 2)
66 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
68 * regnum = reg index in regfile, or special/TIE-user reg number
[all …]
/Linux-v5.15/drivers/misc/habanalabs/goya/
Dgoya_security.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
12 * goya_set_block_as_protected - set the given block as protected
20 u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS; in goya_pb_set_block()
68 word_offset = ((mmMME_DUMMY & PROT_BITS_OFFS) >> 7) << 2; in goya_init_mme_protection_bits()
69 mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2); in goya_init_mme_protection_bits()
70 mask |= 1 << ((mmMME_RESET & 0x7F) >> 2); in goya_init_mme_protection_bits()
71 mask |= 1 << ((mmMME_STALL & 0x7F) >> 2); in goya_init_mme_protection_bits()
72 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); in goya_init_mme_protection_bits()
73 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); in goya_init_mme_protection_bits()
[all …]
/Linux-v5.15/arch/arm64/crypto/
Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
8 * it under the terms of the GNU General Public License version 2 as
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
16 .set .Lv\b\().2d, \b
21 * ARMv8.2 Crypto Extensions instructions
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
[all …]
Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
8 * it under the terms of the GNU General Public License version 2 as
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
17 .set .Lv\b\().2d, \b
37 * The SHA-512 round constants
85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
91 add v\i3\().2d, v\i3\().2d, v5.2d
94 sha512su0 v\in0\().2d, v\in1\().2d
[all …]
/Linux-v5.15/drivers/media/dvb-frontends/
Dstv090x_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
48 #define STV090x_OFFST_SSTREAM_LCK_1_FIELD 2
66 #define STV090x_OFFST_SPKTDEL_LOCK_2_FIELD 2
76 #define STV090x_OFFST_SDEMOD_LOCKB_2_FIELD 2
94 #define STV090x_OFFST_SDISEQC2TX_IRQ_FIELD 2
108 #define STV090x_OFFST_MSTREAM_LCK_1_FIELD 2
126 #define STV090x_OFFST_MPKTDEL_LOCK_2_FIELD 2
144 #define STV090x_OFFST_MDEMOD_LOCKB_2_FIELD 2
162 #define STV090x_OFFST_MDISEQC2TX_IRQ_FIELD 2
173 #define STV090x_WIDTH_12CADDR_INC_FIELD 2
[all …]
/Linux-v5.15/arch/xtensa/variants/csp/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
63 /* Save area for non-coprocessor optional and custom (TIE) state: */
68 #define XCHAL_TOTAL_SA_SIZE 48 /* with 16-byte align padding */
81 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
82 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
85 * galign = group byte alignment (power of 2) (galign >= align)
86 * align = register byte alignment (power of 2)
89 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
91 * regnum = reg index in regfile, or special/TIE-user reg number
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dexynos5410-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Exynos5410 SoC pin-mux and pin-config device tree source
9 #include <dt-bindings/pinctrl/samsung.h>
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
21 gpio-controller;
22 #gpio-cells = <2>;
24 interrupt-controller;
[all …]
/Linux-v5.15/drivers/gpu/drm/panel/
Dpanel-truly-nt35597.c1 // SPDX-License-Identifier: GPL-2.0
64 struct mipi_dsi_device *dsi[2];
78 { { 0xff, 0x20 }, 2 },
79 { { 0xfb, 0x01 }, 2 },
80 { { 0x00, 0x01 }, 2 },
81 { { 0x01, 0x55 }, 2 },
82 { { 0x02, 0x45 }, 2 },
83 { { 0x05, 0x40 }, 2 },
84 { { 0x06, 0x19 }, 2 },
85 { { 0x07, 0x1e }, 2 },
[all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/tigerlake/
Dcache.json4 "CollectPEBSRecord": "2",
5 "Counter": "0,1,2,3",
8 "PEBScounters": "0,1,2,3",
9 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
15 "CollectPEBSRecord": "2",
16 "Counter": "0,1,2,3",
19 "PEBScounters": "0,1,2,3",
26 "CollectPEBSRecord": "2",
27 "Counter": "0,1,2,3",
32 "PEBScounters": "0,1,2,3",
[all …]
Dpipeline.json4 "CollectPEBSRecord": "2",
5 "Counter": "0,1,2,3,4,5,6,7",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
10 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
16 "CollectPEBSRecord": "2",
17 "Counter": "0,1,2,3,4,5,6,7",
21 "PEBScounters": "0,1,2,3,4,5,6,7",
27 "CollectPEBSRecord": "2",
28 "Counter": "0,1,2,3,4,5,6,7",
32 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
/Linux-v5.15/arch/xtensa/variants/test_kc705_be/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
66 /* Save area for non-coprocessor optional and custom (TIE) state: */
71 #define XCHAL_TOTAL_SA_SIZE 160 /* with 16-byte align padding */
84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
88 * galign = group byte alignment (power of 2) (galign >= align)
89 * align = register byte alignment (power of 2)
92 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
[all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/icelake/
Dcache.json4 "CollectPEBSRecord": "2",
5 "Counter": "0,1,2,3",
8 "PEBScounters": "0,1,2,3",
15 …tired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core …
16 "CollectPEBSRecord": "2",
17 "Counter": "0,1,2,3",
22 "PEBScounters": "0,1,2,3",
23 …tired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core …
29 "CollectPEBSRecord": "2",
30 "Counter": "0,1,2,3",
[all …]
Dpipeline.json4 "CollectPEBSRecord": "2",
5 "Counter": "0,1,2,3,4,5,6,7",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
16 "CollectPEBSRecord": "2",
17 "Counter": "0,1,2,3,4,5,6,7",
20 "PEBScounters": "0,1,2,3,4,5,6,7",
28 "CollectPEBSRecord": "2",
29 "Counter": "0,1,2,3,4,5,6,7",
32 "PEBScounters": "0,1,2,3,4,5,6,7",
33 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
[all …]
/Linux-v5.15/drivers/staging/fbtft/
Dfb_ssd1331.c1 // SPDX-License-Identifier: GPL-2.0
16 #define DEFAULT_GAMMA "0 2 2 2 2 2 2 2 " \
17 "2 2 2 2 2 2 2 2 " \
18 "2 2 2 2 2 2 2 2 " \
19 "2 2 2 2 2 2 2 2 " \
20 "2 2 2 2 2 2 2 2 " \
21 "2 2 2 2 2 2 2 2 " \
22 "2 2 2 2 2 2 2 2 " \
23 "2 2 2 2 2 2 2" \
27 par->fbtftops.reset(par); in init_display()
[all …]
Dfb_ssd1351.c1 // SPDX-License-Identifier: GPL-2.0
15 #define DEFAULT_GAMMA "0 2 2 2 2 2 2 2 " \
16 "2 2 2 2 2 2 2 2 " \
17 "2 2 2 2 2 2 2 2 " \
18 "2 2 2 2 2 2 2 2 " \
19 "2 2 2 2 2 2 2 2 " \
20 "2 2 2 2 2 2 2 2 " \
21 "2 2 2 2 2 2 2 2 " \
22 "2 2 2 2 2 2 2" \
28 if (par->pdata && in init_display()
[all …]
/Linux-v5.15/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
66 /* Save area for non-coprocessor optional and custom (TIE) state: */
71 #define XCHAL_TOTAL_SA_SIZE 240 /* with 16-byte align padding */
84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
88 * galign = group byte alignment (power of 2) (galign >= align)
89 * align = register byte alignment (power of 2)
92 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
[all …]
/Linux-v5.15/drivers/mfd/
Dqcom_rpm.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <dt-bindings/mfd/qcom-rpm.h>
58 #define RPM_STATUS_REG(rpm, i) ((rpm)->status_regs + (i) * 4)
59 #define RPM_CTRL_REG(rpm, i) ((rpm)->ctrl_regs + (i) * 4)
60 #define RPM_REQ_REG(rpm, i) ((rpm)->req_regs + (i) * 4)
92 [QCOM_RPM_PM8921_SMPS1] = { 116, 31, 30, 2 },
93 [QCOM_RPM_PM8921_SMPS2] = { 118, 33, 31, 2 },
94 [QCOM_RPM_PM8921_SMPS3] = { 120, 35, 32, 2 },
95 [QCOM_RPM_PM8921_SMPS4] = { 122, 37, 33, 2 },
96 [QCOM_RPM_PM8921_SMPS5] = { 124, 39, 34, 2 },
[all …]
/Linux-v5.15/arch/mips/kernel/
Dmips-r2-to-r6-emul.c28 #include <asm/mips-r2-to-r6-emul.h>
65 pr_info("MIPS R2-to-R6 Emulator Enabled!"); in mipsr2emu_enable()
72 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
83 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
84 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
92 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
93 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
101 return -SIGFPE; in mipsr6_emul()
106 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
107 regs->regs[MIPSInst_RS(ir)] | in mipsr6_emul()
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/fsl/
Dmpc8641_hpcn_36b.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2008-2009 Freescale Semiconductor Inc.
8 /include/ "mpc8641si-pre.dtsi"
13 #address-cells = <2>;
14 #size-cells = <2>;
25 2 0 0xf 0xffdf8000 0x00008000
29 compatible = "cfi-flash";
31 bank-width = <2>;
32 device-width = <2>;
33 #address-cells = <1>;
[all …]
Dmpc8641_hpcn.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "mpc8641si-pre.dtsi"
23 2 0 0xffdf8000 0x00008000
27 compatible = "cfi-flash";
29 bank-width = <2>;
30 device-width = <2>;
31 #address-cells = <1>;
32 #size-cells = <1>;
40 read-only;
49 read-only;
[all …]
/Linux-v5.15/drivers/video/fbdev/
Datafb_utils.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 * would be faster. I suspect not for simple text system - not much
30 * Unaligned read/write used requires 68020+ - think this is a problem?
55 " lsr.l #1,%1 ; jcc 1f ; move.b %2,-(%0)\n" in fb_memclear_small()
56 "1: lsr.l #1,%1 ; jcc 1f ; move.w %2,-(%0)\n" in fb_memclear_small()
57 "1: lsr.l #1,%1 ; jcc 1f ; move.l %2,-(%0)\n" in fb_memclear_small()
58 "1: lsr.l #1,%1 ; jcc 1f ; move.l %2,-(%0) ; move.l %2,-(%0)\n" in fb_memclear_small()
65 " move.l %2,%%d4; move.l %2,%%d5; move.l %2,%%d6\n" in fb_memclear_small()
66 "2: movem.l %2/%%d4/%%d5/%%d6,-(%0)\n" in fb_memclear_small()
67 " dbra %1,2b\n" in fb_memclear_small()
[all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/icelakex/
Dpipeline.json3 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
4 "CollectPEBSRecord": "2",
9 …"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. …
15 "CollectPEBSRecord": "2",
26 "CollectPEBSRecord": "2",
37 "CollectPEBSRecord": "2",
48 "CollectPEBSRecord": "2",
49 "Counter": "0,1,2,3",
52 "PEBScounters": "0,1,2,3",
60 "CollectPEBSRecord": "2",
[all …]
/Linux-v5.15/Documentation/hwmon/
Dir35221.rst9 Addresses scanned: -
13 Author: Samuel Mendoza-Jonas <sam@mendozajonas.com>
17 -----------
19 IR35221 is a Digital DC-DC Multiphase Converter
23 -----------
32 # echo ir35221 0x70 > /sys/bus/i2c/devices/i2c-4/new_device
36 ----------------
44 curr[2-3]_label "iout[1-2]"
45 curr[2-3]_input Measured output current
46 curr[2-3]_crit Critical maximum current
[all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/sandybridge/
Dpipeline.json4 "Counter": "Fixed counter 2",
9 "CounterHTOff": "Fixed counter 2"
12 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
40 "Counter": "0,1,2,3",
45 "CounterHTOff": "0,1,2,3,4,5,6,7"
48 … See the table of not supported store forwards in the Intel\u00ae 64 and IA-32 Architectures Opti…
50 "Counter": "0,1,2,3",
54 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
55 "CounterHTOff": "0,1,2,3,4,5,6,7"
59 "Counter": "0,1,2,3",
[all …]

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