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/Linux-v5.15/drivers/gpu/drm/radeon/
Drs780_dpm.c37 struct igp_ps *ps = rps->ps_priv; in rs780_get_ps()
44 struct igp_power_info *pi = rdev->pm.dpm.priv; in rs780_get_pi()
52 struct radeon_mode_info *minfo = &rdev->mode_info; in rs780_get_pm_mode_parameters()
58 pi->crtc_id = 0; in rs780_get_pm_mode_parameters()
59 pi->refresh_rate = 60; in rs780_get_pm_mode_parameters()
61 for (i = 0; i < rdev->num_crtc; i++) { in rs780_get_pm_mode_parameters()
62 crtc = (struct drm_crtc *)minfo->crtcs[i]; in rs780_get_pm_mode_parameters()
63 if (crtc && crtc->enabled) { in rs780_get_pm_mode_parameters()
65 pi->crtc_id = radeon_crtc->crtc_id; in rs780_get_pm_mode_parameters()
66 if (crtc->mode.htotal && crtc->mode.vtotal) in rs780_get_pm_mode_parameters()
[all …]
Dradeon_uvd.c15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
72 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); in radeon_uvd_init()
74 switch (rdev->family) { in radeon_uvd_init()
134 return -EINVAL; in radeon_uvd_init()
137 rdev->uvd.fw_header_present = false; in radeon_uvd_init()
138 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; in radeon_uvd_init()
141 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev); in radeon_uvd_init()
143 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", in radeon_uvd_init()
146 struct common_firmware_header *hdr = (void *)rdev->uvd_fw->data; in radeon_uvd_init()
149 r = radeon_ucode_validate(rdev->uvd_fw); in radeon_uvd_init()
[all …]
Dsumo_dpm.c76 struct sumo_ps *ps = rps->ps_priv; in sumo_get_ps()
83 struct sumo_power_info *pi = rdev->pm.dpm.priv; in sumo_get_pi()
156 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
184 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
196 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
217 if (rdev->family == CHIP_PALM) in sumo_gfx_powergating_initialize()
226 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
232 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
251 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
259 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
[all …]
Dtrinity_dpm.c306 struct trinity_ps *ps = rps->ps_priv; in trinity_get_ps()
313 struct trinity_power_info *pi = rdev->pm.dpm.priv; in trinity_get_pi()
348 if (pi->override_dynamic_mgpg && (hw_rev == 0)) in trinity_gfx_powergating_initialize()
505 if (pi->enable_gfx_clock_gating) in trinity_enable_clock_power_gating()
507 if (pi->enable_mg_clock_gating) in trinity_enable_clock_power_gating()
509 if (pi->enable_gfx_power_gating) in trinity_enable_clock_power_gating()
511 if (pi->enable_mg_clock_gating) { in trinity_enable_clock_power_gating()
515 if (pi->enable_gfx_clock_gating) in trinity_enable_clock_power_gating()
517 if (pi->enable_gfx_dynamic_mgpg) in trinity_enable_clock_power_gating()
519 if (pi->enable_gfx_power_gating) in trinity_enable_clock_power_gating()
[all …]
Drv6xx_dpm.c38 struct rv6xx_ps *ps = rps->ps_priv; in rv6xx_get_ps()
45 struct rv6xx_power_info *pi = rdev->pm.dpm.priv; in rv6xx_get_pi()
63 for (i = 0; i < rdev->usec_timeout; i++) { in rv6xx_force_pcie_gen1()
150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
152 step->post_divider = 1; in rv6xx_convert_clock_to_stepping()
154 step->vco_frequency = clock * step->post_divider; in rv6xx_convert_clock_to_stepping()
163 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_output_stepping()
167 pi->spll_ref_div, in rv6xx_output_stepping()
173 if (step->post_divider == 1) in rv6xx_output_stepping()
176 u32 lo_len = (step->post_divider - 2) / 2; in rv6xx_output_stepping()
[all …]
Drv770_dpm.c51 struct rv7xx_ps *ps = rps->ps_priv; in rv770_get_ps()
58 struct rv7xx_power_info *pi = rdev->pm.dpm.priv; in rv770_get_pi()
65 struct evergreen_power_info *pi = rdev->pm.dpm.priv; in evergreen_get_pi()
82 if (!pi->boot_in_gen2) { in rv770_enable_bif_dynamic_pcie_gen2()
152 if (rdev->family == CHIP_RV770) in rv770_mg_clock_gating_enable()
160 if (pi->mgcgtssm) in rv770_mg_clock_gating_enable()
231 return (pl->flags & ATOM_PPLIB_R600_FLAGS_LOWPOWER) ? in rv770_get_seq_value()
242 pi->soft_regs_start + reg_offset,
243 value, pi->sram_end);
253 pi->soft_regs_start + reg_offset, in rv770_write_smc_soft_register()
[all …]
Dradeon_asic.h409 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
476 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
533 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
534 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
699 /* DCE6 - SI */
748 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
776 /* DCE8 - CIK */
786 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
/Linux-v5.15/Documentation/devicetree/bindings/media/
Daspeed-video.txt7 - compatible: "aspeed,ast2400-video-engine" or
8 "aspeed,ast2500-video-engine" or
9 "aspeed,ast2600-video-engine"
10 - reg: contains the offset and length of the VE memory region
11 - clocks: clock specifiers for the syscon clocks associated with
12 the VE (ordering must match the clock-names property)
13 - clock-names: "vclk" and "eclk"
14 - resets: reset specifier for the syscon reset associated with
16 - interrupts: the interrupt associated with the VE on this platform
19 - memory-region:
[all …]
/Linux-v5.15/drivers/video/fbdev/nvidia/
Dnv_hw.c3 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
10 |* Any use of this source code must include, in the user documenta- *|
14 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
[all …]
/Linux-v5.15/drivers/gpu/drm/exynos/
Dexynos7_drm_decon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
30 #include "regs-decon7.h"
50 struct clk *vclk; member
62 {.compatible = "samsung,exynos7-decon"},
86 struct decon_context *ctx = crtc->ctx; in decon_wait_for_vblank()
88 if (ctx->suspended) in decon_wait_for_vblank()
91 atomic_set(&ctx->wait_vsync_event, 1); in decon_wait_for_vblank()
97 if (!wait_event_timeout(ctx->wait_vsync_queue, in decon_wait_for_vblank()
98 !atomic_read(&ctx->wait_vsync_event), in decon_wait_for_vblank()
100 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n"); in decon_wait_for_vblank()
[all …]
/Linux-v5.15/drivers/gpu/drm/nouveau/dispnv04/
Darb.c2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2007-2009 Stuart Bennett
63 pclk_freq = arb->pclk_khz; in nv04_calc_arb()
64 mclk_freq = arb->mclk_khz; in nv04_calc_arb()
65 nvclk_freq = arb->nvclk_khz; in nv04_calc_arb()
66 pagemiss = arb->mem_page_miss; in nv04_calc_arb()
67 cas = arb->mem_latency; in nv04_calc_arb()
68 bpp = arb->bpp; in nv04_calc_arb()
92 m1 = clwm + cbs - 512; in nv04_calc_arb()
97 mclk_extra--; in nv04_calc_arb()
[all …]
/Linux-v5.15/drivers/video/fbdev/via/
Dvt1636.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
8 #include <linux/via-core.h>
16 /* T1: VDD on - Data on. Each increment is 1 ms. (50ms = 031h) */
18 /* T2: Data on - Backlight on. Each increment is 2 ms. (210ms = 068h) */
20 /* T3: Backlight off -Data off. Each increment is 2 ms. (210ms = 068h)*/
22 /* T4: Data off - VDD off. Each increment is 1 ms. (50ms = 031h) */
24 /* T5: VDD off - VDD on. Each increment is 100 ms. (500ms = 04h) */
46 viafb_i2c_readbyte(plvds_chip_info->i2c_port, in viafb_gpio_i2c_read_lvds()
[all …]
/Linux-v5.15/drivers/video/fbdev/riva/
Driva_hw.c3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
10 |* Any use of this source code must include, in the user documenta- *|
14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
[all …]
/Linux-v5.15/drivers/video/fbdev/aty/
Dmach64_ct.c1 // SPDX-License-Identifier: GPL-2.0
53 * CLK = ----------------------
70 * XCLK The clock rate of the on-chip memory
75 * VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3
77 * SCLK Multi-purpose clock
79 * - MCLK and XCLK use the same FB_DIV
80 * - VCLK0 .. VCLK3 use the same FB_DIV
81 * - V2CLK is needed when the second CRTC is used (can be used for dualhead);
84 * - SCLK is not available on all cards; it is know to exist on the Rage LT-PRO,
86 * - V2CLK is not available on all cards, most likely only the Rage LT-PRO,
[all …]
Daty128fb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
5 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
9 * - Code cleanup
12 * - 15/16 bit cleanup
13 * - fix panning
16 * - pmac-specific PM stuff
17 * - various fixes & cleanups
20 * - FB_ACTIVATE fixes
23 * - Convert to new framebuffer API,
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu8_hwmgr.c27 #include "atom-types.h"
53 if (smu8_magic != hw_ps->magic) in cast_smu8_power_state()
62 if (smu8_magic != hw_ps->magic) in cast_const_smu8_power_state()
73 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_get_eclk_level()
78 for (i = 0; i < (int)ptable->count; i++) { in smu8_get_eclk_level()
79 if (clock <= ptable->entries[i].ecclk) in smu8_get_eclk_level()
86 for (i = ptable->count - 1; i >= 0; i--) { in smu8_get_eclk_level()
87 if (clock >= ptable->entries[i].ecclk) in smu8_get_eclk_level()
104 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level()
109 for (i = 0; i < (int)table->count; i++) { in smu8_get_sclk_level()
[all …]
Dhwmgr_ppt.h29 #include "atom-types.h"
59 uint32_t dclk; /* UVD D-clock */
60 uint32_t vclk; /* UVD V-clock */ member
/Linux-v5.15/drivers/media/platform/
Daspeed-video.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 // Copyright (c) 2019-2020 Intel Corporation
10 #include <linux/dma-mapping.h>
22 #include <linux/v4l2-controls.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-dev.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-dv-timings.h>
30 #include <media/v4l2-event.h>
31 #include <media/v4l2-ioctl.h>
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/
Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
21 R |-------| |----| Processing | | | | |
22 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/exynos/
Dsamsung-fimd.txt1 Device-Tree bindings for Samsung SoC display controller (FIMD)
8 - compatible: value should be one of the following
9 "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
10 "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
11 "samsung,s5pv210-fimd"; /* for S5PV210 SoC */
12 "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
13 "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
14 "samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
15 "samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
17 - reg: physical base address and length of the FIMD registers set.
[all …]
/Linux-v5.15/drivers/video/fbdev/sis/
Dinit.c10 * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
27 * * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
55 * Formerly based on non-functional code-fragements for 300 series by SiS, Inc.
81 SiS_Pr->SiS_SModeIDTable = SiS_SModeIDTable; in InitCommonPointer()
82 SiS_Pr->SiS_StResInfo = SiS_StResInfo; in InitCommonPointer()
83 SiS_Pr->SiS_ModeResInfo = SiS_ModeResInfo; in InitCommonPointer()
84 SiS_Pr->SiS_StandTable = SiS_StandTable; in InitCommonPointer()
86 SiS_Pr->SiS_NTSCTiming = SiS_NTSCTiming; in InitCommonPointer()
87 SiS_Pr->SiS_PALTiming = SiS_PALTiming; in InitCommonPointer()
88 SiS_Pr->SiS_HiTVSt1Timing = SiS_HiTVSt1Timing; in InitCommonPointer()
[all …]
/Linux-v5.15/drivers/usb/misc/sisusbvga/
Dsisusb_init.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * sisusb - usb kernel driver for SiS315(E) based USB2VGA dongles
7 * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
56 SiS_Pr->SiS_ModeResInfo = SiSUSB_ModeResInfo; in SiSUSB_InitPtr()
57 SiS_Pr->SiS_StandTable = SiSUSB_StandTable; in SiSUSB_InitPtr()
59 SiS_Pr->SiS_SModeIDTable = SiSUSB_SModeIDTable; in SiSUSB_InitPtr()
60 SiS_Pr->SiS_EModeIDTable = SiSUSB_EModeIDTable; in SiSUSB_InitPtr()
61 SiS_Pr->SiS_RefIndex = SiSUSB_RefIndex; in SiSUSB_InitPtr()
62 SiS_Pr->SiS_CRT1Table = SiSUSB_CRT1Table; in SiSUSB_InitPtr()
64 SiS_Pr->SiS_VCLKData = SiSUSB_VCLKData; in SiSUSB_InitPtr()
[all …]
/Linux-v5.15/drivers/gpu/drm/meson/
Dmeson_vclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 * VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.
21 * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
22 * - HDMI Pixel Clocks generation
26 * - Genenate Pixel clocks for 2K/4K 10bit formats
33 * | | | | | |--ENCI
34 * | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
35 * |__________| |_________| \ | MUX |--ENCP
36 * --VCLK2-| |--VDAC
37 * |_____|--HDMI-TX
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dsi.c992 switch (adev->asic_type) { in si_query_video_codecs()
1014 return -EINVAL; in si_query_video_codecs()
1023 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pcie_rreg()
1027 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pcie_rreg()
1035 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pcie_wreg()
1040 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pcie_wreg()
1048 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pciep_rreg()
1052 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pciep_rreg()
1060 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pciep_wreg()
1065 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pciep_wreg()
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/pm/inc/
Dsmu11_driver_if_vangogh.h120 uint32_t vclk; member
149 uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk
186 uint16_t CoreTemperature[8]; //[centi-Celsius]
188 uint16_t L3Temperature[2]; //[centi-Celsius]
190 uint16_t GfxTemperature; //[centi-Celsius]
191 uint16_t SocTemperature; //[centi-Celsius]
216 uint16_t CoreTemperature[4]; //[centi-Celsius]
218 uint16_t L3Temperature[1]; //[centi-Celsius]
220 uint16_t GfxTemperature; //[centi-Celsius]
221 uint16_t SocTemperature; //[centi-Celsius]

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