1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ZynqMP DisplayPort Driver
4 *
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
6 *
7 * Authors:
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 */
11
12 #include <drm/drm_atomic_helper.h>
13 #include <drm/drm_connector.h>
14 #include <drm/drm_crtc.h>
15 #include <drm/drm_device.h>
16 #include <drm/drm_dp_helper.h>
17 #include <drm/drm_edid.h>
18 #include <drm/drm_encoder.h>
19 #include <drm/drm_managed.h>
20 #include <drm/drm_modes.h>
21 #include <drm/drm_of.h>
22 #include <drm/drm_probe_helper.h>
23 #include <drm/drm_simple_kms_helper.h>
24
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/device.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/phy/phy.h>
32 #include <linux/reset.h>
33
34 #include "zynqmp_disp.h"
35 #include "zynqmp_dp.h"
36 #include "zynqmp_dpsub.h"
37
38 static uint zynqmp_dp_aux_timeout_ms = 50;
39 module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444);
40 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
41
42 /*
43 * Some sink requires a delay after power on request
44 */
45 static uint zynqmp_dp_power_on_delay_ms = 4;
46 module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444);
47 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
48
49 /* Link configuration registers */
50 #define ZYNQMP_DP_LINK_BW_SET 0x0
51 #define ZYNQMP_DP_LANE_COUNT_SET 0x4
52 #define ZYNQMP_DP_ENHANCED_FRAME_EN 0x8
53 #define ZYNQMP_DP_TRAINING_PATTERN_SET 0xc
54 #define ZYNQMP_DP_SCRAMBLING_DISABLE 0x14
55 #define ZYNQMP_DP_DOWNSPREAD_CTL 0x18
56 #define ZYNQMP_DP_SOFTWARE_RESET 0x1c
57 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM1 BIT(0)
58 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM2 BIT(1)
59 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM3 BIT(2)
60 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM4 BIT(3)
61 #define ZYNQMP_DP_SOFTWARE_RESET_AUX BIT(7)
62 #define ZYNQMP_DP_SOFTWARE_RESET_ALL (ZYNQMP_DP_SOFTWARE_RESET_STREAM1 | \
63 ZYNQMP_DP_SOFTWARE_RESET_STREAM2 | \
64 ZYNQMP_DP_SOFTWARE_RESET_STREAM3 | \
65 ZYNQMP_DP_SOFTWARE_RESET_STREAM4 | \
66 ZYNQMP_DP_SOFTWARE_RESET_AUX)
67
68 /* Core enable registers */
69 #define ZYNQMP_DP_TRANSMITTER_ENABLE 0x80
70 #define ZYNQMP_DP_MAIN_STREAM_ENABLE 0x84
71 #define ZYNQMP_DP_FORCE_SCRAMBLER_RESET 0xc0
72 #define ZYNQMP_DP_VERSION 0xf8
73 #define ZYNQMP_DP_VERSION_MAJOR_MASK GENMASK(31, 24)
74 #define ZYNQMP_DP_VERSION_MAJOR_SHIFT 24
75 #define ZYNQMP_DP_VERSION_MINOR_MASK GENMASK(23, 16)
76 #define ZYNQMP_DP_VERSION_MINOR_SHIFT 16
77 #define ZYNQMP_DP_VERSION_REVISION_MASK GENMASK(15, 12)
78 #define ZYNQMP_DP_VERSION_REVISION_SHIFT 12
79 #define ZYNQMP_DP_VERSION_PATCH_MASK GENMASK(11, 8)
80 #define ZYNQMP_DP_VERSION_PATCH_SHIFT 8
81 #define ZYNQMP_DP_VERSION_INTERNAL_MASK GENMASK(7, 0)
82 #define ZYNQMP_DP_VERSION_INTERNAL_SHIFT 0
83
84 /* Core ID registers */
85 #define ZYNQMP_DP_CORE_ID 0xfc
86 #define ZYNQMP_DP_CORE_ID_MAJOR_MASK GENMASK(31, 24)
87 #define ZYNQMP_DP_CORE_ID_MAJOR_SHIFT 24
88 #define ZYNQMP_DP_CORE_ID_MINOR_MASK GENMASK(23, 16)
89 #define ZYNQMP_DP_CORE_ID_MINOR_SHIFT 16
90 #define ZYNQMP_DP_CORE_ID_REVISION_MASK GENMASK(15, 8)
91 #define ZYNQMP_DP_CORE_ID_REVISION_SHIFT 8
92 #define ZYNQMP_DP_CORE_ID_DIRECTION GENMASK(1)
93
94 /* AUX channel interface registers */
95 #define ZYNQMP_DP_AUX_COMMAND 0x100
96 #define ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT 8
97 #define ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY BIT(12)
98 #define ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT 0
99 #define ZYNQMP_DP_AUX_WRITE_FIFO 0x104
100 #define ZYNQMP_DP_AUX_ADDRESS 0x108
101 #define ZYNQMP_DP_AUX_CLK_DIVIDER 0x10c
102 #define ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT 8
103 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE 0x130
104 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD BIT(0)
105 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST BIT(1)
106 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY BIT(2)
107 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT BIT(3)
108 #define ZYNQMP_DP_AUX_REPLY_DATA 0x134
109 #define ZYNQMP_DP_AUX_REPLY_CODE 0x138
110 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK (0)
111 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_NACK BIT(0)
112 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_DEFER BIT(1)
113 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK (0)
114 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_NACK BIT(2)
115 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_DEFER BIT(3)
116 #define ZYNQMP_DP_AUX_REPLY_COUNT 0x13c
117 #define ZYNQMP_DP_REPLY_DATA_COUNT 0x148
118 #define ZYNQMP_DP_REPLY_DATA_COUNT_MASK 0xff
119 #define ZYNQMP_DP_INT_STATUS 0x3a0
120 #define ZYNQMP_DP_INT_MASK 0x3a4
121 #define ZYNQMP_DP_INT_EN 0x3a8
122 #define ZYNQMP_DP_INT_DS 0x3ac
123 #define ZYNQMP_DP_INT_HPD_IRQ BIT(0)
124 #define ZYNQMP_DP_INT_HPD_EVENT BIT(1)
125 #define ZYNQMP_DP_INT_REPLY_RECEIVED BIT(2)
126 #define ZYNQMP_DP_INT_REPLY_TIMEOUT BIT(3)
127 #define ZYNQMP_DP_INT_HPD_PULSE_DET BIT(4)
128 #define ZYNQMP_DP_INT_EXT_PKT_TXD BIT(5)
129 #define ZYNQMP_DP_INT_LIV_ABUF_UNDRFLW BIT(12)
130 #define ZYNQMP_DP_INT_VBLANK_START BIT(13)
131 #define ZYNQMP_DP_INT_PIXEL1_MATCH BIT(14)
132 #define ZYNQMP_DP_INT_PIXEL0_MATCH BIT(15)
133 #define ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK 0x3f0000
134 #define ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK 0xfc00000
135 #define ZYNQMP_DP_INT_CUST_TS_2 BIT(28)
136 #define ZYNQMP_DP_INT_CUST_TS BIT(29)
137 #define ZYNQMP_DP_INT_EXT_VSYNC_TS BIT(30)
138 #define ZYNQMP_DP_INT_VSYNC_TS BIT(31)
139 #define ZYNQMP_DP_INT_ALL (ZYNQMP_DP_INT_HPD_IRQ | \
140 ZYNQMP_DP_INT_HPD_EVENT | \
141 ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK | \
142 ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK)
143
144 /* Main stream attribute registers */
145 #define ZYNQMP_DP_MAIN_STREAM_HTOTAL 0x180
146 #define ZYNQMP_DP_MAIN_STREAM_VTOTAL 0x184
147 #define ZYNQMP_DP_MAIN_STREAM_POLARITY 0x188
148 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT 0
149 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT 1
150 #define ZYNQMP_DP_MAIN_STREAM_HSWIDTH 0x18c
151 #define ZYNQMP_DP_MAIN_STREAM_VSWIDTH 0x190
152 #define ZYNQMP_DP_MAIN_STREAM_HRES 0x194
153 #define ZYNQMP_DP_MAIN_STREAM_VRES 0x198
154 #define ZYNQMP_DP_MAIN_STREAM_HSTART 0x19c
155 #define ZYNQMP_DP_MAIN_STREAM_VSTART 0x1a0
156 #define ZYNQMP_DP_MAIN_STREAM_MISC0 0x1a4
157 #define ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK BIT(0)
158 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB (0 << 1)
159 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422 (5 << 1)
160 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444 (6 << 1)
161 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK (7 << 1)
162 #define ZYNQMP_DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE BIT(3)
163 #define ZYNQMP_DP_MAIN_STREAM_MISC0_YCBCR_COLR BIT(4)
164 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6 (0 << 5)
165 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8 (1 << 5)
166 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10 (2 << 5)
167 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12 (3 << 5)
168 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16 (4 << 5)
169 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK (7 << 5)
170 #define ZYNQMP_DP_MAIN_STREAM_MISC1 0x1a8
171 #define ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN BIT(7)
172 #define ZYNQMP_DP_MAIN_STREAM_M_VID 0x1ac
173 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE 0x1b0
174 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF 64
175 #define ZYNQMP_DP_MAIN_STREAM_N_VID 0x1b4
176 #define ZYNQMP_DP_USER_PIX_WIDTH 0x1b8
177 #define ZYNQMP_DP_USER_DATA_COUNT_PER_LANE 0x1bc
178 #define ZYNQMP_DP_MIN_BYTES_PER_TU 0x1c4
179 #define ZYNQMP_DP_FRAC_BYTES_PER_TU 0x1c8
180 #define ZYNQMP_DP_INIT_WAIT 0x1cc
181
182 /* PHY configuration and status registers */
183 #define ZYNQMP_DP_PHY_RESET 0x200
184 #define ZYNQMP_DP_PHY_RESET_PHY_RESET BIT(0)
185 #define ZYNQMP_DP_PHY_RESET_GTTX_RESET BIT(1)
186 #define ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET BIT(8)
187 #define ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET BIT(9)
188 #define ZYNQMP_DP_PHY_RESET_ALL_RESET (ZYNQMP_DP_PHY_RESET_PHY_RESET | \
189 ZYNQMP_DP_PHY_RESET_GTTX_RESET | \
190 ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET | \
191 ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET)
192 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_0 0x210
193 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_1 0x214
194 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_2 0x218
195 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_3 0x21c
196 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_0 0x220
197 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_1 0x224
198 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_2 0x228
199 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_3 0x22c
200 #define ZYNQMP_DP_PHY_CLOCK_SELECT 0x234
201 #define ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G 0x1
202 #define ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G 0x3
203 #define ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G 0x5
204 #define ZYNQMP_DP_TX_PHY_POWER_DOWN 0x238
205 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_0 BIT(0)
206 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_1 BIT(1)
207 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_2 BIT(2)
208 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_3 BIT(3)
209 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL 0xf
210 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_0 0x23c
211 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_1 0x240
212 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_2 0x244
213 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_3 0x248
214 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_0 0x24c
215 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_1 0x250
216 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_2 0x254
217 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_3 0x258
218 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 0x24c
219 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_1 0x250
220 #define ZYNQMP_DP_PHY_STATUS 0x280
221 #define ZYNQMP_DP_PHY_STATUS_PLL_LOCKED_SHIFT 4
222 #define ZYNQMP_DP_PHY_STATUS_FPGA_PLL_LOCKED BIT(6)
223
224 /* Audio registers */
225 #define ZYNQMP_DP_TX_AUDIO_CONTROL 0x300
226 #define ZYNQMP_DP_TX_AUDIO_CHANNELS 0x304
227 #define ZYNQMP_DP_TX_AUDIO_INFO_DATA 0x308
228 #define ZYNQMP_DP_TX_M_AUD 0x328
229 #define ZYNQMP_DP_TX_N_AUD 0x32c
230 #define ZYNQMP_DP_TX_AUDIO_EXT_DATA 0x330
231
232 #define ZYNQMP_DP_MAX_LANES 2
233 #define ZYNQMP_MAX_FREQ 3000000
234
235 #define DP_REDUCED_BIT_RATE 162000
236 #define DP_HIGH_BIT_RATE 270000
237 #define DP_HIGH_BIT_RATE2 540000
238 #define DP_MAX_TRAINING_TRIES 5
239 #define DP_V1_2 0x12
240
241 /**
242 * struct zynqmp_dp_link_config - Common link config between source and sink
243 * @max_rate: maximum link rate
244 * @max_lanes: maximum number of lanes
245 */
246 struct zynqmp_dp_link_config {
247 int max_rate;
248 u8 max_lanes;
249 };
250
251 /**
252 * struct zynqmp_dp_mode - Configured mode of DisplayPort
253 * @bw_code: code for bandwidth(link rate)
254 * @lane_cnt: number of lanes
255 * @pclock: pixel clock frequency of current mode
256 * @fmt: format identifier string
257 */
258 struct zynqmp_dp_mode {
259 u8 bw_code;
260 u8 lane_cnt;
261 int pclock;
262 const char *fmt;
263 };
264
265 /**
266 * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
267 * @misc0: misc0 configuration (per DP v1.2 spec)
268 * @misc1: misc1 configuration (per DP v1.2 spec)
269 * @bpp: bits per pixel
270 */
271 struct zynqmp_dp_config {
272 u8 misc0;
273 u8 misc1;
274 u8 bpp;
275 };
276
277 /**
278 * struct zynqmp_dp - Xilinx DisplayPort core
279 * @encoder: the drm encoder structure
280 * @connector: the drm connector structure
281 * @dev: device structure
282 * @dpsub: Display subsystem
283 * @drm: DRM core
284 * @iomem: device I/O memory for register access
285 * @reset: reset controller
286 * @irq: irq
287 * @config: IP core configuration from DTS
288 * @aux: aux channel
289 * @phy: PHY handles for DP lanes
290 * @num_lanes: number of enabled phy lanes
291 * @hpd_work: hot plug detection worker
292 * @status: connection status
293 * @enabled: flag to indicate if the device is enabled
294 * @dpcd: DP configuration data from currently connected sink device
295 * @link_config: common link configuration between IP core and sink device
296 * @mode: current mode between IP core and sink device
297 * @train_set: set of training data
298 */
299 struct zynqmp_dp {
300 struct drm_encoder encoder;
301 struct drm_connector connector;
302 struct device *dev;
303 struct zynqmp_dpsub *dpsub;
304 struct drm_device *drm;
305 void __iomem *iomem;
306 struct reset_control *reset;
307 int irq;
308
309 struct zynqmp_dp_config config;
310 struct drm_dp_aux aux;
311 struct phy *phy[ZYNQMP_DP_MAX_LANES];
312 u8 num_lanes;
313 struct delayed_work hpd_work;
314 enum drm_connector_status status;
315 bool enabled;
316
317 u8 dpcd[DP_RECEIVER_CAP_SIZE];
318 struct zynqmp_dp_link_config link_config;
319 struct zynqmp_dp_mode mode;
320 u8 train_set[ZYNQMP_DP_MAX_LANES];
321 };
322
encoder_to_dp(struct drm_encoder * encoder)323 static inline struct zynqmp_dp *encoder_to_dp(struct drm_encoder *encoder)
324 {
325 return container_of(encoder, struct zynqmp_dp, encoder);
326 }
327
connector_to_dp(struct drm_connector * connector)328 static inline struct zynqmp_dp *connector_to_dp(struct drm_connector *connector)
329 {
330 return container_of(connector, struct zynqmp_dp, connector);
331 }
332
zynqmp_dp_write(struct zynqmp_dp * dp,int offset,u32 val)333 static void zynqmp_dp_write(struct zynqmp_dp *dp, int offset, u32 val)
334 {
335 writel(val, dp->iomem + offset);
336 }
337
zynqmp_dp_read(struct zynqmp_dp * dp,int offset)338 static u32 zynqmp_dp_read(struct zynqmp_dp *dp, int offset)
339 {
340 return readl(dp->iomem + offset);
341 }
342
zynqmp_dp_clr(struct zynqmp_dp * dp,int offset,u32 clr)343 static void zynqmp_dp_clr(struct zynqmp_dp *dp, int offset, u32 clr)
344 {
345 zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) & ~clr);
346 }
347
zynqmp_dp_set(struct zynqmp_dp * dp,int offset,u32 set)348 static void zynqmp_dp_set(struct zynqmp_dp *dp, int offset, u32 set)
349 {
350 zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) | set);
351 }
352
353 /* -----------------------------------------------------------------------------
354 * PHY Handling
355 */
356
357 #define RST_TIMEOUT_MS 1000
358
zynqmp_dp_reset(struct zynqmp_dp * dp,bool assert)359 static int zynqmp_dp_reset(struct zynqmp_dp *dp, bool assert)
360 {
361 unsigned long timeout;
362
363 if (assert)
364 reset_control_assert(dp->reset);
365 else
366 reset_control_deassert(dp->reset);
367
368 /* Wait for the (de)assert to complete. */
369 timeout = jiffies + msecs_to_jiffies(RST_TIMEOUT_MS);
370 while (!time_after_eq(jiffies, timeout)) {
371 bool status = !!reset_control_status(dp->reset);
372
373 if (assert == status)
374 return 0;
375
376 cpu_relax();
377 }
378
379 dev_err(dp->dev, "reset %s timeout\n", assert ? "assert" : "deassert");
380 return -ETIMEDOUT;
381 }
382
383 /**
384 * zynqmp_dp_phy_init - Initialize the phy
385 * @dp: DisplayPort IP core structure
386 *
387 * Initialize the phy.
388 *
389 * Return: 0 if the phy instances are initialized correctly, or the error code
390 * returned from the callee functions.
391 */
zynqmp_dp_phy_init(struct zynqmp_dp * dp)392 static int zynqmp_dp_phy_init(struct zynqmp_dp *dp)
393 {
394 int ret;
395 int i;
396
397 for (i = 0; i < dp->num_lanes; i++) {
398 ret = phy_init(dp->phy[i]);
399 if (ret) {
400 dev_err(dp->dev, "failed to init phy lane %d\n", i);
401 return ret;
402 }
403 }
404
405 zynqmp_dp_clr(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET);
406
407 /*
408 * Power on lanes in reverse order as only lane 0 waits for the PLL to
409 * lock.
410 */
411 for (i = dp->num_lanes - 1; i >= 0; i--) {
412 ret = phy_power_on(dp->phy[i]);
413 if (ret) {
414 dev_err(dp->dev, "failed to power on phy lane %d\n", i);
415 return ret;
416 }
417 }
418
419 return 0;
420 }
421
422 /**
423 * zynqmp_dp_phy_exit - Exit the phy
424 * @dp: DisplayPort IP core structure
425 *
426 * Exit the phy.
427 */
zynqmp_dp_phy_exit(struct zynqmp_dp * dp)428 static void zynqmp_dp_phy_exit(struct zynqmp_dp *dp)
429 {
430 unsigned int i;
431 int ret;
432
433 for (i = 0; i < dp->num_lanes; i++) {
434 ret = phy_power_off(dp->phy[i]);
435 if (ret)
436 dev_err(dp->dev, "failed to power off phy(%d) %d\n", i,
437 ret);
438 }
439
440 for (i = 0; i < dp->num_lanes; i++) {
441 ret = phy_exit(dp->phy[i]);
442 if (ret)
443 dev_err(dp->dev, "failed to exit phy(%d) %d\n", i, ret);
444 }
445 }
446
447 /**
448 * zynqmp_dp_phy_probe - Probe the PHYs
449 * @dp: DisplayPort IP core structure
450 *
451 * Probe PHYs for all lanes. Less PHYs may be available than the number of
452 * lanes, which is not considered an error as long as at least one PHY is
453 * found. The caller can check dp->num_lanes to check how many PHYs were found.
454 *
455 * Return:
456 * * 0 - Success
457 * * -ENXIO - No PHY found
458 * * -EPROBE_DEFER - Probe deferral requested
459 * * Other negative value - PHY retrieval failure
460 */
zynqmp_dp_phy_probe(struct zynqmp_dp * dp)461 static int zynqmp_dp_phy_probe(struct zynqmp_dp *dp)
462 {
463 unsigned int i;
464
465 for (i = 0; i < ZYNQMP_DP_MAX_LANES; i++) {
466 char phy_name[16];
467 struct phy *phy;
468
469 snprintf(phy_name, sizeof(phy_name), "dp-phy%d", i);
470 phy = devm_phy_get(dp->dev, phy_name);
471
472 if (IS_ERR(phy)) {
473 switch (PTR_ERR(phy)) {
474 case -ENODEV:
475 if (dp->num_lanes)
476 return 0;
477
478 dev_err(dp->dev, "no PHY found\n");
479 return -ENXIO;
480
481 case -EPROBE_DEFER:
482 return -EPROBE_DEFER;
483
484 default:
485 dev_err(dp->dev, "failed to get PHY lane %u\n",
486 i);
487 return PTR_ERR(phy);
488 }
489 }
490
491 dp->phy[i] = phy;
492 dp->num_lanes++;
493 }
494
495 return 0;
496 }
497
498 /**
499 * zynqmp_dp_phy_ready - Check if PHY is ready
500 * @dp: DisplayPort IP core structure
501 *
502 * Check if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times.
503 * This amount of delay was suggested by IP designer.
504 *
505 * Return: 0 if PHY is ready, or -ENODEV if PHY is not ready.
506 */
zynqmp_dp_phy_ready(struct zynqmp_dp * dp)507 static int zynqmp_dp_phy_ready(struct zynqmp_dp *dp)
508 {
509 u32 i, reg, ready;
510
511 ready = (1 << dp->num_lanes) - 1;
512
513 /* Wait for 100 * 1ms. This should be enough time for PHY to be ready */
514 for (i = 0; ; i++) {
515 reg = zynqmp_dp_read(dp, ZYNQMP_DP_PHY_STATUS);
516 if ((reg & ready) == ready)
517 return 0;
518
519 if (i == 100) {
520 dev_err(dp->dev, "PHY isn't ready\n");
521 return -ENODEV;
522 }
523
524 usleep_range(1000, 1100);
525 }
526
527 return 0;
528 }
529
530 /* -----------------------------------------------------------------------------
531 * DisplayPort Link Training
532 */
533
534 /**
535 * zynqmp_dp_max_rate - Calculate and return available max pixel clock
536 * @link_rate: link rate (Kilo-bytes / sec)
537 * @lane_num: number of lanes
538 * @bpp: bits per pixel
539 *
540 * Return: max pixel clock (KHz) supported by current link config.
541 */
zynqmp_dp_max_rate(int link_rate,u8 lane_num,u8 bpp)542 static inline int zynqmp_dp_max_rate(int link_rate, u8 lane_num, u8 bpp)
543 {
544 return link_rate * lane_num * 8 / bpp;
545 }
546
547 /**
548 * zynqmp_dp_mode_configure - Configure the link values
549 * @dp: DisplayPort IP core structure
550 * @pclock: pixel clock for requested display mode
551 * @current_bw: current link rate
552 *
553 * Find the link configuration values, rate and lane count for requested pixel
554 * clock @pclock. The @pclock is stored in the mode to be used in other
555 * functions later. The returned rate is downshifted from the current rate
556 * @current_bw.
557 *
558 * Return: Current link rate code, or -EINVAL.
559 */
zynqmp_dp_mode_configure(struct zynqmp_dp * dp,int pclock,u8 current_bw)560 static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock,
561 u8 current_bw)
562 {
563 int max_rate = dp->link_config.max_rate;
564 u8 bw_code;
565 u8 max_lanes = dp->link_config.max_lanes;
566 u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate);
567 u8 bpp = dp->config.bpp;
568 u8 lane_cnt;
569
570 /* Downshift from current bandwidth */
571 switch (current_bw) {
572 case DP_LINK_BW_5_4:
573 bw_code = DP_LINK_BW_2_7;
574 break;
575 case DP_LINK_BW_2_7:
576 bw_code = DP_LINK_BW_1_62;
577 break;
578 case DP_LINK_BW_1_62:
579 dev_err(dp->dev, "can't downshift. already lowest link rate\n");
580 return -EINVAL;
581 default:
582 /* If not given, start with max supported */
583 bw_code = max_link_rate_code;
584 break;
585 }
586
587 for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) {
588 int bw;
589 u32 rate;
590
591 bw = drm_dp_bw_code_to_link_rate(bw_code);
592 rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp);
593 if (pclock <= rate) {
594 dp->mode.bw_code = bw_code;
595 dp->mode.lane_cnt = lane_cnt;
596 dp->mode.pclock = pclock;
597 return dp->mode.bw_code;
598 }
599 }
600
601 dev_err(dp->dev, "failed to configure link values\n");
602
603 return -EINVAL;
604 }
605
606 /**
607 * zynqmp_dp_adjust_train - Adjust train values
608 * @dp: DisplayPort IP core structure
609 * @link_status: link status from sink which contains requested training values
610 */
zynqmp_dp_adjust_train(struct zynqmp_dp * dp,u8 link_status[DP_LINK_STATUS_SIZE])611 static void zynqmp_dp_adjust_train(struct zynqmp_dp *dp,
612 u8 link_status[DP_LINK_STATUS_SIZE])
613 {
614 u8 *train_set = dp->train_set;
615 u8 voltage = 0, preemphasis = 0;
616 u8 i;
617
618 for (i = 0; i < dp->mode.lane_cnt; i++) {
619 u8 v = drm_dp_get_adjust_request_voltage(link_status, i);
620 u8 p = drm_dp_get_adjust_request_pre_emphasis(link_status, i);
621
622 if (v > voltage)
623 voltage = v;
624
625 if (p > preemphasis)
626 preemphasis = p;
627 }
628
629 if (voltage >= DP_TRAIN_VOLTAGE_SWING_LEVEL_3)
630 voltage |= DP_TRAIN_MAX_SWING_REACHED;
631
632 if (preemphasis >= DP_TRAIN_PRE_EMPH_LEVEL_2)
633 preemphasis |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
634
635 for (i = 0; i < dp->mode.lane_cnt; i++)
636 train_set[i] = voltage | preemphasis;
637 }
638
639 /**
640 * zynqmp_dp_update_vs_emph - Update the training values
641 * @dp: DisplayPort IP core structure
642 *
643 * Update the training values based on the request from sink. The mapped values
644 * are predefined, and values(vs, pe, pc) are from the device manual.
645 *
646 * Return: 0 if vs and emph are updated successfully, or the error code returned
647 * by drm_dp_dpcd_write().
648 */
zynqmp_dp_update_vs_emph(struct zynqmp_dp * dp)649 static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp)
650 {
651 unsigned int i;
652 int ret;
653
654 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set,
655 dp->mode.lane_cnt);
656 if (ret < 0)
657 return ret;
658
659 for (i = 0; i < dp->mode.lane_cnt; i++) {
660 u32 reg = ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 + i * 4;
661 union phy_configure_opts opts = { 0 };
662 u8 train = dp->train_set[i];
663
664 opts.dp.voltage[0] = (train & DP_TRAIN_VOLTAGE_SWING_MASK)
665 >> DP_TRAIN_VOLTAGE_SWING_SHIFT;
666 opts.dp.pre[0] = (train & DP_TRAIN_PRE_EMPHASIS_MASK)
667 >> DP_TRAIN_PRE_EMPHASIS_SHIFT;
668
669 phy_configure(dp->phy[i], &opts);
670
671 zynqmp_dp_write(dp, reg, 0x2);
672 }
673
674 return 0;
675 }
676
677 /**
678 * zynqmp_dp_link_train_cr - Train clock recovery
679 * @dp: DisplayPort IP core structure
680 *
681 * Return: 0 if clock recovery train is done successfully, or corresponding
682 * error code.
683 */
zynqmp_dp_link_train_cr(struct zynqmp_dp * dp)684 static int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp)
685 {
686 u8 link_status[DP_LINK_STATUS_SIZE];
687 u8 lane_cnt = dp->mode.lane_cnt;
688 u8 vs = 0, tries = 0;
689 u16 max_tries, i;
690 bool cr_done;
691 int ret;
692
693 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET,
694 DP_TRAINING_PATTERN_1);
695 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
696 DP_TRAINING_PATTERN_1 |
697 DP_LINK_SCRAMBLING_DISABLE);
698 if (ret < 0)
699 return ret;
700
701 /*
702 * 256 loops should be maximum iterations for 4 lanes and 4 values.
703 * So, This loop should exit before 512 iterations
704 */
705 for (max_tries = 0; max_tries < 512; max_tries++) {
706 ret = zynqmp_dp_update_vs_emph(dp);
707 if (ret)
708 return ret;
709
710 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd);
711 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
712 if (ret < 0)
713 return ret;
714
715 cr_done = drm_dp_clock_recovery_ok(link_status, lane_cnt);
716 if (cr_done)
717 break;
718
719 for (i = 0; i < lane_cnt; i++)
720 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED))
721 break;
722 if (i == lane_cnt)
723 break;
724
725 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs)
726 tries++;
727 else
728 tries = 0;
729
730 if (tries == DP_MAX_TRAINING_TRIES)
731 break;
732
733 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
734 zynqmp_dp_adjust_train(dp, link_status);
735 }
736
737 if (!cr_done)
738 return -EIO;
739
740 return 0;
741 }
742
743 /**
744 * zynqmp_dp_link_train_ce - Train channel equalization
745 * @dp: DisplayPort IP core structure
746 *
747 * Return: 0 if channel equalization train is done successfully, or
748 * corresponding error code.
749 */
zynqmp_dp_link_train_ce(struct zynqmp_dp * dp)750 static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp)
751 {
752 u8 link_status[DP_LINK_STATUS_SIZE];
753 u8 lane_cnt = dp->mode.lane_cnt;
754 u32 pat, tries;
755 int ret;
756 bool ce_done;
757
758 if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 &&
759 dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED)
760 pat = DP_TRAINING_PATTERN_3;
761 else
762 pat = DP_TRAINING_PATTERN_2;
763
764 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, pat);
765 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
766 pat | DP_LINK_SCRAMBLING_DISABLE);
767 if (ret < 0)
768 return ret;
769
770 for (tries = 0; tries < DP_MAX_TRAINING_TRIES; tries++) {
771 ret = zynqmp_dp_update_vs_emph(dp);
772 if (ret)
773 return ret;
774
775 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd);
776 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
777 if (ret < 0)
778 return ret;
779
780 ce_done = drm_dp_channel_eq_ok(link_status, lane_cnt);
781 if (ce_done)
782 break;
783
784 zynqmp_dp_adjust_train(dp, link_status);
785 }
786
787 if (!ce_done)
788 return -EIO;
789
790 return 0;
791 }
792
793 /**
794 * zynqmp_dp_link_train - Train the link
795 * @dp: DisplayPort IP core structure
796 *
797 * Return: 0 if all trains are done successfully, or corresponding error code.
798 */
zynqmp_dp_train(struct zynqmp_dp * dp)799 static int zynqmp_dp_train(struct zynqmp_dp *dp)
800 {
801 u32 reg;
802 u8 bw_code = dp->mode.bw_code;
803 u8 lane_cnt = dp->mode.lane_cnt;
804 u8 aux_lane_cnt = lane_cnt;
805 bool enhanced;
806 int ret;
807
808 zynqmp_dp_write(dp, ZYNQMP_DP_LANE_COUNT_SET, lane_cnt);
809 enhanced = drm_dp_enhanced_frame_cap(dp->dpcd);
810 if (enhanced) {
811 zynqmp_dp_write(dp, ZYNQMP_DP_ENHANCED_FRAME_EN, 1);
812 aux_lane_cnt |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
813 }
814
815 if (dp->dpcd[3] & 0x1) {
816 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 1);
817 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL,
818 DP_SPREAD_AMP_0_5);
819 } else {
820 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 0);
821 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0);
822 }
823
824 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt);
825 if (ret < 0) {
826 dev_err(dp->dev, "failed to set lane count\n");
827 return ret;
828 }
829
830 ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
831 DP_SET_ANSI_8B10B);
832 if (ret < 0) {
833 dev_err(dp->dev, "failed to set ANSI 8B/10B encoding\n");
834 return ret;
835 }
836
837 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code);
838 if (ret < 0) {
839 dev_err(dp->dev, "failed to set DP bandwidth\n");
840 return ret;
841 }
842
843 zynqmp_dp_write(dp, ZYNQMP_DP_LINK_BW_SET, bw_code);
844 switch (bw_code) {
845 case DP_LINK_BW_1_62:
846 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G;
847 break;
848 case DP_LINK_BW_2_7:
849 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G;
850 break;
851 case DP_LINK_BW_5_4:
852 default:
853 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G;
854 break;
855 }
856
857 zynqmp_dp_write(dp, ZYNQMP_DP_PHY_CLOCK_SELECT, reg);
858 ret = zynqmp_dp_phy_ready(dp);
859 if (ret < 0)
860 return ret;
861
862 zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 1);
863 memset(dp->train_set, 0, sizeof(dp->train_set));
864 ret = zynqmp_dp_link_train_cr(dp);
865 if (ret)
866 return ret;
867
868 ret = zynqmp_dp_link_train_ce(dp);
869 if (ret)
870 return ret;
871
872 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
873 DP_TRAINING_PATTERN_DISABLE);
874 if (ret < 0) {
875 dev_err(dp->dev, "failed to disable training pattern\n");
876 return ret;
877 }
878 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET,
879 DP_TRAINING_PATTERN_DISABLE);
880
881 zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 0);
882
883 return 0;
884 }
885
886 /**
887 * zynqmp_dp_train_loop - Downshift the link rate during training
888 * @dp: DisplayPort IP core structure
889 *
890 * Train the link by downshifting the link rate if training is not successful.
891 */
zynqmp_dp_train_loop(struct zynqmp_dp * dp)892 static void zynqmp_dp_train_loop(struct zynqmp_dp *dp)
893 {
894 struct zynqmp_dp_mode *mode = &dp->mode;
895 u8 bw = mode->bw_code;
896 int ret;
897
898 do {
899 if (dp->status == connector_status_disconnected ||
900 !dp->enabled)
901 return;
902
903 ret = zynqmp_dp_train(dp);
904 if (!ret)
905 return;
906
907 ret = zynqmp_dp_mode_configure(dp, mode->pclock, bw);
908 if (ret < 0)
909 goto err_out;
910
911 bw = ret;
912 } while (bw >= DP_LINK_BW_1_62);
913
914 err_out:
915 dev_err(dp->dev, "failed to train the DP link\n");
916 }
917
918 /* -----------------------------------------------------------------------------
919 * DisplayPort AUX
920 */
921
922 #define AUX_READ_BIT 0x1
923
924 /**
925 * zynqmp_dp_aux_cmd_submit - Submit aux command
926 * @dp: DisplayPort IP core structure
927 * @cmd: aux command
928 * @addr: aux address
929 * @buf: buffer for command data
930 * @bytes: number of bytes for @buf
931 * @reply: reply code to be returned
932 *
933 * Submit an aux command. All aux related commands, native or i2c aux
934 * read/write, are submitted through this function. The function is mapped to
935 * the transfer function of struct drm_dp_aux. This function involves in
936 * multiple register reads/writes, thus synchronization is needed, and it is
937 * done by drm_dp_helper using @hw_mutex. The calling thread goes into sleep
938 * if there's no immediate reply to the command submission. The reply code is
939 * returned at @reply if @reply != NULL.
940 *
941 * Return: 0 if the command is submitted properly, or corresponding error code:
942 * -EBUSY when there is any request already being processed
943 * -ETIMEDOUT when receiving reply is timed out
944 * -EIO when received bytes are less than requested
945 */
zynqmp_dp_aux_cmd_submit(struct zynqmp_dp * dp,u32 cmd,u16 addr,u8 * buf,u8 bytes,u8 * reply)946 static int zynqmp_dp_aux_cmd_submit(struct zynqmp_dp *dp, u32 cmd, u16 addr,
947 u8 *buf, u8 bytes, u8 *reply)
948 {
949 bool is_read = (cmd & AUX_READ_BIT) ? true : false;
950 u32 reg, i;
951
952 reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
953 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST)
954 return -EBUSY;
955
956 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_ADDRESS, addr);
957 if (!is_read)
958 for (i = 0; i < bytes; i++)
959 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_WRITE_FIFO,
960 buf[i]);
961
962 reg = cmd << ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT;
963 if (!buf || !bytes)
964 reg |= ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY;
965 else
966 reg |= (bytes - 1) << ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT;
967 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_COMMAND, reg);
968
969 /* Wait for reply to be delivered upto 2ms */
970 for (i = 0; ; i++) {
971 reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
972 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY)
973 break;
974
975 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT ||
976 i == 2)
977 return -ETIMEDOUT;
978
979 usleep_range(1000, 1100);
980 }
981
982 reg = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_CODE);
983 if (reply)
984 *reply = reg;
985
986 if (is_read &&
987 (reg == ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK ||
988 reg == ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK)) {
989 reg = zynqmp_dp_read(dp, ZYNQMP_DP_REPLY_DATA_COUNT);
990 if ((reg & ZYNQMP_DP_REPLY_DATA_COUNT_MASK) != bytes)
991 return -EIO;
992
993 for (i = 0; i < bytes; i++)
994 buf[i] = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_DATA);
995 }
996
997 return 0;
998 }
999
1000 static ssize_t
zynqmp_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)1001 zynqmp_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1002 {
1003 struct zynqmp_dp *dp = container_of(aux, struct zynqmp_dp, aux);
1004 int ret;
1005 unsigned int i, iter;
1006
1007 /* Number of loops = timeout in msec / aux delay (400 usec) */
1008 iter = zynqmp_dp_aux_timeout_ms * 1000 / 400;
1009 iter = iter ? iter : 1;
1010
1011 for (i = 0; i < iter; i++) {
1012 ret = zynqmp_dp_aux_cmd_submit(dp, msg->request, msg->address,
1013 msg->buffer, msg->size,
1014 &msg->reply);
1015 if (!ret) {
1016 dev_dbg(dp->dev, "aux %d retries\n", i);
1017 return msg->size;
1018 }
1019
1020 if (dp->status == connector_status_disconnected) {
1021 dev_dbg(dp->dev, "no connected aux device\n");
1022 return -ENODEV;
1023 }
1024
1025 usleep_range(400, 500);
1026 }
1027
1028 dev_dbg(dp->dev, "failed to do aux transfer (%d)\n", ret);
1029
1030 return ret;
1031 }
1032
1033 /**
1034 * zynqmp_dp_aux_init - Initialize and register the DP AUX
1035 * @dp: DisplayPort IP core structure
1036 *
1037 * Program the AUX clock divider and filter and register the DP AUX adapter.
1038 *
1039 * Return: 0 on success, error value otherwise
1040 */
zynqmp_dp_aux_init(struct zynqmp_dp * dp)1041 static int zynqmp_dp_aux_init(struct zynqmp_dp *dp)
1042 {
1043 unsigned long rate;
1044 unsigned int w;
1045
1046 /*
1047 * The AUX_SIGNAL_WIDTH_FILTER is the number of APB clock cycles
1048 * corresponding to the AUX pulse. Allowable values are 8, 16, 24, 32,
1049 * 40 and 48. The AUX pulse width must be between 0.4µs and 0.6µs,
1050 * compute the w / 8 value corresponding to 0.4µs rounded up, and make
1051 * sure it stays below 0.6µs and within the allowable values.
1052 */
1053 rate = clk_get_rate(dp->dpsub->apb_clk);
1054 w = DIV_ROUND_UP(4 * rate, 1000 * 1000 * 10 * 8) * 8;
1055 if (w > 6 * rate / (1000 * 1000 * 10) || w > 48) {
1056 dev_err(dp->dev, "aclk frequency too high\n");
1057 return -EINVAL;
1058 }
1059
1060 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_CLK_DIVIDER,
1061 (w << ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT) |
1062 (rate / (1000 * 1000)));
1063
1064 dp->aux.name = "ZynqMP DP AUX";
1065 dp->aux.dev = dp->dev;
1066 dp->aux.drm_dev = dp->drm;
1067 dp->aux.transfer = zynqmp_dp_aux_transfer;
1068
1069 return drm_dp_aux_register(&dp->aux);
1070 }
1071
1072 /**
1073 * zynqmp_dp_aux_cleanup - Cleanup the DP AUX
1074 * @dp: DisplayPort IP core structure
1075 *
1076 * Unregister the DP AUX adapter.
1077 */
zynqmp_dp_aux_cleanup(struct zynqmp_dp * dp)1078 static void zynqmp_dp_aux_cleanup(struct zynqmp_dp *dp)
1079 {
1080 drm_dp_aux_unregister(&dp->aux);
1081 }
1082
1083 /* -----------------------------------------------------------------------------
1084 * DisplayPort Generic Support
1085 */
1086
1087 /**
1088 * zynqmp_dp_update_misc - Write the misc registers
1089 * @dp: DisplayPort IP core structure
1090 *
1091 * The misc register values are stored in the structure, and this
1092 * function applies the values into the registers.
1093 */
zynqmp_dp_update_misc(struct zynqmp_dp * dp)1094 static void zynqmp_dp_update_misc(struct zynqmp_dp *dp)
1095 {
1096 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC0, dp->config.misc0);
1097 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC1, dp->config.misc1);
1098 }
1099
1100 /**
1101 * zynqmp_dp_set_format - Set the input format
1102 * @dp: DisplayPort IP core structure
1103 * @format: input format
1104 * @bpc: bits per component
1105 *
1106 * Update misc register values based on input @format and @bpc.
1107 *
1108 * Return: 0 on success, or -EINVAL.
1109 */
zynqmp_dp_set_format(struct zynqmp_dp * dp,enum zynqmp_dpsub_format format,unsigned int bpc)1110 static int zynqmp_dp_set_format(struct zynqmp_dp *dp,
1111 enum zynqmp_dpsub_format format,
1112 unsigned int bpc)
1113 {
1114 static const struct drm_display_info *display;
1115 struct zynqmp_dp_config *config = &dp->config;
1116 unsigned int num_colors;
1117
1118 config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK;
1119 config->misc1 &= ~ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN;
1120
1121 switch (format) {
1122 case ZYNQMP_DPSUB_FORMAT_RGB:
1123 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB;
1124 num_colors = 3;
1125 break;
1126
1127 case ZYNQMP_DPSUB_FORMAT_YCRCB444:
1128 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444;
1129 num_colors = 3;
1130 break;
1131
1132 case ZYNQMP_DPSUB_FORMAT_YCRCB422:
1133 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422;
1134 num_colors = 2;
1135 break;
1136
1137 case ZYNQMP_DPSUB_FORMAT_YONLY:
1138 config->misc1 |= ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN;
1139 num_colors = 1;
1140 break;
1141
1142 default:
1143 dev_err(dp->dev, "Invalid colormetry in DT\n");
1144 return -EINVAL;
1145 }
1146
1147 display = &dp->connector.display_info;
1148 if (display->bpc && bpc > display->bpc) {
1149 dev_warn(dp->dev,
1150 "downgrading requested %ubpc to display limit %ubpc\n",
1151 bpc, display->bpc);
1152 bpc = display->bpc;
1153 }
1154
1155 config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK;
1156
1157 switch (bpc) {
1158 case 6:
1159 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6;
1160 break;
1161 case 8:
1162 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8;
1163 break;
1164 case 10:
1165 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10;
1166 break;
1167 case 12:
1168 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12;
1169 break;
1170 case 16:
1171 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16;
1172 break;
1173 default:
1174 dev_warn(dp->dev, "Not supported bpc (%u). fall back to 8bpc\n",
1175 bpc);
1176 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8;
1177 bpc = 8;
1178 break;
1179 }
1180
1181 /* Update the current bpp based on the format. */
1182 config->bpp = bpc * num_colors;
1183
1184 return 0;
1185 }
1186
1187 /**
1188 * zynqmp_dp_encoder_mode_set_transfer_unit - Set the transfer unit values
1189 * @dp: DisplayPort IP core structure
1190 * @mode: requested display mode
1191 *
1192 * Set the transfer unit, and calculate all transfer unit size related values.
1193 * Calculation is based on DP and IP core specification.
1194 */
1195 static void
zynqmp_dp_encoder_mode_set_transfer_unit(struct zynqmp_dp * dp,struct drm_display_mode * mode)1196 zynqmp_dp_encoder_mode_set_transfer_unit(struct zynqmp_dp *dp,
1197 struct drm_display_mode *mode)
1198 {
1199 u32 tu = ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF;
1200 u32 bw, vid_kbytes, avg_bytes_per_tu, init_wait;
1201
1202 /* Use the max transfer unit size (default) */
1203 zynqmp_dp_write(dp, ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE, tu);
1204
1205 vid_kbytes = mode->clock * (dp->config.bpp / 8);
1206 bw = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1207 avg_bytes_per_tu = vid_kbytes * tu / (dp->mode.lane_cnt * bw / 1000);
1208 zynqmp_dp_write(dp, ZYNQMP_DP_MIN_BYTES_PER_TU,
1209 avg_bytes_per_tu / 1000);
1210 zynqmp_dp_write(dp, ZYNQMP_DP_FRAC_BYTES_PER_TU,
1211 avg_bytes_per_tu % 1000);
1212
1213 /* Configure the initial wait cycle based on transfer unit size */
1214 if (tu < (avg_bytes_per_tu / 1000))
1215 init_wait = 0;
1216 else if ((avg_bytes_per_tu / 1000) <= 4)
1217 init_wait = tu;
1218 else
1219 init_wait = tu - avg_bytes_per_tu / 1000;
1220
1221 zynqmp_dp_write(dp, ZYNQMP_DP_INIT_WAIT, init_wait);
1222 }
1223
1224 /**
1225 * zynqmp_dp_encoder_mode_set_stream - Configure the main stream
1226 * @dp: DisplayPort IP core structure
1227 * @mode: requested display mode
1228 *
1229 * Configure the main stream based on the requested mode @mode. Calculation is
1230 * based on IP core specification.
1231 */
zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp * dp,const struct drm_display_mode * mode)1232 static void zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp *dp,
1233 const struct drm_display_mode *mode)
1234 {
1235 u8 lane_cnt = dp->mode.lane_cnt;
1236 u32 reg, wpl;
1237 unsigned int rate;
1238
1239 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HTOTAL, mode->htotal);
1240 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VTOTAL, mode->vtotal);
1241 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_POLARITY,
1242 (!!(mode->flags & DRM_MODE_FLAG_PVSYNC) <<
1243 ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT) |
1244 (!!(mode->flags & DRM_MODE_FLAG_PHSYNC) <<
1245 ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT));
1246 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSWIDTH,
1247 mode->hsync_end - mode->hsync_start);
1248 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSWIDTH,
1249 mode->vsync_end - mode->vsync_start);
1250 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HRES, mode->hdisplay);
1251 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VRES, mode->vdisplay);
1252 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSTART,
1253 mode->htotal - mode->hsync_start);
1254 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSTART,
1255 mode->vtotal - mode->vsync_start);
1256
1257 /* In synchronous mode, set the diviers */
1258 if (dp->config.misc0 & ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK) {
1259 reg = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1260 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_N_VID, reg);
1261 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_M_VID, mode->clock);
1262 rate = zynqmp_disp_get_audio_clk_rate(dp->dpsub->disp);
1263 if (rate) {
1264 dev_dbg(dp->dev, "Audio rate: %d\n", rate / 512);
1265 zynqmp_dp_write(dp, ZYNQMP_DP_TX_N_AUD, reg);
1266 zynqmp_dp_write(dp, ZYNQMP_DP_TX_M_AUD, rate / 1000);
1267 }
1268 }
1269
1270 /* Only 2 channel audio is supported now */
1271 if (zynqmp_disp_audio_enabled(dp->dpsub->disp))
1272 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CHANNELS, 1);
1273
1274 zynqmp_dp_write(dp, ZYNQMP_DP_USER_PIX_WIDTH, 1);
1275
1276 /* Translate to the native 16 bit datapath based on IP core spec */
1277 wpl = (mode->hdisplay * dp->config.bpp + 15) / 16;
1278 reg = wpl + wpl % lane_cnt - lane_cnt;
1279 zynqmp_dp_write(dp, ZYNQMP_DP_USER_DATA_COUNT_PER_LANE, reg);
1280 }
1281
1282 /* -----------------------------------------------------------------------------
1283 * DRM Connector
1284 */
1285
1286 static enum drm_connector_status
zynqmp_dp_connector_detect(struct drm_connector * connector,bool force)1287 zynqmp_dp_connector_detect(struct drm_connector *connector, bool force)
1288 {
1289 struct zynqmp_dp *dp = connector_to_dp(connector);
1290 struct zynqmp_dp_link_config *link_config = &dp->link_config;
1291 u32 state, i;
1292 int ret;
1293
1294 /*
1295 * This is from heuristic. It takes some delay (ex, 100 ~ 500 msec) to
1296 * get the HPD signal with some monitors.
1297 */
1298 for (i = 0; i < 10; i++) {
1299 state = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
1300 if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD)
1301 break;
1302 msleep(100);
1303 }
1304
1305 if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD) {
1306 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd,
1307 sizeof(dp->dpcd));
1308 if (ret < 0) {
1309 dev_dbg(dp->dev, "DPCD read failed");
1310 goto disconnected;
1311 }
1312
1313 link_config->max_rate = min_t(int,
1314 drm_dp_max_link_rate(dp->dpcd),
1315 DP_HIGH_BIT_RATE2);
1316 link_config->max_lanes = min_t(u8,
1317 drm_dp_max_lane_count(dp->dpcd),
1318 dp->num_lanes);
1319
1320 dp->status = connector_status_connected;
1321 return connector_status_connected;
1322 }
1323
1324 disconnected:
1325 dp->status = connector_status_disconnected;
1326 return connector_status_disconnected;
1327 }
1328
zynqmp_dp_connector_get_modes(struct drm_connector * connector)1329 static int zynqmp_dp_connector_get_modes(struct drm_connector *connector)
1330 {
1331 struct zynqmp_dp *dp = connector_to_dp(connector);
1332 struct edid *edid;
1333 int ret;
1334
1335 edid = drm_get_edid(connector, &dp->aux.ddc);
1336 if (!edid)
1337 return 0;
1338
1339 drm_connector_update_edid_property(connector, edid);
1340 ret = drm_add_edid_modes(connector, edid);
1341 kfree(edid);
1342
1343 return ret;
1344 }
1345
1346 static struct drm_encoder *
zynqmp_dp_connector_best_encoder(struct drm_connector * connector)1347 zynqmp_dp_connector_best_encoder(struct drm_connector *connector)
1348 {
1349 struct zynqmp_dp *dp = connector_to_dp(connector);
1350
1351 return &dp->encoder;
1352 }
1353
zynqmp_dp_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1354 static int zynqmp_dp_connector_mode_valid(struct drm_connector *connector,
1355 struct drm_display_mode *mode)
1356 {
1357 struct zynqmp_dp *dp = connector_to_dp(connector);
1358 u8 max_lanes = dp->link_config.max_lanes;
1359 u8 bpp = dp->config.bpp;
1360 int max_rate = dp->link_config.max_rate;
1361 int rate;
1362
1363 if (mode->clock > ZYNQMP_MAX_FREQ) {
1364 dev_dbg(dp->dev, "filtered the mode, %s,for high pixel rate\n",
1365 mode->name);
1366 drm_mode_debug_printmodeline(mode);
1367 return MODE_CLOCK_HIGH;
1368 }
1369
1370 /* Check with link rate and lane count */
1371 rate = zynqmp_dp_max_rate(max_rate, max_lanes, bpp);
1372 if (mode->clock > rate) {
1373 dev_dbg(dp->dev, "filtered the mode, %s,for high pixel rate\n",
1374 mode->name);
1375 drm_mode_debug_printmodeline(mode);
1376 return MODE_CLOCK_HIGH;
1377 }
1378
1379 return MODE_OK;
1380 }
1381
1382 static const struct drm_connector_funcs zynqmp_dp_connector_funcs = {
1383 .detect = zynqmp_dp_connector_detect,
1384 .fill_modes = drm_helper_probe_single_connector_modes,
1385 .destroy = drm_connector_cleanup,
1386 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1387 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1388 .reset = drm_atomic_helper_connector_reset,
1389 };
1390
1391 static const struct drm_connector_helper_funcs
1392 zynqmp_dp_connector_helper_funcs = {
1393 .get_modes = zynqmp_dp_connector_get_modes,
1394 .best_encoder = zynqmp_dp_connector_best_encoder,
1395 .mode_valid = zynqmp_dp_connector_mode_valid,
1396 };
1397
1398 /* -----------------------------------------------------------------------------
1399 * DRM Encoder
1400 */
1401
zynqmp_dp_encoder_enable(struct drm_encoder * encoder)1402 static void zynqmp_dp_encoder_enable(struct drm_encoder *encoder)
1403 {
1404 struct zynqmp_dp *dp = encoder_to_dp(encoder);
1405 unsigned int i;
1406 int ret = 0;
1407
1408 pm_runtime_get_sync(dp->dev);
1409 dp->enabled = true;
1410 zynqmp_dp_update_misc(dp);
1411 if (zynqmp_disp_audio_enabled(dp->dpsub->disp))
1412 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 1);
1413 zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 0);
1414 if (dp->status == connector_status_connected) {
1415 for (i = 0; i < 3; i++) {
1416 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER,
1417 DP_SET_POWER_D0);
1418 if (ret == 1)
1419 break;
1420 usleep_range(300, 500);
1421 }
1422 /* Some monitors take time to wake up properly */
1423 msleep(zynqmp_dp_power_on_delay_ms);
1424 }
1425 if (ret != 1)
1426 dev_dbg(dp->dev, "DP aux failed\n");
1427 else
1428 zynqmp_dp_train_loop(dp);
1429 zynqmp_dp_write(dp, ZYNQMP_DP_SOFTWARE_RESET,
1430 ZYNQMP_DP_SOFTWARE_RESET_ALL);
1431 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 1);
1432 }
1433
zynqmp_dp_encoder_disable(struct drm_encoder * encoder)1434 static void zynqmp_dp_encoder_disable(struct drm_encoder *encoder)
1435 {
1436 struct zynqmp_dp *dp = encoder_to_dp(encoder);
1437
1438 dp->enabled = false;
1439 cancel_delayed_work(&dp->hpd_work);
1440 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 0);
1441 drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3);
1442 zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN,
1443 ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL);
1444 if (zynqmp_disp_audio_enabled(dp->dpsub->disp))
1445 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 0);
1446 pm_runtime_put_sync(dp->dev);
1447 }
1448
1449 static void
zynqmp_dp_encoder_atomic_mode_set(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * connector_state)1450 zynqmp_dp_encoder_atomic_mode_set(struct drm_encoder *encoder,
1451 struct drm_crtc_state *crtc_state,
1452 struct drm_connector_state *connector_state)
1453 {
1454 struct zynqmp_dp *dp = encoder_to_dp(encoder);
1455 struct drm_display_mode *mode = &crtc_state->mode;
1456 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1457 u8 max_lanes = dp->link_config.max_lanes;
1458 u8 bpp = dp->config.bpp;
1459 int rate, max_rate = dp->link_config.max_rate;
1460 int ret;
1461
1462 zynqmp_dp_set_format(dp, ZYNQMP_DPSUB_FORMAT_RGB, 8);
1463
1464 /* Check again as bpp or format might have been chagned */
1465 rate = zynqmp_dp_max_rate(max_rate, max_lanes, bpp);
1466 if (mode->clock > rate) {
1467 dev_err(dp->dev, "the mode, %s,has too high pixel rate\n",
1468 mode->name);
1469 drm_mode_debug_printmodeline(mode);
1470 }
1471
1472 ret = zynqmp_dp_mode_configure(dp, adjusted_mode->clock, 0);
1473 if (ret < 0)
1474 return;
1475
1476 zynqmp_dp_encoder_mode_set_transfer_unit(dp, adjusted_mode);
1477 zynqmp_dp_encoder_mode_set_stream(dp, adjusted_mode);
1478 }
1479
1480 #define ZYNQMP_DP_MIN_H_BACKPORCH 20
1481
1482 static int
zynqmp_dp_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1483 zynqmp_dp_encoder_atomic_check(struct drm_encoder *encoder,
1484 struct drm_crtc_state *crtc_state,
1485 struct drm_connector_state *conn_state)
1486 {
1487 struct drm_display_mode *mode = &crtc_state->mode;
1488 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1489 int diff = mode->htotal - mode->hsync_end;
1490
1491 /*
1492 * ZynqMP DP requires horizontal backporch to be greater than 12.
1493 * This limitation may not be compatible with the sink device.
1494 */
1495 if (diff < ZYNQMP_DP_MIN_H_BACKPORCH) {
1496 int vrefresh = (adjusted_mode->clock * 1000) /
1497 (adjusted_mode->vtotal * adjusted_mode->htotal);
1498
1499 dev_dbg(encoder->dev->dev, "hbackporch adjusted: %d to %d",
1500 diff, ZYNQMP_DP_MIN_H_BACKPORCH - diff);
1501 diff = ZYNQMP_DP_MIN_H_BACKPORCH - diff;
1502 adjusted_mode->htotal += diff;
1503 adjusted_mode->clock = adjusted_mode->vtotal *
1504 adjusted_mode->htotal * vrefresh / 1000;
1505 }
1506
1507 return 0;
1508 }
1509
1510 static const struct drm_encoder_helper_funcs zynqmp_dp_encoder_helper_funcs = {
1511 .enable = zynqmp_dp_encoder_enable,
1512 .disable = zynqmp_dp_encoder_disable,
1513 .atomic_mode_set = zynqmp_dp_encoder_atomic_mode_set,
1514 .atomic_check = zynqmp_dp_encoder_atomic_check,
1515 };
1516
1517 /* -----------------------------------------------------------------------------
1518 * Interrupt Handling
1519 */
1520
1521 /**
1522 * zynqmp_dp_enable_vblank - Enable vblank
1523 * @dp: DisplayPort IP core structure
1524 *
1525 * Enable vblank interrupt
1526 */
zynqmp_dp_enable_vblank(struct zynqmp_dp * dp)1527 void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp)
1528 {
1529 zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_VBLANK_START);
1530 }
1531
1532 /**
1533 * zynqmp_dp_disable_vblank - Disable vblank
1534 * @dp: DisplayPort IP core structure
1535 *
1536 * Disable vblank interrupt
1537 */
zynqmp_dp_disable_vblank(struct zynqmp_dp * dp)1538 void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp)
1539 {
1540 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_VBLANK_START);
1541 }
1542
zynqmp_dp_hpd_work_func(struct work_struct * work)1543 static void zynqmp_dp_hpd_work_func(struct work_struct *work)
1544 {
1545 struct zynqmp_dp *dp;
1546
1547 dp = container_of(work, struct zynqmp_dp, hpd_work.work);
1548
1549 if (dp->drm)
1550 drm_helper_hpd_irq_event(dp->drm);
1551 }
1552
zynqmp_dp_irq_handler(int irq,void * data)1553 static irqreturn_t zynqmp_dp_irq_handler(int irq, void *data)
1554 {
1555 struct zynqmp_dp *dp = (struct zynqmp_dp *)data;
1556 u32 status, mask;
1557
1558 status = zynqmp_dp_read(dp, ZYNQMP_DP_INT_STATUS);
1559 mask = zynqmp_dp_read(dp, ZYNQMP_DP_INT_MASK);
1560 if (!(status & ~mask))
1561 return IRQ_NONE;
1562
1563 /* dbg for diagnostic, but not much that the driver can do */
1564 if (status & ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK)
1565 dev_dbg_ratelimited(dp->dev, "underflow interrupt\n");
1566 if (status & ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK)
1567 dev_dbg_ratelimited(dp->dev, "overflow interrupt\n");
1568
1569 zynqmp_dp_write(dp, ZYNQMP_DP_INT_STATUS, status);
1570
1571 if (status & ZYNQMP_DP_INT_VBLANK_START)
1572 zynqmp_disp_handle_vblank(dp->dpsub->disp);
1573
1574 if (status & ZYNQMP_DP_INT_HPD_EVENT)
1575 schedule_delayed_work(&dp->hpd_work, 0);
1576
1577 if (status & ZYNQMP_DP_INT_HPD_IRQ) {
1578 int ret;
1579 u8 status[DP_LINK_STATUS_SIZE + 2];
1580
1581 ret = drm_dp_dpcd_read(&dp->aux, DP_SINK_COUNT, status,
1582 DP_LINK_STATUS_SIZE + 2);
1583 if (ret < 0)
1584 goto handled;
1585
1586 if (status[4] & DP_LINK_STATUS_UPDATED ||
1587 !drm_dp_clock_recovery_ok(&status[2], dp->mode.lane_cnt) ||
1588 !drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt)) {
1589 zynqmp_dp_train_loop(dp);
1590 }
1591 }
1592
1593 handled:
1594 return IRQ_HANDLED;
1595 }
1596
1597 /* -----------------------------------------------------------------------------
1598 * Initialization & Cleanup
1599 */
1600
zynqmp_dp_drm_init(struct zynqmp_dpsub * dpsub)1601 int zynqmp_dp_drm_init(struct zynqmp_dpsub *dpsub)
1602 {
1603 struct zynqmp_dp *dp = dpsub->dp;
1604 struct drm_encoder *encoder = &dp->encoder;
1605 struct drm_connector *connector = &dp->connector;
1606 int ret;
1607
1608 dp->config.misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK;
1609 zynqmp_dp_set_format(dp, ZYNQMP_DPSUB_FORMAT_RGB, 8);
1610
1611 /* Create the DRM encoder and connector. */
1612 encoder->possible_crtcs |= zynqmp_disp_get_crtc_mask(dpsub->disp);
1613 drm_simple_encoder_init(dp->drm, encoder, DRM_MODE_ENCODER_TMDS);
1614 drm_encoder_helper_add(encoder, &zynqmp_dp_encoder_helper_funcs);
1615
1616 connector->polled = DRM_CONNECTOR_POLL_HPD;
1617 ret = drm_connector_init(encoder->dev, connector,
1618 &zynqmp_dp_connector_funcs,
1619 DRM_MODE_CONNECTOR_DisplayPort);
1620 if (ret) {
1621 dev_err(dp->dev, "failed to create the DRM connector\n");
1622 return ret;
1623 }
1624
1625 drm_connector_helper_add(connector, &zynqmp_dp_connector_helper_funcs);
1626 drm_connector_register(connector);
1627 drm_connector_attach_encoder(connector, encoder);
1628
1629 /* Initialize and register the AUX adapter. */
1630 ret = zynqmp_dp_aux_init(dp);
1631 if (ret) {
1632 dev_err(dp->dev, "failed to initialize DP aux\n");
1633 return ret;
1634 }
1635
1636 /* Now that initialisation is complete, enable interrupts. */
1637 zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_ALL);
1638
1639 return 0;
1640 }
1641
zynqmp_dp_probe(struct zynqmp_dpsub * dpsub,struct drm_device * drm)1642 int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub, struct drm_device *drm)
1643 {
1644 struct platform_device *pdev = to_platform_device(dpsub->dev);
1645 struct zynqmp_dp *dp;
1646 struct resource *res;
1647 int ret;
1648
1649 dp = drmm_kzalloc(drm, sizeof(*dp), GFP_KERNEL);
1650 if (!dp)
1651 return -ENOMEM;
1652
1653 dp->dev = &pdev->dev;
1654 dp->dpsub = dpsub;
1655 dp->status = connector_status_disconnected;
1656 dp->drm = drm;
1657
1658 INIT_DELAYED_WORK(&dp->hpd_work, zynqmp_dp_hpd_work_func);
1659
1660 dpsub->dp = dp;
1661
1662 /* Acquire all resources (IOMEM, IRQ and PHYs). */
1663 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dp");
1664 dp->iomem = devm_ioremap_resource(dp->dev, res);
1665 if (IS_ERR(dp->iomem))
1666 return PTR_ERR(dp->iomem);
1667
1668 dp->irq = platform_get_irq(pdev, 0);
1669 if (dp->irq < 0)
1670 return dp->irq;
1671
1672 dp->reset = devm_reset_control_get(dp->dev, NULL);
1673 if (IS_ERR(dp->reset)) {
1674 if (PTR_ERR(dp->reset) != -EPROBE_DEFER)
1675 dev_err(dp->dev, "failed to get reset: %ld\n",
1676 PTR_ERR(dp->reset));
1677 return PTR_ERR(dp->reset);
1678 }
1679
1680 ret = zynqmp_dp_reset(dp, false);
1681 if (ret < 0)
1682 return ret;
1683
1684 ret = zynqmp_dp_phy_probe(dp);
1685 if (ret)
1686 goto err_reset;
1687
1688 /* Initialize the hardware. */
1689 zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN,
1690 ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL);
1691 zynqmp_dp_set(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET);
1692 zynqmp_dp_write(dp, ZYNQMP_DP_FORCE_SCRAMBLER_RESET, 1);
1693 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0);
1694 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff);
1695
1696 ret = zynqmp_dp_phy_init(dp);
1697 if (ret)
1698 goto err_reset;
1699
1700 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 1);
1701
1702 /*
1703 * Now that the hardware is initialized and won't generate spurious
1704 * interrupts, request the IRQ.
1705 */
1706 ret = devm_request_threaded_irq(dp->dev, dp->irq, NULL,
1707 zynqmp_dp_irq_handler, IRQF_ONESHOT,
1708 dev_name(dp->dev), dp);
1709 if (ret < 0)
1710 goto err_phy_exit;
1711
1712 dev_dbg(dp->dev, "ZynqMP DisplayPort Tx probed with %u lanes\n",
1713 dp->num_lanes);
1714
1715 return 0;
1716
1717 err_phy_exit:
1718 zynqmp_dp_phy_exit(dp);
1719 err_reset:
1720 zynqmp_dp_reset(dp, true);
1721
1722 return ret;
1723 }
1724
zynqmp_dp_remove(struct zynqmp_dpsub * dpsub)1725 void zynqmp_dp_remove(struct zynqmp_dpsub *dpsub)
1726 {
1727 struct zynqmp_dp *dp = dpsub->dp;
1728
1729 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_ALL);
1730 disable_irq(dp->irq);
1731
1732 cancel_delayed_work_sync(&dp->hpd_work);
1733 zynqmp_dp_aux_cleanup(dp);
1734
1735 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0);
1736 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff);
1737
1738 zynqmp_dp_phy_exit(dp);
1739 zynqmp_dp_reset(dp, true);
1740 }
1741
