1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * 26 * Contributors: 27 * Bing Niu <bing.niu@intel.com> 28 * Xu Han <xu.han@intel.com> 29 * Ping Gao <ping.a.gao@intel.com> 30 * Xiaoguang Chen <xiaoguang.chen@intel.com> 31 * Yang Liu <yang2.liu@intel.com> 32 * Tina Zhang <tina.zhang@intel.com> 33 * 34 */ 35 36 #ifndef _GVT_FB_DECODER_H_ 37 #define _GVT_FB_DECODER_H_ 38 39 #define _PLANE_CTL_FORMAT_SHIFT 24 40 #define _PLANE_CTL_TILED_SHIFT 10 41 #define _PIPE_V_SRCSZ_SHIFT 0 42 #define _PIPE_V_SRCSZ_MASK (0xfff << _PIPE_V_SRCSZ_SHIFT) 43 #define _PIPE_H_SRCSZ_SHIFT 16 44 #define _PIPE_H_SRCSZ_MASK (0x1fff << _PIPE_H_SRCSZ_SHIFT) 45 46 #define _PRI_PLANE_FMT_SHIFT 26 47 #define _PRI_PLANE_STRIDE_MASK (0x3ff << 6) 48 #define _PRI_PLANE_X_OFF_SHIFT 0 49 #define _PRI_PLANE_X_OFF_MASK (0x1fff << _PRI_PLANE_X_OFF_SHIFT) 50 #define _PRI_PLANE_Y_OFF_SHIFT 16 51 #define _PRI_PLANE_Y_OFF_MASK (0xfff << _PRI_PLANE_Y_OFF_SHIFT) 52 53 #define _CURSOR_MODE 0x3f 54 #define _CURSOR_ALPHA_FORCE_SHIFT 8 55 #define _CURSOR_ALPHA_FORCE_MASK (0x3 << _CURSOR_ALPHA_FORCE_SHIFT) 56 #define _CURSOR_ALPHA_PLANE_SHIFT 10 57 #define _CURSOR_ALPHA_PLANE_MASK (0x3 << _CURSOR_ALPHA_PLANE_SHIFT) 58 #define _CURSOR_POS_X_SHIFT 0 59 #define _CURSOR_POS_X_MASK (0x1fff << _CURSOR_POS_X_SHIFT) 60 #define _CURSOR_SIGN_X_SHIFT 15 61 #define _CURSOR_SIGN_X_MASK (1 << _CURSOR_SIGN_X_SHIFT) 62 #define _CURSOR_POS_Y_SHIFT 16 63 #define _CURSOR_POS_Y_MASK (0xfff << _CURSOR_POS_Y_SHIFT) 64 #define _CURSOR_SIGN_Y_SHIFT 31 65 #define _CURSOR_SIGN_Y_MASK (1 << _CURSOR_SIGN_Y_SHIFT) 66 67 #define _SPRITE_FMT_SHIFT 25 68 #define _SPRITE_COLOR_ORDER_SHIFT 20 69 #define _SPRITE_YUV_ORDER_SHIFT 16 70 #define _SPRITE_STRIDE_SHIFT 6 71 #define _SPRITE_STRIDE_MASK (0x1ff << _SPRITE_STRIDE_SHIFT) 72 #define _SPRITE_SIZE_WIDTH_SHIFT 0 73 #define _SPRITE_SIZE_HEIGHT_SHIFT 16 74 #define _SPRITE_SIZE_WIDTH_MASK (0x1fff << _SPRITE_SIZE_WIDTH_SHIFT) 75 #define _SPRITE_SIZE_HEIGHT_MASK (0xfff << _SPRITE_SIZE_HEIGHT_SHIFT) 76 #define _SPRITE_POS_X_SHIFT 0 77 #define _SPRITE_POS_Y_SHIFT 16 78 #define _SPRITE_POS_X_MASK (0x1fff << _SPRITE_POS_X_SHIFT) 79 #define _SPRITE_POS_Y_MASK (0xfff << _SPRITE_POS_Y_SHIFT) 80 #define _SPRITE_OFFSET_START_X_SHIFT 0 81 #define _SPRITE_OFFSET_START_Y_SHIFT 16 82 #define _SPRITE_OFFSET_START_X_MASK (0x1fff << _SPRITE_OFFSET_START_X_SHIFT) 83 #define _SPRITE_OFFSET_START_Y_MASK (0xfff << _SPRITE_OFFSET_START_Y_SHIFT) 84 85 enum GVT_FB_EVENT { 86 FB_MODE_SET_START = 1, 87 FB_MODE_SET_END, 88 FB_DISPLAY_FLIP, 89 }; 90 91 enum DDI_PORT { 92 DDI_PORT_NONE = 0, 93 DDI_PORT_B = 1, 94 DDI_PORT_C = 2, 95 DDI_PORT_D = 3, 96 DDI_PORT_E = 4 97 }; 98 99 struct intel_gvt; 100 101 /* color space conversion and gamma correction are not included */ 102 struct intel_vgpu_primary_plane_format { 103 u8 enabled; /* plane is enabled */ 104 u32 tiled; /* tiling mode: linear, X-tiled, Y tiled, etc */ 105 u8 bpp; /* bits per pixel */ 106 u32 hw_format; /* format field in the PRI_CTL register */ 107 u32 drm_format; /* format in DRM definition */ 108 u32 base; /* framebuffer base in graphics memory */ 109 u64 base_gpa; 110 u32 x_offset; /* in pixels */ 111 u32 y_offset; /* in lines */ 112 u32 width; /* in pixels */ 113 u32 height; /* in lines */ 114 u32 stride; /* in bytes */ 115 }; 116 117 struct intel_vgpu_sprite_plane_format { 118 u8 enabled; /* plane is enabled */ 119 u8 tiled; /* X-tiled */ 120 u8 bpp; /* bits per pixel */ 121 u32 hw_format; /* format field in the SPR_CTL register */ 122 u32 drm_format; /* format in DRM definition */ 123 u32 base; /* sprite base in graphics memory */ 124 u64 base_gpa; 125 u32 x_pos; /* in pixels */ 126 u32 y_pos; /* in lines */ 127 u32 x_offset; /* in pixels */ 128 u32 y_offset; /* in lines */ 129 u32 width; /* in pixels */ 130 u32 height; /* in lines */ 131 u32 stride; /* in bytes */ 132 }; 133 134 struct intel_vgpu_cursor_plane_format { 135 u8 enabled; 136 u8 mode; /* cursor mode select */ 137 u8 bpp; /* bits per pixel */ 138 u32 drm_format; /* format in DRM definition */ 139 u32 base; /* cursor base in graphics memory */ 140 u64 base_gpa; 141 u32 x_pos; /* in pixels */ 142 u32 y_pos; /* in lines */ 143 u8 x_sign; /* X Position Sign */ 144 u8 y_sign; /* Y Position Sign */ 145 u32 width; /* in pixels */ 146 u32 height; /* in lines */ 147 u32 x_hot; /* in pixels */ 148 u32 y_hot; /* in pixels */ 149 }; 150 151 struct intel_vgpu_pipe_format { 152 struct intel_vgpu_primary_plane_format primary; 153 struct intel_vgpu_sprite_plane_format sprite; 154 struct intel_vgpu_cursor_plane_format cursor; 155 enum DDI_PORT ddi_port; /* the DDI port that pipe is connected to */ 156 }; 157 158 struct intel_vgpu_fb_format { 159 struct intel_vgpu_pipe_format pipes[I915_MAX_PIPES]; 160 }; 161 162 int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 163 struct intel_vgpu_primary_plane_format *plane); 164 int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, 165 struct intel_vgpu_cursor_plane_format *plane); 166 int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, 167 struct intel_vgpu_sprite_plane_format *plane); 168 169 #endif 170
