1 /*
2 * arch/xtensa/kernel/setup.c
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995 Linus Torvalds
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
10 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
11 *
12 * Chris Zankel <chris@zankel.net>
13 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
14 * Kevin Chea
15 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
16 */
17
18 #include <linux/errno.h>
19 #include <linux/init.h>
20 #include <linux/mm.h>
21 #include <linux/proc_fs.h>
22 #include <linux/screen_info.h>
23 #include <linux/kernel.h>
24 #include <linux/percpu.h>
25 #include <linux/reboot.h>
26 #include <linux/cpu.h>
27 #include <linux/of.h>
28 #include <linux/of_fdt.h>
29
30 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
31 # include <linux/console.h>
32 #endif
33
34 #ifdef CONFIG_PROC_FS
35 # include <linux/seq_file.h>
36 #endif
37
38 #include <asm/bootparam.h>
39 #include <asm/kasan.h>
40 #include <asm/mmu_context.h>
41 #include <asm/page.h>
42 #include <asm/param.h>
43 #include <asm/platform.h>
44 #include <asm/processor.h>
45 #include <asm/sections.h>
46 #include <asm/setup.h>
47 #include <asm/smp.h>
48 #include <asm/sysmem.h>
49 #include <asm/timex.h>
50 #include <asm/traps.h>
51
52 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
53 struct screen_info screen_info = {
54 .orig_x = 0,
55 .orig_y = 24,
56 .orig_video_cols = 80,
57 .orig_video_lines = 24,
58 .orig_video_isVGA = 1,
59 .orig_video_points = 16,
60 };
61 #endif
62
63 #ifdef CONFIG_BLK_DEV_INITRD
64 extern unsigned long initrd_start;
65 extern unsigned long initrd_end;
66 extern int initrd_below_start_ok;
67 #endif
68
69 #ifdef CONFIG_USE_OF
70 void *dtb_start = __dtb_start;
71 #endif
72
73 extern unsigned long loops_per_jiffy;
74
75 /* Command line specified as configuration option. */
76
77 static char __initdata command_line[COMMAND_LINE_SIZE];
78
79 #ifdef CONFIG_CMDLINE_BOOL
80 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
81 #endif
82
83 #ifdef CONFIG_PARSE_BOOTPARAM
84 /*
85 * Boot parameter parsing.
86 *
87 * The Xtensa port uses a list of variable-sized tags to pass data to
88 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
89 * to be recognised. The list is terminated with a zero-sized
90 * BP_TAG_LAST tag.
91 */
92
93 typedef struct tagtable {
94 u32 tag;
95 int (*parse)(const bp_tag_t*);
96 } tagtable_t;
97
98 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
99 __section(".taglist") __attribute__((used)) = { tag, fn }
100
101 /* parse current tag */
102
parse_tag_mem(const bp_tag_t * tag)103 static int __init parse_tag_mem(const bp_tag_t *tag)
104 {
105 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
106
107 if (mi->type != MEMORY_TYPE_CONVENTIONAL)
108 return -1;
109
110 return memblock_add(mi->start, mi->end - mi->start);
111 }
112
113 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
114
115 #ifdef CONFIG_BLK_DEV_INITRD
116
parse_tag_initrd(const bp_tag_t * tag)117 static int __init parse_tag_initrd(const bp_tag_t* tag)
118 {
119 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
120
121 initrd_start = (unsigned long)__va(mi->start);
122 initrd_end = (unsigned long)__va(mi->end);
123
124 return 0;
125 }
126
127 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
128
129 #endif /* CONFIG_BLK_DEV_INITRD */
130
131 #ifdef CONFIG_USE_OF
132
parse_tag_fdt(const bp_tag_t * tag)133 static int __init parse_tag_fdt(const bp_tag_t *tag)
134 {
135 dtb_start = __va(tag->data[0]);
136 return 0;
137 }
138
139 __tagtable(BP_TAG_FDT, parse_tag_fdt);
140
141 #endif /* CONFIG_USE_OF */
142
parse_tag_cmdline(const bp_tag_t * tag)143 static int __init parse_tag_cmdline(const bp_tag_t* tag)
144 {
145 strscpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
146 return 0;
147 }
148
149 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
150
parse_bootparam(const bp_tag_t * tag)151 static int __init parse_bootparam(const bp_tag_t* tag)
152 {
153 extern tagtable_t __tagtable_begin, __tagtable_end;
154 tagtable_t *t;
155
156 /* Boot parameters must start with a BP_TAG_FIRST tag. */
157
158 if (tag->id != BP_TAG_FIRST) {
159 pr_warn("Invalid boot parameters!\n");
160 return 0;
161 }
162
163 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
164
165 /* Parse all tags. */
166
167 while (tag != NULL && tag->id != BP_TAG_LAST) {
168 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
169 if (tag->id == t->tag) {
170 t->parse(tag);
171 break;
172 }
173 }
174 if (t == &__tagtable_end)
175 pr_warn("Ignoring tag 0x%08x\n", tag->id);
176 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
177 }
178
179 return 0;
180 }
181 #else
parse_bootparam(const bp_tag_t * tag)182 static int __init parse_bootparam(const bp_tag_t *tag)
183 {
184 pr_info("Ignoring boot parameters at %p\n", tag);
185 return 0;
186 }
187 #endif
188
189 #ifdef CONFIG_USE_OF
190
191 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
192 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
193 EXPORT_SYMBOL(xtensa_kio_paddr);
194
xtensa_dt_io_area(unsigned long node,const char * uname,int depth,void * data)195 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
196 int depth, void *data)
197 {
198 const __be32 *ranges;
199 int len;
200
201 if (depth > 1)
202 return 0;
203
204 if (!of_flat_dt_is_compatible(node, "simple-bus"))
205 return 0;
206
207 ranges = of_get_flat_dt_prop(node, "ranges", &len);
208 if (!ranges)
209 return 1;
210 if (len == 0)
211 return 1;
212
213 xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
214 /* round down to nearest 256MB boundary */
215 xtensa_kio_paddr &= 0xf0000000;
216
217 init_kio();
218
219 return 1;
220 }
221 #else
xtensa_dt_io_area(unsigned long node,const char * uname,int depth,void * data)222 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
223 int depth, void *data)
224 {
225 return 1;
226 }
227 #endif
228
early_init_devtree(void * params)229 void __init early_init_devtree(void *params)
230 {
231 early_init_dt_scan(params);
232 of_scan_flat_dt(xtensa_dt_io_area, NULL);
233
234 if (!command_line[0])
235 strscpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
236 }
237
238 #endif /* CONFIG_USE_OF */
239
240 /*
241 * Initialize architecture. (Early stage)
242 */
243
init_arch(bp_tag_t * bp_start)244 void __init init_arch(bp_tag_t *bp_start)
245 {
246 /* Initialize basic exception handling if configuration may need it */
247
248 if (IS_ENABLED(CONFIG_KASAN) ||
249 IS_ENABLED(CONFIG_XTENSA_LOAD_STORE))
250 early_trap_init();
251
252 /* Initialize MMU. */
253
254 init_mmu();
255
256 /* Initialize initial KASAN shadow map */
257
258 kasan_early_init();
259
260 /* Parse boot parameters */
261
262 if (bp_start)
263 parse_bootparam(bp_start);
264
265 #ifdef CONFIG_USE_OF
266 early_init_devtree(dtb_start);
267 #endif
268
269 #ifdef CONFIG_CMDLINE_BOOL
270 if (!command_line[0])
271 strscpy(command_line, default_command_line, COMMAND_LINE_SIZE);
272 #endif
273
274 /* Early hook for platforms */
275
276 platform_init(bp_start);
277 }
278
279 /*
280 * Initialize system. Setup memory and reserve regions.
281 */
282
mem_reserve(unsigned long start,unsigned long end)283 static inline int __init_memblock mem_reserve(unsigned long start,
284 unsigned long end)
285 {
286 return memblock_reserve(start, end - start);
287 }
288
setup_arch(char ** cmdline_p)289 void __init setup_arch(char **cmdline_p)
290 {
291 pr_info("config ID: %08x:%08x\n",
292 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE));
293 if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 ||
294 xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1)
295 pr_info("built for config ID: %08x:%08x\n",
296 XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1);
297
298 *cmdline_p = command_line;
299 platform_setup(cmdline_p);
300 strscpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
301
302 /* Reserve some memory regions */
303
304 #ifdef CONFIG_BLK_DEV_INITRD
305 if (initrd_start < initrd_end &&
306 !mem_reserve(__pa(initrd_start), __pa(initrd_end)))
307 initrd_below_start_ok = 1;
308 else
309 initrd_start = 0;
310 #endif
311
312 mem_reserve(__pa(_stext), __pa(_end));
313 #ifdef CONFIG_XIP_KERNEL
314 #ifdef CONFIG_VECTORS_ADDR
315 mem_reserve(__pa(_xip_text_start), __pa(_xip_text_end));
316 #endif
317 mem_reserve(__pa(_xip_start), __pa(_xip_end));
318 #endif
319
320 #ifdef CONFIG_VECTORS_ADDR
321 #ifdef SUPPORT_WINDOWED
322 mem_reserve(__pa(_WindowVectors_text_start),
323 __pa(_WindowVectors_text_end));
324 #endif
325
326 mem_reserve(__pa(_DebugInterruptVector_text_start),
327 __pa(_DebugInterruptVector_text_end));
328
329 mem_reserve(__pa(_KernelExceptionVector_text_start),
330 __pa(_KernelExceptionVector_text_end));
331
332 mem_reserve(__pa(_UserExceptionVector_text_start),
333 __pa(_UserExceptionVector_text_end));
334
335 mem_reserve(__pa(_DoubleExceptionVector_text_start),
336 __pa(_DoubleExceptionVector_text_end));
337
338 mem_reserve(__pa(_exception_text_start),
339 __pa(_exception_text_end));
340 #if XCHAL_EXCM_LEVEL >= 2
341 mem_reserve(__pa(_Level2InterruptVector_text_start),
342 __pa(_Level2InterruptVector_text_end));
343 #endif
344 #if XCHAL_EXCM_LEVEL >= 3
345 mem_reserve(__pa(_Level3InterruptVector_text_start),
346 __pa(_Level3InterruptVector_text_end));
347 #endif
348 #if XCHAL_EXCM_LEVEL >= 4
349 mem_reserve(__pa(_Level4InterruptVector_text_start),
350 __pa(_Level4InterruptVector_text_end));
351 #endif
352 #if XCHAL_EXCM_LEVEL >= 5
353 mem_reserve(__pa(_Level5InterruptVector_text_start),
354 __pa(_Level5InterruptVector_text_end));
355 #endif
356 #if XCHAL_EXCM_LEVEL >= 6
357 mem_reserve(__pa(_Level6InterruptVector_text_start),
358 __pa(_Level6InterruptVector_text_end));
359 #endif
360
361 #endif /* CONFIG_VECTORS_ADDR */
362
363 #ifdef CONFIG_SECONDARY_RESET_VECTOR
364 mem_reserve(__pa(_SecondaryResetVector_text_start),
365 __pa(_SecondaryResetVector_text_end));
366 #endif
367 parse_early_param();
368 bootmem_init();
369 kasan_init();
370 unflatten_and_copy_device_tree();
371
372 #ifdef CONFIG_SMP
373 smp_init_cpus();
374 #endif
375
376 paging_init();
377 zones_init();
378
379 #ifdef CONFIG_VT
380 # if defined(CONFIG_VGA_CONSOLE)
381 conswitchp = &vga_con;
382 # endif
383 #endif
384 }
385
386 static DEFINE_PER_CPU(struct cpu, cpu_data);
387
topology_init(void)388 static int __init topology_init(void)
389 {
390 int i;
391
392 for_each_possible_cpu(i) {
393 struct cpu *cpu = &per_cpu(cpu_data, i);
394 cpu->hotpluggable = !!i;
395 register_cpu(cpu, i);
396 }
397
398 return 0;
399 }
400 subsys_initcall(topology_init);
401
cpu_reset(void)402 void cpu_reset(void)
403 {
404 #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
405 local_irq_disable();
406 /*
407 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
408 * be flushed.
409 * Way 4 is not currently used by linux.
410 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
411 * Way 5 shall be flushed and way 6 shall be set to identity mapping
412 * on MMUv3.
413 */
414 local_flush_tlb_all();
415 invalidate_page_directory();
416 #if XCHAL_HAVE_SPANNING_WAY
417 /* MMU v3 */
418 {
419 unsigned long vaddr = (unsigned long)cpu_reset;
420 unsigned long paddr = __pa(vaddr);
421 unsigned long tmpaddr = vaddr + SZ_512M;
422 unsigned long tmp0, tmp1, tmp2, tmp3;
423
424 /*
425 * Find a place for the temporary mapping. It must not be
426 * in the same 512MB region with vaddr or paddr, otherwise
427 * there may be multihit exception either on entry to the
428 * temporary mapping, or on entry to the identity mapping.
429 * (512MB is the biggest page size supported by TLB.)
430 */
431 while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
432 tmpaddr += SZ_512M;
433
434 /* Invalidate mapping in the selected temporary area */
435 if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
436 invalidate_itlb_entry(itlb_probe(tmpaddr));
437 if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
438 invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
439
440 /*
441 * Map two consecutive pages starting at the physical address
442 * of this function to the temporary mapping area.
443 */
444 write_itlb_entry(__pte((paddr & PAGE_MASK) |
445 _PAGE_HW_VALID |
446 _PAGE_HW_EXEC |
447 _PAGE_CA_BYPASS),
448 tmpaddr & PAGE_MASK);
449 write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
450 _PAGE_HW_VALID |
451 _PAGE_HW_EXEC |
452 _PAGE_CA_BYPASS),
453 (tmpaddr & PAGE_MASK) + PAGE_SIZE);
454
455 /* Reinitialize TLB */
456 __asm__ __volatile__ ("movi %0, 1f\n\t"
457 "movi %3, 2f\n\t"
458 "add %0, %0, %4\n\t"
459 "add %3, %3, %5\n\t"
460 "jx %0\n"
461 /*
462 * No literal, data or stack access
463 * below this point
464 */
465 "1:\n\t"
466 /* Initialize *tlbcfg */
467 "movi %0, 0\n\t"
468 "wsr %0, itlbcfg\n\t"
469 "wsr %0, dtlbcfg\n\t"
470 /* Invalidate TLB way 5 */
471 "movi %0, 4\n\t"
472 "movi %1, 5\n"
473 "1:\n\t"
474 "iitlb %1\n\t"
475 "idtlb %1\n\t"
476 "add %1, %1, %6\n\t"
477 "addi %0, %0, -1\n\t"
478 "bnez %0, 1b\n\t"
479 /* Initialize TLB way 6 */
480 "movi %0, 7\n\t"
481 "addi %1, %9, 3\n\t"
482 "addi %2, %9, 6\n"
483 "1:\n\t"
484 "witlb %1, %2\n\t"
485 "wdtlb %1, %2\n\t"
486 "add %1, %1, %7\n\t"
487 "add %2, %2, %7\n\t"
488 "addi %0, %0, -1\n\t"
489 "bnez %0, 1b\n\t"
490 "isync\n\t"
491 /* Jump to identity mapping */
492 "jx %3\n"
493 "2:\n\t"
494 /* Complete way 6 initialization */
495 "witlb %1, %2\n\t"
496 "wdtlb %1, %2\n\t"
497 /* Invalidate temporary mapping */
498 "sub %0, %9, %7\n\t"
499 "iitlb %0\n\t"
500 "add %0, %0, %8\n\t"
501 "iitlb %0"
502 : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
503 "=&a"(tmp3)
504 : "a"(tmpaddr - vaddr),
505 "a"(paddr - vaddr),
506 "a"(SZ_128M), "a"(SZ_512M),
507 "a"(PAGE_SIZE),
508 "a"((tmpaddr + SZ_512M) & PAGE_MASK)
509 : "memory");
510 }
511 #endif
512 #endif
513 __asm__ __volatile__ ("movi a2, 0\n\t"
514 "wsr a2, icountlevel\n\t"
515 "movi a2, 0\n\t"
516 "wsr a2, icount\n\t"
517 #if XCHAL_NUM_IBREAK > 0
518 "wsr a2, ibreakenable\n\t"
519 #endif
520 #if XCHAL_HAVE_LOOPS
521 "wsr a2, lcount\n\t"
522 #endif
523 "movi a2, 0x1f\n\t"
524 "wsr a2, ps\n\t"
525 "isync\n\t"
526 "jx %0\n\t"
527 :
528 : "a" (XCHAL_RESET_VECTOR_VADDR)
529 : "a2");
530 for (;;)
531 ;
532 }
533
machine_restart(char * cmd)534 void machine_restart(char * cmd)
535 {
536 local_irq_disable();
537 smp_send_stop();
538 do_kernel_restart(cmd);
539 pr_err("Reboot failed -- System halted\n");
540 while (1)
541 cpu_relax();
542 }
543
machine_halt(void)544 void machine_halt(void)
545 {
546 local_irq_disable();
547 smp_send_stop();
548 do_kernel_power_off();
549 while (1)
550 cpu_relax();
551 }
552
machine_power_off(void)553 void machine_power_off(void)
554 {
555 local_irq_disable();
556 smp_send_stop();
557 do_kernel_power_off();
558 while (1)
559 cpu_relax();
560 }
561 #ifdef CONFIG_PROC_FS
562
563 /*
564 * Display some core information through /proc/cpuinfo.
565 */
566
567 static int
c_show(struct seq_file * f,void * slot)568 c_show(struct seq_file *f, void *slot)
569 {
570 /* high-level stuff */
571 seq_printf(f, "CPU count\t: %u\n"
572 "CPU list\t: %*pbl\n"
573 "vendor_id\t: Tensilica\n"
574 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
575 "core ID\t\t: " XCHAL_CORE_ID "\n"
576 "build ID\t: 0x%x\n"
577 "config ID\t: %08x:%08x\n"
578 "byte order\t: %s\n"
579 "cpu MHz\t\t: %lu.%02lu\n"
580 "bogomips\t: %lu.%02lu\n",
581 num_online_cpus(),
582 cpumask_pr_args(cpu_online_mask),
583 XCHAL_BUILD_UNIQUE_ID,
584 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE),
585 XCHAL_HAVE_BE ? "big" : "little",
586 ccount_freq/1000000,
587 (ccount_freq/10000) % 100,
588 loops_per_jiffy/(500000/HZ),
589 (loops_per_jiffy/(5000/HZ)) % 100);
590 seq_puts(f, "flags\t\t: "
591 #if XCHAL_HAVE_NMI
592 "nmi "
593 #endif
594 #if XCHAL_HAVE_DEBUG
595 "debug "
596 # if XCHAL_HAVE_OCD
597 "ocd "
598 # endif
599 #if XCHAL_HAVE_TRAX
600 "trax "
601 #endif
602 #if XCHAL_NUM_PERF_COUNTERS
603 "perf "
604 #endif
605 #endif
606 #if XCHAL_HAVE_DENSITY
607 "density "
608 #endif
609 #if XCHAL_HAVE_BOOLEANS
610 "boolean "
611 #endif
612 #if XCHAL_HAVE_LOOPS
613 "loop "
614 #endif
615 #if XCHAL_HAVE_NSA
616 "nsa "
617 #endif
618 #if XCHAL_HAVE_MINMAX
619 "minmax "
620 #endif
621 #if XCHAL_HAVE_SEXT
622 "sext "
623 #endif
624 #if XCHAL_HAVE_CLAMPS
625 "clamps "
626 #endif
627 #if XCHAL_HAVE_MAC16
628 "mac16 "
629 #endif
630 #if XCHAL_HAVE_MUL16
631 "mul16 "
632 #endif
633 #if XCHAL_HAVE_MUL32
634 "mul32 "
635 #endif
636 #if XCHAL_HAVE_MUL32_HIGH
637 "mul32h "
638 #endif
639 #if XCHAL_HAVE_FP
640 "fpu "
641 #endif
642 #if XCHAL_HAVE_S32C1I
643 "s32c1i "
644 #endif
645 #if XCHAL_HAVE_EXCLUSIVE
646 "exclusive "
647 #endif
648 "\n");
649
650 /* Registers. */
651 seq_printf(f,"physical aregs\t: %d\n"
652 "misc regs\t: %d\n"
653 "ibreak\t\t: %d\n"
654 "dbreak\t\t: %d\n"
655 "perf counters\t: %d\n",
656 XCHAL_NUM_AREGS,
657 XCHAL_NUM_MISC_REGS,
658 XCHAL_NUM_IBREAK,
659 XCHAL_NUM_DBREAK,
660 XCHAL_NUM_PERF_COUNTERS);
661
662
663 /* Interrupt. */
664 seq_printf(f,"num ints\t: %d\n"
665 "ext ints\t: %d\n"
666 "int levels\t: %d\n"
667 "timers\t\t: %d\n"
668 "debug level\t: %d\n",
669 XCHAL_NUM_INTERRUPTS,
670 XCHAL_NUM_EXTINTERRUPTS,
671 XCHAL_NUM_INTLEVELS,
672 XCHAL_NUM_TIMERS,
673 XCHAL_DEBUGLEVEL);
674
675 /* Cache */
676 seq_printf(f,"icache line size: %d\n"
677 "icache ways\t: %d\n"
678 "icache size\t: %d\n"
679 "icache flags\t: "
680 #if XCHAL_ICACHE_LINE_LOCKABLE
681 "lock "
682 #endif
683 "\n"
684 "dcache line size: %d\n"
685 "dcache ways\t: %d\n"
686 "dcache size\t: %d\n"
687 "dcache flags\t: "
688 #if XCHAL_DCACHE_IS_WRITEBACK
689 "writeback "
690 #endif
691 #if XCHAL_DCACHE_LINE_LOCKABLE
692 "lock "
693 #endif
694 "\n",
695 XCHAL_ICACHE_LINESIZE,
696 XCHAL_ICACHE_WAYS,
697 XCHAL_ICACHE_SIZE,
698 XCHAL_DCACHE_LINESIZE,
699 XCHAL_DCACHE_WAYS,
700 XCHAL_DCACHE_SIZE);
701
702 return 0;
703 }
704
705 /*
706 * We show only CPU #0 info.
707 */
708 static void *
c_start(struct seq_file * f,loff_t * pos)709 c_start(struct seq_file *f, loff_t *pos)
710 {
711 return (*pos == 0) ? (void *)1 : NULL;
712 }
713
714 static void *
c_next(struct seq_file * f,void * v,loff_t * pos)715 c_next(struct seq_file *f, void *v, loff_t *pos)
716 {
717 ++*pos;
718 return c_start(f, pos);
719 }
720
721 static void
c_stop(struct seq_file * f,void * v)722 c_stop(struct seq_file *f, void *v)
723 {
724 }
725
726 const struct seq_operations cpuinfo_op =
727 {
728 .start = c_start,
729 .next = c_next,
730 .stop = c_stop,
731 .show = c_show,
732 };
733
734 #endif /* CONFIG_PROC_FS */
735
