1 /*
2 * arch/xtensa/kernel/setup.c
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995 Linus Torvalds
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
10 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
11 *
12 * Chris Zankel <chris@zankel.net>
13 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
14 * Kevin Chea
15 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
16 */
17
18 #include <linux/errno.h>
19 #include <linux/init.h>
20 #include <linux/mm.h>
21 #include <linux/proc_fs.h>
22 #include <linux/screen_info.h>
23 #include <linux/kernel.h>
24 #include <linux/percpu.h>
25 #include <linux/cpu.h>
26 #include <linux/of.h>
27 #include <linux/of_fdt.h>
28
29 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
30 # include <linux/console.h>
31 #endif
32
33 #ifdef CONFIG_PROC_FS
34 # include <linux/seq_file.h>
35 #endif
36
37 #include <asm/bootparam.h>
38 #include <asm/kasan.h>
39 #include <asm/mmu_context.h>
40 #include <asm/processor.h>
41 #include <asm/timex.h>
42 #include <asm/platform.h>
43 #include <asm/page.h>
44 #include <asm/setup.h>
45 #include <asm/param.h>
46 #include <asm/smp.h>
47 #include <asm/sysmem.h>
48
49 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
50 struct screen_info screen_info = {
51 .orig_x = 0,
52 .orig_y = 24,
53 .orig_video_cols = 80,
54 .orig_video_lines = 24,
55 .orig_video_isVGA = 1,
56 .orig_video_points = 16,
57 };
58 #endif
59
60 #ifdef CONFIG_BLK_DEV_INITRD
61 extern unsigned long initrd_start;
62 extern unsigned long initrd_end;
63 extern int initrd_below_start_ok;
64 #endif
65
66 #ifdef CONFIG_OF
67 void *dtb_start = __dtb_start;
68 #endif
69
70 extern unsigned long loops_per_jiffy;
71
72 /* Command line specified as configuration option. */
73
74 static char __initdata command_line[COMMAND_LINE_SIZE];
75
76 #ifdef CONFIG_CMDLINE_BOOL
77 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
78 #endif
79
80 #ifdef CONFIG_PARSE_BOOTPARAM
81 /*
82 * Boot parameter parsing.
83 *
84 * The Xtensa port uses a list of variable-sized tags to pass data to
85 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
86 * to be recognised. The list is terminated with a zero-sized
87 * BP_TAG_LAST tag.
88 */
89
90 typedef struct tagtable {
91 u32 tag;
92 int (*parse)(const bp_tag_t*);
93 } tagtable_t;
94
95 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
96 __section(".taglist") __attribute__((used)) = { tag, fn }
97
98 /* parse current tag */
99
parse_tag_mem(const bp_tag_t * tag)100 static int __init parse_tag_mem(const bp_tag_t *tag)
101 {
102 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
103
104 if (mi->type != MEMORY_TYPE_CONVENTIONAL)
105 return -1;
106
107 return memblock_add(mi->start, mi->end - mi->start);
108 }
109
110 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
111
112 #ifdef CONFIG_BLK_DEV_INITRD
113
parse_tag_initrd(const bp_tag_t * tag)114 static int __init parse_tag_initrd(const bp_tag_t* tag)
115 {
116 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
117
118 initrd_start = (unsigned long)__va(mi->start);
119 initrd_end = (unsigned long)__va(mi->end);
120
121 return 0;
122 }
123
124 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
125
126 #endif /* CONFIG_BLK_DEV_INITRD */
127
128 #ifdef CONFIG_OF
129
parse_tag_fdt(const bp_tag_t * tag)130 static int __init parse_tag_fdt(const bp_tag_t *tag)
131 {
132 dtb_start = __va(tag->data[0]);
133 return 0;
134 }
135
136 __tagtable(BP_TAG_FDT, parse_tag_fdt);
137
138 #endif /* CONFIG_OF */
139
parse_tag_cmdline(const bp_tag_t * tag)140 static int __init parse_tag_cmdline(const bp_tag_t* tag)
141 {
142 strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
143 return 0;
144 }
145
146 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
147
parse_bootparam(const bp_tag_t * tag)148 static int __init parse_bootparam(const bp_tag_t* tag)
149 {
150 extern tagtable_t __tagtable_begin, __tagtable_end;
151 tagtable_t *t;
152
153 /* Boot parameters must start with a BP_TAG_FIRST tag. */
154
155 if (tag->id != BP_TAG_FIRST) {
156 pr_warn("Invalid boot parameters!\n");
157 return 0;
158 }
159
160 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
161
162 /* Parse all tags. */
163
164 while (tag != NULL && tag->id != BP_TAG_LAST) {
165 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
166 if (tag->id == t->tag) {
167 t->parse(tag);
168 break;
169 }
170 }
171 if (t == &__tagtable_end)
172 pr_warn("Ignoring tag 0x%08x\n", tag->id);
173 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
174 }
175
176 return 0;
177 }
178 #else
parse_bootparam(const bp_tag_t * tag)179 static int __init parse_bootparam(const bp_tag_t *tag)
180 {
181 pr_info("Ignoring boot parameters at %p\n", tag);
182 return 0;
183 }
184 #endif
185
186 #ifdef CONFIG_OF
187
188 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
189 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
190 EXPORT_SYMBOL(xtensa_kio_paddr);
191
xtensa_dt_io_area(unsigned long node,const char * uname,int depth,void * data)192 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
193 int depth, void *data)
194 {
195 const __be32 *ranges;
196 int len;
197
198 if (depth > 1)
199 return 0;
200
201 if (!of_flat_dt_is_compatible(node, "simple-bus"))
202 return 0;
203
204 ranges = of_get_flat_dt_prop(node, "ranges", &len);
205 if (!ranges)
206 return 1;
207 if (len == 0)
208 return 1;
209
210 xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
211 /* round down to nearest 256MB boundary */
212 xtensa_kio_paddr &= 0xf0000000;
213
214 init_kio();
215
216 return 1;
217 }
218 #else
xtensa_dt_io_area(unsigned long node,const char * uname,int depth,void * data)219 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
220 int depth, void *data)
221 {
222 return 1;
223 }
224 #endif
225
early_init_devtree(void * params)226 void __init early_init_devtree(void *params)
227 {
228 early_init_dt_scan(params);
229 of_scan_flat_dt(xtensa_dt_io_area, NULL);
230
231 if (!command_line[0])
232 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
233 }
234
235 #endif /* CONFIG_OF */
236
237 /*
238 * Initialize architecture. (Early stage)
239 */
240
init_arch(bp_tag_t * bp_start)241 void __init init_arch(bp_tag_t *bp_start)
242 {
243 /* Initialize MMU. */
244
245 init_mmu();
246
247 /* Initialize initial KASAN shadow map */
248
249 kasan_early_init();
250
251 /* Parse boot parameters */
252
253 if (bp_start)
254 parse_bootparam(bp_start);
255
256 #ifdef CONFIG_OF
257 early_init_devtree(dtb_start);
258 #endif
259
260 #ifdef CONFIG_CMDLINE_BOOL
261 if (!command_line[0])
262 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
263 #endif
264
265 /* Early hook for platforms */
266
267 platform_init(bp_start);
268 }
269
270 /*
271 * Initialize system. Setup memory and reserve regions.
272 */
273
274 extern char _end[];
275 extern char _stext[];
276 extern char _WindowVectors_text_start;
277 extern char _WindowVectors_text_end;
278 extern char _DebugInterruptVector_text_start;
279 extern char _DebugInterruptVector_text_end;
280 extern char _KernelExceptionVector_text_start;
281 extern char _KernelExceptionVector_text_end;
282 extern char _UserExceptionVector_text_start;
283 extern char _UserExceptionVector_text_end;
284 extern char _DoubleExceptionVector_text_start;
285 extern char _DoubleExceptionVector_text_end;
286 extern char _exception_text_start;
287 extern char _exception_text_end;
288 #if XCHAL_EXCM_LEVEL >= 2
289 extern char _Level2InterruptVector_text_start;
290 extern char _Level2InterruptVector_text_end;
291 #endif
292 #if XCHAL_EXCM_LEVEL >= 3
293 extern char _Level3InterruptVector_text_start;
294 extern char _Level3InterruptVector_text_end;
295 #endif
296 #if XCHAL_EXCM_LEVEL >= 4
297 extern char _Level4InterruptVector_text_start;
298 extern char _Level4InterruptVector_text_end;
299 #endif
300 #if XCHAL_EXCM_LEVEL >= 5
301 extern char _Level5InterruptVector_text_start;
302 extern char _Level5InterruptVector_text_end;
303 #endif
304 #if XCHAL_EXCM_LEVEL >= 6
305 extern char _Level6InterruptVector_text_start;
306 extern char _Level6InterruptVector_text_end;
307 #endif
308 #ifdef CONFIG_SMP
309 extern char _SecondaryResetVector_text_start;
310 extern char _SecondaryResetVector_text_end;
311 #endif
312 #ifdef CONFIG_XIP_KERNEL
313 extern char _xip_start[];
314 extern char _xip_end[];
315 #endif
316
mem_reserve(unsigned long start,unsigned long end)317 static inline int __init_memblock mem_reserve(unsigned long start,
318 unsigned long end)
319 {
320 return memblock_reserve(start, end - start);
321 }
322
setup_arch(char ** cmdline_p)323 void __init setup_arch(char **cmdline_p)
324 {
325 pr_info("config ID: %08x:%08x\n",
326 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE));
327 if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 ||
328 xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1)
329 pr_info("built for config ID: %08x:%08x\n",
330 XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1);
331
332 *cmdline_p = command_line;
333 platform_setup(cmdline_p);
334 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
335
336 /* Reserve some memory regions */
337
338 #ifdef CONFIG_BLK_DEV_INITRD
339 if (initrd_start < initrd_end &&
340 !mem_reserve(__pa(initrd_start), __pa(initrd_end)))
341 initrd_below_start_ok = 1;
342 else
343 initrd_start = 0;
344 #endif
345
346 mem_reserve(__pa(_stext), __pa(_end));
347 #ifdef CONFIG_XIP_KERNEL
348 mem_reserve(__pa(_xip_start), __pa(_xip_end));
349 #endif
350
351 #ifdef CONFIG_VECTORS_ADDR
352 mem_reserve(__pa(&_WindowVectors_text_start),
353 __pa(&_WindowVectors_text_end));
354
355 mem_reserve(__pa(&_DebugInterruptVector_text_start),
356 __pa(&_DebugInterruptVector_text_end));
357
358 mem_reserve(__pa(&_KernelExceptionVector_text_start),
359 __pa(&_KernelExceptionVector_text_end));
360
361 mem_reserve(__pa(&_UserExceptionVector_text_start),
362 __pa(&_UserExceptionVector_text_end));
363
364 mem_reserve(__pa(&_DoubleExceptionVector_text_start),
365 __pa(&_DoubleExceptionVector_text_end));
366
367 mem_reserve(__pa(&_exception_text_start),
368 __pa(&_exception_text_end));
369 #if XCHAL_EXCM_LEVEL >= 2
370 mem_reserve(__pa(&_Level2InterruptVector_text_start),
371 __pa(&_Level2InterruptVector_text_end));
372 #endif
373 #if XCHAL_EXCM_LEVEL >= 3
374 mem_reserve(__pa(&_Level3InterruptVector_text_start),
375 __pa(&_Level3InterruptVector_text_end));
376 #endif
377 #if XCHAL_EXCM_LEVEL >= 4
378 mem_reserve(__pa(&_Level4InterruptVector_text_start),
379 __pa(&_Level4InterruptVector_text_end));
380 #endif
381 #if XCHAL_EXCM_LEVEL >= 5
382 mem_reserve(__pa(&_Level5InterruptVector_text_start),
383 __pa(&_Level5InterruptVector_text_end));
384 #endif
385 #if XCHAL_EXCM_LEVEL >= 6
386 mem_reserve(__pa(&_Level6InterruptVector_text_start),
387 __pa(&_Level6InterruptVector_text_end));
388 #endif
389
390 #endif /* CONFIG_VECTORS_ADDR */
391
392 #ifdef CONFIG_SMP
393 mem_reserve(__pa(&_SecondaryResetVector_text_start),
394 __pa(&_SecondaryResetVector_text_end));
395 #endif
396 parse_early_param();
397 bootmem_init();
398 kasan_init();
399 unflatten_and_copy_device_tree();
400
401 #ifdef CONFIG_SMP
402 smp_init_cpus();
403 #endif
404
405 paging_init();
406 zones_init();
407
408 #ifdef CONFIG_VT
409 # if defined(CONFIG_VGA_CONSOLE)
410 conswitchp = &vga_con;
411 # endif
412 #endif
413 }
414
415 static DEFINE_PER_CPU(struct cpu, cpu_data);
416
topology_init(void)417 static int __init topology_init(void)
418 {
419 int i;
420
421 for_each_possible_cpu(i) {
422 struct cpu *cpu = &per_cpu(cpu_data, i);
423 cpu->hotpluggable = !!i;
424 register_cpu(cpu, i);
425 }
426
427 return 0;
428 }
429 subsys_initcall(topology_init);
430
cpu_reset(void)431 void cpu_reset(void)
432 {
433 #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
434 local_irq_disable();
435 /*
436 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
437 * be flushed.
438 * Way 4 is not currently used by linux.
439 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
440 * Way 5 shall be flushed and way 6 shall be set to identity mapping
441 * on MMUv3.
442 */
443 local_flush_tlb_all();
444 invalidate_page_directory();
445 #if XCHAL_HAVE_SPANNING_WAY
446 /* MMU v3 */
447 {
448 unsigned long vaddr = (unsigned long)cpu_reset;
449 unsigned long paddr = __pa(vaddr);
450 unsigned long tmpaddr = vaddr + SZ_512M;
451 unsigned long tmp0, tmp1, tmp2, tmp3;
452
453 /*
454 * Find a place for the temporary mapping. It must not be
455 * in the same 512MB region with vaddr or paddr, otherwise
456 * there may be multihit exception either on entry to the
457 * temporary mapping, or on entry to the identity mapping.
458 * (512MB is the biggest page size supported by TLB.)
459 */
460 while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
461 tmpaddr += SZ_512M;
462
463 /* Invalidate mapping in the selected temporary area */
464 if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
465 invalidate_itlb_entry(itlb_probe(tmpaddr));
466 if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
467 invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
468
469 /*
470 * Map two consecutive pages starting at the physical address
471 * of this function to the temporary mapping area.
472 */
473 write_itlb_entry(__pte((paddr & PAGE_MASK) |
474 _PAGE_HW_VALID |
475 _PAGE_HW_EXEC |
476 _PAGE_CA_BYPASS),
477 tmpaddr & PAGE_MASK);
478 write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
479 _PAGE_HW_VALID |
480 _PAGE_HW_EXEC |
481 _PAGE_CA_BYPASS),
482 (tmpaddr & PAGE_MASK) + PAGE_SIZE);
483
484 /* Reinitialize TLB */
485 __asm__ __volatile__ ("movi %0, 1f\n\t"
486 "movi %3, 2f\n\t"
487 "add %0, %0, %4\n\t"
488 "add %3, %3, %5\n\t"
489 "jx %0\n"
490 /*
491 * No literal, data or stack access
492 * below this point
493 */
494 "1:\n\t"
495 /* Initialize *tlbcfg */
496 "movi %0, 0\n\t"
497 "wsr %0, itlbcfg\n\t"
498 "wsr %0, dtlbcfg\n\t"
499 /* Invalidate TLB way 5 */
500 "movi %0, 4\n\t"
501 "movi %1, 5\n"
502 "1:\n\t"
503 "iitlb %1\n\t"
504 "idtlb %1\n\t"
505 "add %1, %1, %6\n\t"
506 "addi %0, %0, -1\n\t"
507 "bnez %0, 1b\n\t"
508 /* Initialize TLB way 6 */
509 "movi %0, 7\n\t"
510 "addi %1, %9, 3\n\t"
511 "addi %2, %9, 6\n"
512 "1:\n\t"
513 "witlb %1, %2\n\t"
514 "wdtlb %1, %2\n\t"
515 "add %1, %1, %7\n\t"
516 "add %2, %2, %7\n\t"
517 "addi %0, %0, -1\n\t"
518 "bnez %0, 1b\n\t"
519 "isync\n\t"
520 /* Jump to identity mapping */
521 "jx %3\n"
522 "2:\n\t"
523 /* Complete way 6 initialization */
524 "witlb %1, %2\n\t"
525 "wdtlb %1, %2\n\t"
526 /* Invalidate temporary mapping */
527 "sub %0, %9, %7\n\t"
528 "iitlb %0\n\t"
529 "add %0, %0, %8\n\t"
530 "iitlb %0"
531 : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
532 "=&a"(tmp3)
533 : "a"(tmpaddr - vaddr),
534 "a"(paddr - vaddr),
535 "a"(SZ_128M), "a"(SZ_512M),
536 "a"(PAGE_SIZE),
537 "a"((tmpaddr + SZ_512M) & PAGE_MASK)
538 : "memory");
539 }
540 #endif
541 #endif
542 __asm__ __volatile__ ("movi a2, 0\n\t"
543 "wsr a2, icountlevel\n\t"
544 "movi a2, 0\n\t"
545 "wsr a2, icount\n\t"
546 #if XCHAL_NUM_IBREAK > 0
547 "wsr a2, ibreakenable\n\t"
548 #endif
549 #if XCHAL_HAVE_LOOPS
550 "wsr a2, lcount\n\t"
551 #endif
552 "movi a2, 0x1f\n\t"
553 "wsr a2, ps\n\t"
554 "isync\n\t"
555 "jx %0\n\t"
556 :
557 : "a" (XCHAL_RESET_VECTOR_VADDR)
558 : "a2");
559 for (;;)
560 ;
561 }
562
machine_restart(char * cmd)563 void machine_restart(char * cmd)
564 {
565 platform_restart();
566 }
567
machine_halt(void)568 void machine_halt(void)
569 {
570 platform_halt();
571 while (1);
572 }
573
machine_power_off(void)574 void machine_power_off(void)
575 {
576 platform_power_off();
577 while (1);
578 }
579 #ifdef CONFIG_PROC_FS
580
581 /*
582 * Display some core information through /proc/cpuinfo.
583 */
584
585 static int
c_show(struct seq_file * f,void * slot)586 c_show(struct seq_file *f, void *slot)
587 {
588 /* high-level stuff */
589 seq_printf(f, "CPU count\t: %u\n"
590 "CPU list\t: %*pbl\n"
591 "vendor_id\t: Tensilica\n"
592 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
593 "core ID\t\t: " XCHAL_CORE_ID "\n"
594 "build ID\t: 0x%x\n"
595 "config ID\t: %08x:%08x\n"
596 "byte order\t: %s\n"
597 "cpu MHz\t\t: %lu.%02lu\n"
598 "bogomips\t: %lu.%02lu\n",
599 num_online_cpus(),
600 cpumask_pr_args(cpu_online_mask),
601 XCHAL_BUILD_UNIQUE_ID,
602 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE),
603 XCHAL_HAVE_BE ? "big" : "little",
604 ccount_freq/1000000,
605 (ccount_freq/10000) % 100,
606 loops_per_jiffy/(500000/HZ),
607 (loops_per_jiffy/(5000/HZ)) % 100);
608 seq_puts(f, "flags\t\t: "
609 #if XCHAL_HAVE_NMI
610 "nmi "
611 #endif
612 #if XCHAL_HAVE_DEBUG
613 "debug "
614 # if XCHAL_HAVE_OCD
615 "ocd "
616 # endif
617 #endif
618 #if XCHAL_HAVE_DENSITY
619 "density "
620 #endif
621 #if XCHAL_HAVE_BOOLEANS
622 "boolean "
623 #endif
624 #if XCHAL_HAVE_LOOPS
625 "loop "
626 #endif
627 #if XCHAL_HAVE_NSA
628 "nsa "
629 #endif
630 #if XCHAL_HAVE_MINMAX
631 "minmax "
632 #endif
633 #if XCHAL_HAVE_SEXT
634 "sext "
635 #endif
636 #if XCHAL_HAVE_CLAMPS
637 "clamps "
638 #endif
639 #if XCHAL_HAVE_MAC16
640 "mac16 "
641 #endif
642 #if XCHAL_HAVE_MUL16
643 "mul16 "
644 #endif
645 #if XCHAL_HAVE_MUL32
646 "mul32 "
647 #endif
648 #if XCHAL_HAVE_MUL32_HIGH
649 "mul32h "
650 #endif
651 #if XCHAL_HAVE_FP
652 "fpu "
653 #endif
654 #if XCHAL_HAVE_S32C1I
655 "s32c1i "
656 #endif
657 #if XCHAL_HAVE_EXCLUSIVE
658 "exclusive "
659 #endif
660 "\n");
661
662 /* Registers. */
663 seq_printf(f,"physical aregs\t: %d\n"
664 "misc regs\t: %d\n"
665 "ibreak\t\t: %d\n"
666 "dbreak\t\t: %d\n",
667 XCHAL_NUM_AREGS,
668 XCHAL_NUM_MISC_REGS,
669 XCHAL_NUM_IBREAK,
670 XCHAL_NUM_DBREAK);
671
672
673 /* Interrupt. */
674 seq_printf(f,"num ints\t: %d\n"
675 "ext ints\t: %d\n"
676 "int levels\t: %d\n"
677 "timers\t\t: %d\n"
678 "debug level\t: %d\n",
679 XCHAL_NUM_INTERRUPTS,
680 XCHAL_NUM_EXTINTERRUPTS,
681 XCHAL_NUM_INTLEVELS,
682 XCHAL_NUM_TIMERS,
683 XCHAL_DEBUGLEVEL);
684
685 /* Cache */
686 seq_printf(f,"icache line size: %d\n"
687 "icache ways\t: %d\n"
688 "icache size\t: %d\n"
689 "icache flags\t: "
690 #if XCHAL_ICACHE_LINE_LOCKABLE
691 "lock "
692 #endif
693 "\n"
694 "dcache line size: %d\n"
695 "dcache ways\t: %d\n"
696 "dcache size\t: %d\n"
697 "dcache flags\t: "
698 #if XCHAL_DCACHE_IS_WRITEBACK
699 "writeback "
700 #endif
701 #if XCHAL_DCACHE_LINE_LOCKABLE
702 "lock "
703 #endif
704 "\n",
705 XCHAL_ICACHE_LINESIZE,
706 XCHAL_ICACHE_WAYS,
707 XCHAL_ICACHE_SIZE,
708 XCHAL_DCACHE_LINESIZE,
709 XCHAL_DCACHE_WAYS,
710 XCHAL_DCACHE_SIZE);
711
712 return 0;
713 }
714
715 /*
716 * We show only CPU #0 info.
717 */
718 static void *
c_start(struct seq_file * f,loff_t * pos)719 c_start(struct seq_file *f, loff_t *pos)
720 {
721 return (*pos == 0) ? (void *)1 : NULL;
722 }
723
724 static void *
c_next(struct seq_file * f,void * v,loff_t * pos)725 c_next(struct seq_file *f, void *v, loff_t *pos)
726 {
727 ++*pos;
728 return c_start(f, pos);
729 }
730
731 static void
c_stop(struct seq_file * f,void * v)732 c_stop(struct seq_file *f, void *v)
733 {
734 }
735
736 const struct seq_operations cpuinfo_op =
737 {
738 .start = c_start,
739 .next = c_next,
740 .stop = c_stop,
741 .show = c_show,
742 };
743
744 #endif /* CONFIG_PROC_FS */
745
