1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * linux/arch/xtensa/kernel/irq.c
4 *
5 * Xtensa built-in interrupt controller and some generic functions copied
6 * from i386.
7 *
8 * Copyright (C) 2002 - 2013 Tensilica, Inc.
9 * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
10 *
11 *
12 * Chris Zankel <chris@zankel.net>
13 * Kevin Chea
14 *
15 */
16
17 #include <linux/module.h>
18 #include <linux/seq_file.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/irqchip.h>
23 #include <linux/irqchip/xtensa-mx.h>
24 #include <linux/irqchip/xtensa-pic.h>
25 #include <linux/irqdomain.h>
26 #include <linux/of.h>
27
28 #include <asm/mxregs.h>
29 #include <linux/uaccess.h>
30 #include <asm/platform.h>
31
32 DECLARE_PER_CPU(unsigned long, nmi_count);
33
do_IRQ(int hwirq,struct pt_regs * regs)34 asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
35 {
36 int irq = irq_find_mapping(NULL, hwirq);
37
38 #ifdef CONFIG_DEBUG_STACKOVERFLOW
39 /* Debugging check for stack overflow: is there less than 1KB free? */
40 {
41 unsigned long sp;
42
43 __asm__ __volatile__ ("mov %0, a1\n" : "=a" (sp));
44 sp &= THREAD_SIZE - 1;
45
46 if (unlikely(sp < (sizeof(thread_info) + 1024)))
47 printk("Stack overflow in do_IRQ: %ld\n",
48 sp - sizeof(struct thread_info));
49 }
50 #endif
51 generic_handle_irq(irq);
52 }
53
arch_show_interrupts(struct seq_file * p,int prec)54 int arch_show_interrupts(struct seq_file *p, int prec)
55 {
56 unsigned cpu __maybe_unused;
57 #ifdef CONFIG_SMP
58 show_ipi_list(p, prec);
59 #endif
60 #if XTENSA_FAKE_NMI
61 seq_printf(p, "%*s:", prec, "NMI");
62 for_each_online_cpu(cpu)
63 seq_printf(p, " %10lu", per_cpu(nmi_count, cpu));
64 seq_puts(p, " Non-maskable interrupts\n");
65 #endif
66 return 0;
67 }
68
xtensa_irq_domain_xlate(const u32 * intspec,unsigned int intsize,unsigned long int_irq,unsigned long ext_irq,unsigned long * out_hwirq,unsigned int * out_type)69 int xtensa_irq_domain_xlate(const u32 *intspec, unsigned int intsize,
70 unsigned long int_irq, unsigned long ext_irq,
71 unsigned long *out_hwirq, unsigned int *out_type)
72 {
73 if (WARN_ON(intsize < 1 || intsize > 2))
74 return -EINVAL;
75 if (intsize == 2 && intspec[1] == 1) {
76 int_irq = xtensa_map_ext_irq(ext_irq);
77 if (int_irq < XCHAL_NUM_INTERRUPTS)
78 *out_hwirq = int_irq;
79 else
80 return -EINVAL;
81 } else {
82 *out_hwirq = int_irq;
83 }
84 *out_type = IRQ_TYPE_NONE;
85 return 0;
86 }
87
xtensa_irq_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)88 int xtensa_irq_map(struct irq_domain *d, unsigned int irq,
89 irq_hw_number_t hw)
90 {
91 struct irq_chip *irq_chip = d->host_data;
92 u32 mask = 1 << hw;
93
94 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) {
95 irq_set_chip_and_handler_name(irq, irq_chip,
96 handle_simple_irq, "level");
97 irq_set_status_flags(irq, IRQ_LEVEL);
98 } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) {
99 irq_set_chip_and_handler_name(irq, irq_chip,
100 handle_edge_irq, "edge");
101 irq_clear_status_flags(irq, IRQ_LEVEL);
102 } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) {
103 irq_set_chip_and_handler_name(irq, irq_chip,
104 handle_level_irq, "level");
105 irq_set_status_flags(irq, IRQ_LEVEL);
106 } else if (mask & XCHAL_INTTYPE_MASK_TIMER) {
107 irq_set_chip_and_handler_name(irq, irq_chip,
108 handle_percpu_irq, "timer");
109 irq_clear_status_flags(irq, IRQ_LEVEL);
110 #ifdef XCHAL_INTTYPE_MASK_PROFILING
111 } else if (mask & XCHAL_INTTYPE_MASK_PROFILING) {
112 irq_set_chip_and_handler_name(irq, irq_chip,
113 handle_percpu_irq, "profiling");
114 irq_set_status_flags(irq, IRQ_LEVEL);
115 #endif
116 } else {/* XCHAL_INTTYPE_MASK_WRITE_ERROR */
117 /* XCHAL_INTTYPE_MASK_NMI */
118 irq_set_chip_and_handler_name(irq, irq_chip,
119 handle_level_irq, "level");
120 irq_set_status_flags(irq, IRQ_LEVEL);
121 }
122 return 0;
123 }
124
xtensa_map_ext_irq(unsigned ext_irq)125 unsigned xtensa_map_ext_irq(unsigned ext_irq)
126 {
127 unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE |
128 XCHAL_INTTYPE_MASK_EXTERN_LEVEL;
129 unsigned i;
130
131 for (i = 0; mask; ++i, mask >>= 1) {
132 if ((mask & 1) && ext_irq-- == 0)
133 return i;
134 }
135 return XCHAL_NUM_INTERRUPTS;
136 }
137
xtensa_get_ext_irq_no(unsigned irq)138 unsigned xtensa_get_ext_irq_no(unsigned irq)
139 {
140 unsigned mask = (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
141 XCHAL_INTTYPE_MASK_EXTERN_LEVEL) &
142 ((1u << irq) - 1);
143 return hweight32(mask);
144 }
145
init_IRQ(void)146 void __init init_IRQ(void)
147 {
148 #ifdef CONFIG_OF
149 irqchip_init();
150 #else
151 #ifdef CONFIG_HAVE_SMP
152 xtensa_mx_init_legacy(NULL);
153 #else
154 xtensa_pic_init_legacy(NULL);
155 #endif
156 #endif
157
158 #ifdef CONFIG_SMP
159 ipi_init();
160 #endif
161 }
162
163 #ifdef CONFIG_HOTPLUG_CPU
164 /*
165 * The CPU has been marked offline. Migrate IRQs off this CPU. If
166 * the affinity settings do not allow other CPUs, force them onto any
167 * available CPU.
168 */
migrate_irqs(void)169 void migrate_irqs(void)
170 {
171 unsigned int i, cpu = smp_processor_id();
172
173 for_each_active_irq(i) {
174 struct irq_data *data = irq_get_irq_data(i);
175 struct cpumask *mask;
176 unsigned int newcpu;
177
178 if (irqd_is_per_cpu(data))
179 continue;
180
181 mask = irq_data_get_affinity_mask(data);
182 if (!cpumask_test_cpu(cpu, mask))
183 continue;
184
185 newcpu = cpumask_any_and(mask, cpu_online_mask);
186
187 if (newcpu >= nr_cpu_ids) {
188 pr_info_ratelimited("IRQ%u no longer affine to CPU%u\n",
189 i, cpu);
190
191 cpumask_setall(mask);
192 }
193 irq_set_affinity(i, mask);
194 }
195 }
196 #endif /* CONFIG_HOTPLUG_CPU */
197
