1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/module.h>
118 #include <linux/spinlock.h>
119 #include <linux/tcp.h>
120 #include <linux/if_vlan.h>
121 #include <linux/interrupt.h>
122 #include <net/busy_poll.h>
123 #include <linux/clk.h>
124 #include <linux/if_ether.h>
125 #include <linux/net_tstamp.h>
126 #include <linux/phy.h>
127 #include <net/vxlan.h>
128
129 #include "xgbe.h"
130 #include "xgbe-common.h"
131
132 static unsigned int ecc_sec_info_threshold = 10;
133 static unsigned int ecc_sec_warn_threshold = 10000;
134 static unsigned int ecc_sec_period = 600;
135 static unsigned int ecc_ded_threshold = 2;
136 static unsigned int ecc_ded_period = 600;
137
138 #ifdef CONFIG_AMD_XGBE_HAVE_ECC
139 /* Only expose the ECC parameters if supported */
140 module_param(ecc_sec_info_threshold, uint, 0644);
141 MODULE_PARM_DESC(ecc_sec_info_threshold,
142 " ECC corrected error informational threshold setting");
143
144 module_param(ecc_sec_warn_threshold, uint, 0644);
145 MODULE_PARM_DESC(ecc_sec_warn_threshold,
146 " ECC corrected error warning threshold setting");
147
148 module_param(ecc_sec_period, uint, 0644);
149 MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)");
150
151 module_param(ecc_ded_threshold, uint, 0644);
152 MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting");
153
154 module_param(ecc_ded_period, uint, 0644);
155 MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)");
156 #endif
157
158 static int xgbe_one_poll(struct napi_struct *, int);
159 static int xgbe_all_poll(struct napi_struct *, int);
160 static void xgbe_stop(struct xgbe_prv_data *);
161
xgbe_alloc_node(size_t size,int node)162 static void *xgbe_alloc_node(size_t size, int node)
163 {
164 void *mem;
165
166 mem = kzalloc_node(size, GFP_KERNEL, node);
167 if (!mem)
168 mem = kzalloc(size, GFP_KERNEL);
169
170 return mem;
171 }
172
xgbe_free_channels(struct xgbe_prv_data * pdata)173 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
174 {
175 unsigned int i;
176
177 for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) {
178 if (!pdata->channel[i])
179 continue;
180
181 kfree(pdata->channel[i]->rx_ring);
182 kfree(pdata->channel[i]->tx_ring);
183 kfree(pdata->channel[i]);
184
185 pdata->channel[i] = NULL;
186 }
187
188 pdata->channel_count = 0;
189 }
190
xgbe_alloc_channels(struct xgbe_prv_data * pdata)191 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
192 {
193 struct xgbe_channel *channel;
194 struct xgbe_ring *ring;
195 unsigned int count, i;
196 unsigned int cpu;
197 int node;
198
199 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
200 for (i = 0; i < count; i++) {
201 /* Attempt to use a CPU on the node the device is on */
202 cpu = cpumask_local_spread(i, dev_to_node(pdata->dev));
203
204 /* Set the allocation node based on the returned CPU */
205 node = cpu_to_node(cpu);
206
207 channel = xgbe_alloc_node(sizeof(*channel), node);
208 if (!channel)
209 goto err_mem;
210 pdata->channel[i] = channel;
211
212 snprintf(channel->name, sizeof(channel->name), "channel-%u", i);
213 channel->pdata = pdata;
214 channel->queue_index = i;
215 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
216 (DMA_CH_INC * i);
217 channel->node = node;
218 cpumask_set_cpu(cpu, &channel->affinity_mask);
219
220 if (pdata->per_channel_irq)
221 channel->dma_irq = pdata->channel_irq[i];
222
223 if (i < pdata->tx_ring_count) {
224 ring = xgbe_alloc_node(sizeof(*ring), node);
225 if (!ring)
226 goto err_mem;
227
228 spin_lock_init(&ring->lock);
229 ring->node = node;
230
231 channel->tx_ring = ring;
232 }
233
234 if (i < pdata->rx_ring_count) {
235 ring = xgbe_alloc_node(sizeof(*ring), node);
236 if (!ring)
237 goto err_mem;
238
239 spin_lock_init(&ring->lock);
240 ring->node = node;
241
242 channel->rx_ring = ring;
243 }
244
245 netif_dbg(pdata, drv, pdata->netdev,
246 "%s: cpu=%u, node=%d\n", channel->name, cpu, node);
247
248 netif_dbg(pdata, drv, pdata->netdev,
249 "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
250 channel->name, channel->dma_regs, channel->dma_irq,
251 channel->tx_ring, channel->rx_ring);
252 }
253
254 pdata->channel_count = count;
255
256 return 0;
257
258 err_mem:
259 xgbe_free_channels(pdata);
260
261 return -ENOMEM;
262 }
263
xgbe_tx_avail_desc(struct xgbe_ring * ring)264 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
265 {
266 return (ring->rdesc_count - (ring->cur - ring->dirty));
267 }
268
xgbe_rx_dirty_desc(struct xgbe_ring * ring)269 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
270 {
271 return (ring->cur - ring->dirty);
272 }
273
xgbe_maybe_stop_tx_queue(struct xgbe_channel * channel,struct xgbe_ring * ring,unsigned int count)274 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
275 struct xgbe_ring *ring, unsigned int count)
276 {
277 struct xgbe_prv_data *pdata = channel->pdata;
278
279 if (count > xgbe_tx_avail_desc(ring)) {
280 netif_info(pdata, drv, pdata->netdev,
281 "Tx queue stopped, not enough descriptors available\n");
282 netif_stop_subqueue(pdata->netdev, channel->queue_index);
283 ring->tx.queue_stopped = 1;
284
285 /* If we haven't notified the hardware because of xmit_more
286 * support, tell it now
287 */
288 if (ring->tx.xmit_more)
289 pdata->hw_if.tx_start_xmit(channel, ring);
290
291 return NETDEV_TX_BUSY;
292 }
293
294 return 0;
295 }
296
xgbe_calc_rx_buf_size(struct net_device * netdev,unsigned int mtu)297 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
298 {
299 unsigned int rx_buf_size;
300
301 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
302 rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
303
304 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
305 ~(XGBE_RX_BUF_ALIGN - 1);
306
307 return rx_buf_size;
308 }
309
xgbe_enable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)310 static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata,
311 struct xgbe_channel *channel)
312 {
313 struct xgbe_hw_if *hw_if = &pdata->hw_if;
314 enum xgbe_int int_id;
315
316 if (channel->tx_ring && channel->rx_ring)
317 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
318 else if (channel->tx_ring)
319 int_id = XGMAC_INT_DMA_CH_SR_TI;
320 else if (channel->rx_ring)
321 int_id = XGMAC_INT_DMA_CH_SR_RI;
322 else
323 return;
324
325 hw_if->enable_int(channel, int_id);
326 }
327
xgbe_enable_rx_tx_ints(struct xgbe_prv_data * pdata)328 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
329 {
330 unsigned int i;
331
332 for (i = 0; i < pdata->channel_count; i++)
333 xgbe_enable_rx_tx_int(pdata, pdata->channel[i]);
334 }
335
xgbe_disable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)336 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata,
337 struct xgbe_channel *channel)
338 {
339 struct xgbe_hw_if *hw_if = &pdata->hw_if;
340 enum xgbe_int int_id;
341
342 if (channel->tx_ring && channel->rx_ring)
343 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
344 else if (channel->tx_ring)
345 int_id = XGMAC_INT_DMA_CH_SR_TI;
346 else if (channel->rx_ring)
347 int_id = XGMAC_INT_DMA_CH_SR_RI;
348 else
349 return;
350
351 hw_if->disable_int(channel, int_id);
352 }
353
xgbe_disable_rx_tx_ints(struct xgbe_prv_data * pdata)354 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
355 {
356 unsigned int i;
357
358 for (i = 0; i < pdata->channel_count; i++)
359 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
360 }
361
xgbe_ecc_sec(struct xgbe_prv_data * pdata,unsigned long * period,unsigned int * count,const char * area)362 static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period,
363 unsigned int *count, const char *area)
364 {
365 if (time_before(jiffies, *period)) {
366 (*count)++;
367 } else {
368 *period = jiffies + (ecc_sec_period * HZ);
369 *count = 1;
370 }
371
372 if (*count > ecc_sec_info_threshold)
373 dev_warn_once(pdata->dev,
374 "%s ECC corrected errors exceed informational threshold\n",
375 area);
376
377 if (*count > ecc_sec_warn_threshold) {
378 dev_warn_once(pdata->dev,
379 "%s ECC corrected errors exceed warning threshold\n",
380 area);
381 return true;
382 }
383
384 return false;
385 }
386
xgbe_ecc_ded(struct xgbe_prv_data * pdata,unsigned long * period,unsigned int * count,const char * area)387 static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period,
388 unsigned int *count, const char *area)
389 {
390 if (time_before(jiffies, *period)) {
391 (*count)++;
392 } else {
393 *period = jiffies + (ecc_ded_period * HZ);
394 *count = 1;
395 }
396
397 if (*count > ecc_ded_threshold) {
398 netdev_alert(pdata->netdev,
399 "%s ECC detected errors exceed threshold\n",
400 area);
401 return true;
402 }
403
404 return false;
405 }
406
xgbe_ecc_isr_task(unsigned long data)407 static void xgbe_ecc_isr_task(unsigned long data)
408 {
409 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
410 unsigned int ecc_isr;
411 bool stop = false;
412
413 /* Mask status with only the interrupts we care about */
414 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
415 ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER);
416 netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr);
417
418 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) {
419 stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period,
420 &pdata->tx_ded_count, "TX fifo");
421 }
422
423 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) {
424 stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period,
425 &pdata->rx_ded_count, "RX fifo");
426 }
427
428 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) {
429 stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period,
430 &pdata->desc_ded_count,
431 "descriptor cache");
432 }
433
434 if (stop) {
435 pdata->hw_if.disable_ecc_ded(pdata);
436 schedule_work(&pdata->stopdev_work);
437 goto out;
438 }
439
440 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) {
441 if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period,
442 &pdata->tx_sec_count, "TX fifo"))
443 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX);
444 }
445
446 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC))
447 if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period,
448 &pdata->rx_sec_count, "RX fifo"))
449 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX);
450
451 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC))
452 if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period,
453 &pdata->desc_sec_count, "descriptor cache"))
454 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC);
455
456 out:
457 /* Clear all ECC interrupts */
458 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
459
460 /* Reissue interrupt if status is not clear */
461 if (pdata->vdata->irq_reissue_support)
462 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 1);
463 }
464
xgbe_ecc_isr(int irq,void * data)465 static irqreturn_t xgbe_ecc_isr(int irq, void *data)
466 {
467 struct xgbe_prv_data *pdata = data;
468
469 if (pdata->isr_as_tasklet)
470 tasklet_schedule(&pdata->tasklet_ecc);
471 else
472 xgbe_ecc_isr_task((unsigned long)pdata);
473
474 return IRQ_HANDLED;
475 }
476
xgbe_isr_task(unsigned long data)477 static void xgbe_isr_task(unsigned long data)
478 {
479 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
480 struct xgbe_hw_if *hw_if = &pdata->hw_if;
481 struct xgbe_channel *channel;
482 unsigned int dma_isr, dma_ch_isr;
483 unsigned int mac_isr, mac_tssr, mac_mdioisr;
484 unsigned int i;
485
486 /* The DMA interrupt status register also reports MAC and MTL
487 * interrupts. So for polling mode, we just need to check for
488 * this register to be non-zero
489 */
490 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
491 if (!dma_isr)
492 goto isr_done;
493
494 netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
495
496 for (i = 0; i < pdata->channel_count; i++) {
497 if (!(dma_isr & (1 << i)))
498 continue;
499
500 channel = pdata->channel[i];
501
502 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
503 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
504 i, dma_ch_isr);
505
506 /* The TI or RI interrupt bits may still be set even if using
507 * per channel DMA interrupts. Check to be sure those are not
508 * enabled before using the private data napi structure.
509 */
510 if (!pdata->per_channel_irq &&
511 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
512 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
513 if (napi_schedule_prep(&pdata->napi)) {
514 /* Disable Tx and Rx interrupts */
515 xgbe_disable_rx_tx_ints(pdata);
516
517 /* Turn on polling */
518 __napi_schedule_irqoff(&pdata->napi);
519 }
520 } else {
521 /* Don't clear Rx/Tx status if doing per channel DMA
522 * interrupts, these will be cleared by the ISR for
523 * per channel DMA interrupts.
524 */
525 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
526 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
527 }
528
529 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
530 pdata->ext_stats.rx_buffer_unavailable++;
531
532 /* Restart the device on a Fatal Bus Error */
533 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
534 schedule_work(&pdata->restart_work);
535
536 /* Clear interrupt signals */
537 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
538 }
539
540 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
541 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
542
543 netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n",
544 mac_isr);
545
546 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
547 hw_if->tx_mmc_int(pdata);
548
549 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
550 hw_if->rx_mmc_int(pdata);
551
552 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
553 mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
554
555 netif_dbg(pdata, intr, pdata->netdev,
556 "MAC_TSSR=%#010x\n", mac_tssr);
557
558 if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
559 /* Read Tx Timestamp to clear interrupt */
560 pdata->tx_tstamp =
561 hw_if->get_tx_tstamp(pdata);
562 queue_work(pdata->dev_workqueue,
563 &pdata->tx_tstamp_work);
564 }
565 }
566
567 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
568 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
569
570 netif_dbg(pdata, intr, pdata->netdev,
571 "MAC_MDIOISR=%#010x\n", mac_mdioisr);
572
573 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
574 SNGLCOMPINT))
575 complete(&pdata->mdio_complete);
576 }
577 }
578
579 isr_done:
580 /* If there is not a separate AN irq, handle it here */
581 if (pdata->dev_irq == pdata->an_irq)
582 pdata->phy_if.an_isr(pdata);
583
584 /* If there is not a separate ECC irq, handle it here */
585 if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))
586 xgbe_ecc_isr_task((unsigned long)pdata);
587
588 /* If there is not a separate I2C irq, handle it here */
589 if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq))
590 pdata->i2c_if.i2c_isr(pdata);
591
592 /* Reissue interrupt if status is not clear */
593 if (pdata->vdata->irq_reissue_support) {
594 unsigned int reissue_mask;
595
596 reissue_mask = 1 << 0;
597 if (!pdata->per_channel_irq)
598 reissue_mask |= 0xffff << 4;
599
600 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, reissue_mask);
601 }
602 }
603
xgbe_isr(int irq,void * data)604 static irqreturn_t xgbe_isr(int irq, void *data)
605 {
606 struct xgbe_prv_data *pdata = data;
607
608 if (pdata->isr_as_tasklet)
609 tasklet_schedule(&pdata->tasklet_dev);
610 else
611 xgbe_isr_task((unsigned long)pdata);
612
613 return IRQ_HANDLED;
614 }
615
xgbe_dma_isr(int irq,void * data)616 static irqreturn_t xgbe_dma_isr(int irq, void *data)
617 {
618 struct xgbe_channel *channel = data;
619 struct xgbe_prv_data *pdata = channel->pdata;
620 unsigned int dma_status;
621
622 /* Per channel DMA interrupts are enabled, so we use the per
623 * channel napi structure and not the private data napi structure
624 */
625 if (napi_schedule_prep(&channel->napi)) {
626 /* Disable Tx and Rx interrupts */
627 if (pdata->channel_irq_mode)
628 xgbe_disable_rx_tx_int(pdata, channel);
629 else
630 disable_irq_nosync(channel->dma_irq);
631
632 /* Turn on polling */
633 __napi_schedule_irqoff(&channel->napi);
634 }
635
636 /* Clear Tx/Rx signals */
637 dma_status = 0;
638 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
639 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
640 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
641
642 return IRQ_HANDLED;
643 }
644
xgbe_tx_timer(struct timer_list * t)645 static void xgbe_tx_timer(struct timer_list *t)
646 {
647 struct xgbe_channel *channel = from_timer(channel, t, tx_timer);
648 struct xgbe_prv_data *pdata = channel->pdata;
649 struct napi_struct *napi;
650
651 DBGPR("-->xgbe_tx_timer\n");
652
653 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
654
655 if (napi_schedule_prep(napi)) {
656 /* Disable Tx and Rx interrupts */
657 if (pdata->per_channel_irq)
658 if (pdata->channel_irq_mode)
659 xgbe_disable_rx_tx_int(pdata, channel);
660 else
661 disable_irq_nosync(channel->dma_irq);
662 else
663 xgbe_disable_rx_tx_ints(pdata);
664
665 /* Turn on polling */
666 __napi_schedule(napi);
667 }
668
669 channel->tx_timer_active = 0;
670
671 DBGPR("<--xgbe_tx_timer\n");
672 }
673
xgbe_service(struct work_struct * work)674 static void xgbe_service(struct work_struct *work)
675 {
676 struct xgbe_prv_data *pdata = container_of(work,
677 struct xgbe_prv_data,
678 service_work);
679
680 pdata->phy_if.phy_status(pdata);
681 }
682
xgbe_service_timer(struct timer_list * t)683 static void xgbe_service_timer(struct timer_list *t)
684 {
685 struct xgbe_prv_data *pdata = from_timer(pdata, t, service_timer);
686
687 queue_work(pdata->dev_workqueue, &pdata->service_work);
688
689 mod_timer(&pdata->service_timer, jiffies + HZ);
690 }
691
xgbe_init_timers(struct xgbe_prv_data * pdata)692 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
693 {
694 struct xgbe_channel *channel;
695 unsigned int i;
696
697 timer_setup(&pdata->service_timer, xgbe_service_timer, 0);
698
699 for (i = 0; i < pdata->channel_count; i++) {
700 channel = pdata->channel[i];
701 if (!channel->tx_ring)
702 break;
703
704 timer_setup(&channel->tx_timer, xgbe_tx_timer, 0);
705 }
706 }
707
xgbe_start_timers(struct xgbe_prv_data * pdata)708 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
709 {
710 mod_timer(&pdata->service_timer, jiffies + HZ);
711 }
712
xgbe_stop_timers(struct xgbe_prv_data * pdata)713 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
714 {
715 struct xgbe_channel *channel;
716 unsigned int i;
717
718 del_timer_sync(&pdata->service_timer);
719
720 for (i = 0; i < pdata->channel_count; i++) {
721 channel = pdata->channel[i];
722 if (!channel->tx_ring)
723 break;
724
725 del_timer_sync(&channel->tx_timer);
726 }
727 }
728
xgbe_get_all_hw_features(struct xgbe_prv_data * pdata)729 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
730 {
731 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
732 struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
733
734 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
735 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
736 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
737
738 memset(hw_feat, 0, sizeof(*hw_feat));
739
740 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
741
742 /* Hardware feature register 0 */
743 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
744 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
745 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
746 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
747 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
748 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
749 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
750 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
751 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
752 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
753 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
754 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
755 ADDMACADRSEL);
756 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
757 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
758 hw_feat->vxn = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN);
759
760 /* Hardware feature register 1 */
761 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
762 RXFIFOSIZE);
763 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
764 TXFIFOSIZE);
765 hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
766 hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
767 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
768 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
769 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
770 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
771 hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
772 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
773 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
774 HASHTBLSZ);
775 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
776 L3L4FNUM);
777
778 /* Hardware feature register 2 */
779 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
780 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
781 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
782 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
783 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
784 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
785
786 /* Translate the Hash Table size into actual number */
787 switch (hw_feat->hash_table_size) {
788 case 0:
789 break;
790 case 1:
791 hw_feat->hash_table_size = 64;
792 break;
793 case 2:
794 hw_feat->hash_table_size = 128;
795 break;
796 case 3:
797 hw_feat->hash_table_size = 256;
798 break;
799 }
800
801 /* Translate the address width setting into actual number */
802 switch (hw_feat->dma_width) {
803 case 0:
804 hw_feat->dma_width = 32;
805 break;
806 case 1:
807 hw_feat->dma_width = 40;
808 break;
809 case 2:
810 hw_feat->dma_width = 48;
811 break;
812 default:
813 hw_feat->dma_width = 32;
814 }
815
816 /* The Queue, Channel and TC counts are zero based so increment them
817 * to get the actual number
818 */
819 hw_feat->rx_q_cnt++;
820 hw_feat->tx_q_cnt++;
821 hw_feat->rx_ch_cnt++;
822 hw_feat->tx_ch_cnt++;
823 hw_feat->tc_cnt++;
824
825 /* Translate the fifo sizes into actual numbers */
826 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
827 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
828
829 if (netif_msg_probe(pdata)) {
830 dev_dbg(pdata->dev, "Hardware features:\n");
831
832 /* Hardware feature register 0 */
833 dev_dbg(pdata->dev, " 1GbE support : %s\n",
834 hw_feat->gmii ? "yes" : "no");
835 dev_dbg(pdata->dev, " VLAN hash filter : %s\n",
836 hw_feat->vlhash ? "yes" : "no");
837 dev_dbg(pdata->dev, " MDIO interface : %s\n",
838 hw_feat->sma ? "yes" : "no");
839 dev_dbg(pdata->dev, " Wake-up packet support : %s\n",
840 hw_feat->rwk ? "yes" : "no");
841 dev_dbg(pdata->dev, " Magic packet support : %s\n",
842 hw_feat->mgk ? "yes" : "no");
843 dev_dbg(pdata->dev, " Management counters : %s\n",
844 hw_feat->mmc ? "yes" : "no");
845 dev_dbg(pdata->dev, " ARP offload : %s\n",
846 hw_feat->aoe ? "yes" : "no");
847 dev_dbg(pdata->dev, " IEEE 1588-2008 Timestamp : %s\n",
848 hw_feat->ts ? "yes" : "no");
849 dev_dbg(pdata->dev, " Energy Efficient Ethernet : %s\n",
850 hw_feat->eee ? "yes" : "no");
851 dev_dbg(pdata->dev, " TX checksum offload : %s\n",
852 hw_feat->tx_coe ? "yes" : "no");
853 dev_dbg(pdata->dev, " RX checksum offload : %s\n",
854 hw_feat->rx_coe ? "yes" : "no");
855 dev_dbg(pdata->dev, " Additional MAC addresses : %u\n",
856 hw_feat->addn_mac);
857 dev_dbg(pdata->dev, " Timestamp source : %s\n",
858 (hw_feat->ts_src == 1) ? "internal" :
859 (hw_feat->ts_src == 2) ? "external" :
860 (hw_feat->ts_src == 3) ? "internal/external" : "n/a");
861 dev_dbg(pdata->dev, " SA/VLAN insertion : %s\n",
862 hw_feat->sa_vlan_ins ? "yes" : "no");
863 dev_dbg(pdata->dev, " VXLAN/NVGRE support : %s\n",
864 hw_feat->vxn ? "yes" : "no");
865
866 /* Hardware feature register 1 */
867 dev_dbg(pdata->dev, " RX fifo size : %u\n",
868 hw_feat->rx_fifo_size);
869 dev_dbg(pdata->dev, " TX fifo size : %u\n",
870 hw_feat->tx_fifo_size);
871 dev_dbg(pdata->dev, " IEEE 1588 high word : %s\n",
872 hw_feat->adv_ts_hi ? "yes" : "no");
873 dev_dbg(pdata->dev, " DMA width : %u\n",
874 hw_feat->dma_width);
875 dev_dbg(pdata->dev, " Data Center Bridging : %s\n",
876 hw_feat->dcb ? "yes" : "no");
877 dev_dbg(pdata->dev, " Split header : %s\n",
878 hw_feat->sph ? "yes" : "no");
879 dev_dbg(pdata->dev, " TCP Segmentation Offload : %s\n",
880 hw_feat->tso ? "yes" : "no");
881 dev_dbg(pdata->dev, " Debug memory interface : %s\n",
882 hw_feat->dma_debug ? "yes" : "no");
883 dev_dbg(pdata->dev, " Receive Side Scaling : %s\n",
884 hw_feat->rss ? "yes" : "no");
885 dev_dbg(pdata->dev, " Traffic Class count : %u\n",
886 hw_feat->tc_cnt);
887 dev_dbg(pdata->dev, " Hash table size : %u\n",
888 hw_feat->hash_table_size);
889 dev_dbg(pdata->dev, " L3/L4 Filters : %u\n",
890 hw_feat->l3l4_filter_num);
891
892 /* Hardware feature register 2 */
893 dev_dbg(pdata->dev, " RX queue count : %u\n",
894 hw_feat->rx_q_cnt);
895 dev_dbg(pdata->dev, " TX queue count : %u\n",
896 hw_feat->tx_q_cnt);
897 dev_dbg(pdata->dev, " RX DMA channel count : %u\n",
898 hw_feat->rx_ch_cnt);
899 dev_dbg(pdata->dev, " TX DMA channel count : %u\n",
900 hw_feat->rx_ch_cnt);
901 dev_dbg(pdata->dev, " PPS outputs : %u\n",
902 hw_feat->pps_out_num);
903 dev_dbg(pdata->dev, " Auxiliary snapshot inputs : %u\n",
904 hw_feat->aux_snap_num);
905 }
906 }
907
xgbe_disable_vxlan_offloads(struct xgbe_prv_data * pdata)908 static void xgbe_disable_vxlan_offloads(struct xgbe_prv_data *pdata)
909 {
910 struct net_device *netdev = pdata->netdev;
911
912 if (!pdata->vxlan_offloads_set)
913 return;
914
915 netdev_info(netdev, "disabling VXLAN offloads\n");
916
917 netdev->hw_enc_features &= ~(NETIF_F_SG |
918 NETIF_F_IP_CSUM |
919 NETIF_F_IPV6_CSUM |
920 NETIF_F_RXCSUM |
921 NETIF_F_TSO |
922 NETIF_F_TSO6 |
923 NETIF_F_GRO |
924 NETIF_F_GSO_UDP_TUNNEL |
925 NETIF_F_GSO_UDP_TUNNEL_CSUM);
926
927 netdev->features &= ~(NETIF_F_GSO_UDP_TUNNEL |
928 NETIF_F_GSO_UDP_TUNNEL_CSUM);
929
930 pdata->vxlan_offloads_set = 0;
931 }
932
xgbe_disable_vxlan_hw(struct xgbe_prv_data * pdata)933 static void xgbe_disable_vxlan_hw(struct xgbe_prv_data *pdata)
934 {
935 if (!pdata->vxlan_port_set)
936 return;
937
938 pdata->hw_if.disable_vxlan(pdata);
939
940 pdata->vxlan_port_set = 0;
941 pdata->vxlan_port = 0;
942 }
943
xgbe_disable_vxlan_accel(struct xgbe_prv_data * pdata)944 static void xgbe_disable_vxlan_accel(struct xgbe_prv_data *pdata)
945 {
946 xgbe_disable_vxlan_offloads(pdata);
947
948 xgbe_disable_vxlan_hw(pdata);
949 }
950
xgbe_enable_vxlan_offloads(struct xgbe_prv_data * pdata)951 static void xgbe_enable_vxlan_offloads(struct xgbe_prv_data *pdata)
952 {
953 struct net_device *netdev = pdata->netdev;
954
955 if (pdata->vxlan_offloads_set)
956 return;
957
958 netdev_info(netdev, "enabling VXLAN offloads\n");
959
960 netdev->hw_enc_features |= NETIF_F_SG |
961 NETIF_F_IP_CSUM |
962 NETIF_F_IPV6_CSUM |
963 NETIF_F_RXCSUM |
964 NETIF_F_TSO |
965 NETIF_F_TSO6 |
966 NETIF_F_GRO |
967 pdata->vxlan_features;
968
969 netdev->features |= pdata->vxlan_features;
970
971 pdata->vxlan_offloads_set = 1;
972 }
973
xgbe_enable_vxlan_hw(struct xgbe_prv_data * pdata)974 static void xgbe_enable_vxlan_hw(struct xgbe_prv_data *pdata)
975 {
976 struct xgbe_vxlan_data *vdata;
977
978 if (pdata->vxlan_port_set)
979 return;
980
981 if (list_empty(&pdata->vxlan_ports))
982 return;
983
984 vdata = list_first_entry(&pdata->vxlan_ports,
985 struct xgbe_vxlan_data, list);
986
987 pdata->vxlan_port_set = 1;
988 pdata->vxlan_port = be16_to_cpu(vdata->port);
989
990 pdata->hw_if.enable_vxlan(pdata);
991 }
992
xgbe_enable_vxlan_accel(struct xgbe_prv_data * pdata)993 static void xgbe_enable_vxlan_accel(struct xgbe_prv_data *pdata)
994 {
995 /* VXLAN acceleration desired? */
996 if (!pdata->vxlan_features)
997 return;
998
999 /* VXLAN acceleration possible? */
1000 if (pdata->vxlan_force_disable)
1001 return;
1002
1003 xgbe_enable_vxlan_hw(pdata);
1004
1005 xgbe_enable_vxlan_offloads(pdata);
1006 }
1007
xgbe_reset_vxlan_accel(struct xgbe_prv_data * pdata)1008 static void xgbe_reset_vxlan_accel(struct xgbe_prv_data *pdata)
1009 {
1010 xgbe_disable_vxlan_hw(pdata);
1011
1012 if (pdata->vxlan_features)
1013 xgbe_enable_vxlan_offloads(pdata);
1014
1015 pdata->vxlan_force_disable = 0;
1016 }
1017
xgbe_napi_enable(struct xgbe_prv_data * pdata,unsigned int add)1018 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
1019 {
1020 struct xgbe_channel *channel;
1021 unsigned int i;
1022
1023 if (pdata->per_channel_irq) {
1024 for (i = 0; i < pdata->channel_count; i++) {
1025 channel = pdata->channel[i];
1026 if (add)
1027 netif_napi_add(pdata->netdev, &channel->napi,
1028 xgbe_one_poll, NAPI_POLL_WEIGHT);
1029
1030 napi_enable(&channel->napi);
1031 }
1032 } else {
1033 if (add)
1034 netif_napi_add(pdata->netdev, &pdata->napi,
1035 xgbe_all_poll, NAPI_POLL_WEIGHT);
1036
1037 napi_enable(&pdata->napi);
1038 }
1039 }
1040
xgbe_napi_disable(struct xgbe_prv_data * pdata,unsigned int del)1041 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
1042 {
1043 struct xgbe_channel *channel;
1044 unsigned int i;
1045
1046 if (pdata->per_channel_irq) {
1047 for (i = 0; i < pdata->channel_count; i++) {
1048 channel = pdata->channel[i];
1049 napi_disable(&channel->napi);
1050
1051 if (del)
1052 netif_napi_del(&channel->napi);
1053 }
1054 } else {
1055 napi_disable(&pdata->napi);
1056
1057 if (del)
1058 netif_napi_del(&pdata->napi);
1059 }
1060 }
1061
xgbe_request_irqs(struct xgbe_prv_data * pdata)1062 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
1063 {
1064 struct xgbe_channel *channel;
1065 struct net_device *netdev = pdata->netdev;
1066 unsigned int i;
1067 int ret;
1068
1069 tasklet_init(&pdata->tasklet_dev, xgbe_isr_task, (unsigned long)pdata);
1070 tasklet_init(&pdata->tasklet_ecc, xgbe_ecc_isr_task,
1071 (unsigned long)pdata);
1072
1073 ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
1074 netdev_name(netdev), pdata);
1075 if (ret) {
1076 netdev_alert(netdev, "error requesting irq %d\n",
1077 pdata->dev_irq);
1078 return ret;
1079 }
1080
1081 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) {
1082 ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr,
1083 0, pdata->ecc_name, pdata);
1084 if (ret) {
1085 netdev_alert(netdev, "error requesting ecc irq %d\n",
1086 pdata->ecc_irq);
1087 goto err_dev_irq;
1088 }
1089 }
1090
1091 if (!pdata->per_channel_irq)
1092 return 0;
1093
1094 for (i = 0; i < pdata->channel_count; i++) {
1095 channel = pdata->channel[i];
1096 snprintf(channel->dma_irq_name,
1097 sizeof(channel->dma_irq_name) - 1,
1098 "%s-TxRx-%u", netdev_name(netdev),
1099 channel->queue_index);
1100
1101 ret = devm_request_irq(pdata->dev, channel->dma_irq,
1102 xgbe_dma_isr, 0,
1103 channel->dma_irq_name, channel);
1104 if (ret) {
1105 netdev_alert(netdev, "error requesting irq %d\n",
1106 channel->dma_irq);
1107 goto err_dma_irq;
1108 }
1109
1110 irq_set_affinity_hint(channel->dma_irq,
1111 &channel->affinity_mask);
1112 }
1113
1114 return 0;
1115
1116 err_dma_irq:
1117 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
1118 for (i--; i < pdata->channel_count; i--) {
1119 channel = pdata->channel[i];
1120
1121 irq_set_affinity_hint(channel->dma_irq, NULL);
1122 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1123 }
1124
1125 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1126 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1127
1128 err_dev_irq:
1129 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1130
1131 return ret;
1132 }
1133
xgbe_free_irqs(struct xgbe_prv_data * pdata)1134 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
1135 {
1136 struct xgbe_channel *channel;
1137 unsigned int i;
1138
1139 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1140
1141 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1142 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1143
1144 if (!pdata->per_channel_irq)
1145 return;
1146
1147 for (i = 0; i < pdata->channel_count; i++) {
1148 channel = pdata->channel[i];
1149
1150 irq_set_affinity_hint(channel->dma_irq, NULL);
1151 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1152 }
1153 }
1154
xgbe_init_tx_coalesce(struct xgbe_prv_data * pdata)1155 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
1156 {
1157 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1158
1159 DBGPR("-->xgbe_init_tx_coalesce\n");
1160
1161 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
1162 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
1163
1164 hw_if->config_tx_coalesce(pdata);
1165
1166 DBGPR("<--xgbe_init_tx_coalesce\n");
1167 }
1168
xgbe_init_rx_coalesce(struct xgbe_prv_data * pdata)1169 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
1170 {
1171 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1172
1173 DBGPR("-->xgbe_init_rx_coalesce\n");
1174
1175 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
1176 pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
1177 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
1178
1179 hw_if->config_rx_coalesce(pdata);
1180
1181 DBGPR("<--xgbe_init_rx_coalesce\n");
1182 }
1183
xgbe_free_tx_data(struct xgbe_prv_data * pdata)1184 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
1185 {
1186 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1187 struct xgbe_ring *ring;
1188 struct xgbe_ring_data *rdata;
1189 unsigned int i, j;
1190
1191 DBGPR("-->xgbe_free_tx_data\n");
1192
1193 for (i = 0; i < pdata->channel_count; i++) {
1194 ring = pdata->channel[i]->tx_ring;
1195 if (!ring)
1196 break;
1197
1198 for (j = 0; j < ring->rdesc_count; j++) {
1199 rdata = XGBE_GET_DESC_DATA(ring, j);
1200 desc_if->unmap_rdata(pdata, rdata);
1201 }
1202 }
1203
1204 DBGPR("<--xgbe_free_tx_data\n");
1205 }
1206
xgbe_free_rx_data(struct xgbe_prv_data * pdata)1207 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
1208 {
1209 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1210 struct xgbe_ring *ring;
1211 struct xgbe_ring_data *rdata;
1212 unsigned int i, j;
1213
1214 DBGPR("-->xgbe_free_rx_data\n");
1215
1216 for (i = 0; i < pdata->channel_count; i++) {
1217 ring = pdata->channel[i]->rx_ring;
1218 if (!ring)
1219 break;
1220
1221 for (j = 0; j < ring->rdesc_count; j++) {
1222 rdata = XGBE_GET_DESC_DATA(ring, j);
1223 desc_if->unmap_rdata(pdata, rdata);
1224 }
1225 }
1226
1227 DBGPR("<--xgbe_free_rx_data\n");
1228 }
1229
xgbe_phy_reset(struct xgbe_prv_data * pdata)1230 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1231 {
1232 pdata->phy_link = -1;
1233 pdata->phy_speed = SPEED_UNKNOWN;
1234
1235 return pdata->phy_if.phy_reset(pdata);
1236 }
1237
xgbe_powerdown(struct net_device * netdev,unsigned int caller)1238 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
1239 {
1240 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1241 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1242 unsigned long flags;
1243
1244 DBGPR("-->xgbe_powerdown\n");
1245
1246 if (!netif_running(netdev) ||
1247 (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
1248 netdev_alert(netdev, "Device is already powered down\n");
1249 DBGPR("<--xgbe_powerdown\n");
1250 return -EINVAL;
1251 }
1252
1253 spin_lock_irqsave(&pdata->lock, flags);
1254
1255 if (caller == XGMAC_DRIVER_CONTEXT)
1256 netif_device_detach(netdev);
1257
1258 netif_tx_stop_all_queues(netdev);
1259
1260 xgbe_stop_timers(pdata);
1261 flush_workqueue(pdata->dev_workqueue);
1262
1263 hw_if->powerdown_tx(pdata);
1264 hw_if->powerdown_rx(pdata);
1265
1266 xgbe_napi_disable(pdata, 0);
1267
1268 pdata->power_down = 1;
1269
1270 spin_unlock_irqrestore(&pdata->lock, flags);
1271
1272 DBGPR("<--xgbe_powerdown\n");
1273
1274 return 0;
1275 }
1276
xgbe_powerup(struct net_device * netdev,unsigned int caller)1277 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
1278 {
1279 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1280 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1281 unsigned long flags;
1282
1283 DBGPR("-->xgbe_powerup\n");
1284
1285 if (!netif_running(netdev) ||
1286 (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
1287 netdev_alert(netdev, "Device is already powered up\n");
1288 DBGPR("<--xgbe_powerup\n");
1289 return -EINVAL;
1290 }
1291
1292 spin_lock_irqsave(&pdata->lock, flags);
1293
1294 pdata->power_down = 0;
1295
1296 xgbe_napi_enable(pdata, 0);
1297
1298 hw_if->powerup_tx(pdata);
1299 hw_if->powerup_rx(pdata);
1300
1301 if (caller == XGMAC_DRIVER_CONTEXT)
1302 netif_device_attach(netdev);
1303
1304 netif_tx_start_all_queues(netdev);
1305
1306 xgbe_start_timers(pdata);
1307
1308 spin_unlock_irqrestore(&pdata->lock, flags);
1309
1310 DBGPR("<--xgbe_powerup\n");
1311
1312 return 0;
1313 }
1314
xgbe_free_memory(struct xgbe_prv_data * pdata)1315 static void xgbe_free_memory(struct xgbe_prv_data *pdata)
1316 {
1317 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1318
1319 /* Free the ring descriptors and buffers */
1320 desc_if->free_ring_resources(pdata);
1321
1322 /* Free the channel and ring structures */
1323 xgbe_free_channels(pdata);
1324 }
1325
xgbe_alloc_memory(struct xgbe_prv_data * pdata)1326 static int xgbe_alloc_memory(struct xgbe_prv_data *pdata)
1327 {
1328 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1329 struct net_device *netdev = pdata->netdev;
1330 int ret;
1331
1332 if (pdata->new_tx_ring_count) {
1333 pdata->tx_ring_count = pdata->new_tx_ring_count;
1334 pdata->tx_q_count = pdata->tx_ring_count;
1335 pdata->new_tx_ring_count = 0;
1336 }
1337
1338 if (pdata->new_rx_ring_count) {
1339 pdata->rx_ring_count = pdata->new_rx_ring_count;
1340 pdata->new_rx_ring_count = 0;
1341 }
1342
1343 /* Calculate the Rx buffer size before allocating rings */
1344 pdata->rx_buf_size = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1345
1346 /* Allocate the channel and ring structures */
1347 ret = xgbe_alloc_channels(pdata);
1348 if (ret)
1349 return ret;
1350
1351 /* Allocate the ring descriptors and buffers */
1352 ret = desc_if->alloc_ring_resources(pdata);
1353 if (ret)
1354 goto err_channels;
1355
1356 /* Initialize the service and Tx timers */
1357 xgbe_init_timers(pdata);
1358
1359 return 0;
1360
1361 err_channels:
1362 xgbe_free_memory(pdata);
1363
1364 return ret;
1365 }
1366
xgbe_start(struct xgbe_prv_data * pdata)1367 static int xgbe_start(struct xgbe_prv_data *pdata)
1368 {
1369 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1370 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1371 struct net_device *netdev = pdata->netdev;
1372 unsigned int i;
1373 int ret;
1374
1375 /* Set the number of queues */
1376 ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
1377 if (ret) {
1378 netdev_err(netdev, "error setting real tx queue count\n");
1379 return ret;
1380 }
1381
1382 ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count);
1383 if (ret) {
1384 netdev_err(netdev, "error setting real rx queue count\n");
1385 return ret;
1386 }
1387
1388 /* Set RSS lookup table data for programming */
1389 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
1390 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
1391 i % pdata->rx_ring_count);
1392
1393 ret = hw_if->init(pdata);
1394 if (ret)
1395 return ret;
1396
1397 xgbe_napi_enable(pdata, 1);
1398
1399 ret = xgbe_request_irqs(pdata);
1400 if (ret)
1401 goto err_napi;
1402
1403 ret = phy_if->phy_start(pdata);
1404 if (ret)
1405 goto err_irqs;
1406
1407 hw_if->enable_tx(pdata);
1408 hw_if->enable_rx(pdata);
1409
1410 udp_tunnel_get_rx_info(netdev);
1411
1412 netif_tx_start_all_queues(netdev);
1413
1414 xgbe_start_timers(pdata);
1415 queue_work(pdata->dev_workqueue, &pdata->service_work);
1416
1417 clear_bit(XGBE_STOPPED, &pdata->dev_state);
1418
1419 return 0;
1420
1421 err_irqs:
1422 xgbe_free_irqs(pdata);
1423
1424 err_napi:
1425 xgbe_napi_disable(pdata, 1);
1426
1427 hw_if->exit(pdata);
1428
1429 return ret;
1430 }
1431
xgbe_stop(struct xgbe_prv_data * pdata)1432 static void xgbe_stop(struct xgbe_prv_data *pdata)
1433 {
1434 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1435 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1436 struct xgbe_channel *channel;
1437 struct net_device *netdev = pdata->netdev;
1438 struct netdev_queue *txq;
1439 unsigned int i;
1440
1441 DBGPR("-->xgbe_stop\n");
1442
1443 if (test_bit(XGBE_STOPPED, &pdata->dev_state))
1444 return;
1445
1446 netif_tx_stop_all_queues(netdev);
1447
1448 xgbe_stop_timers(pdata);
1449 flush_workqueue(pdata->dev_workqueue);
1450
1451 xgbe_reset_vxlan_accel(pdata);
1452
1453 hw_if->disable_tx(pdata);
1454 hw_if->disable_rx(pdata);
1455
1456 phy_if->phy_stop(pdata);
1457
1458 xgbe_free_irqs(pdata);
1459
1460 xgbe_napi_disable(pdata, 1);
1461
1462 hw_if->exit(pdata);
1463
1464 for (i = 0; i < pdata->channel_count; i++) {
1465 channel = pdata->channel[i];
1466 if (!channel->tx_ring)
1467 continue;
1468
1469 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1470 netdev_tx_reset_queue(txq);
1471 }
1472
1473 set_bit(XGBE_STOPPED, &pdata->dev_state);
1474
1475 DBGPR("<--xgbe_stop\n");
1476 }
1477
xgbe_stopdev(struct work_struct * work)1478 static void xgbe_stopdev(struct work_struct *work)
1479 {
1480 struct xgbe_prv_data *pdata = container_of(work,
1481 struct xgbe_prv_data,
1482 stopdev_work);
1483
1484 rtnl_lock();
1485
1486 xgbe_stop(pdata);
1487
1488 xgbe_free_tx_data(pdata);
1489 xgbe_free_rx_data(pdata);
1490
1491 rtnl_unlock();
1492
1493 netdev_alert(pdata->netdev, "device stopped\n");
1494 }
1495
xgbe_full_restart_dev(struct xgbe_prv_data * pdata)1496 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata)
1497 {
1498 /* If not running, "restart" will happen on open */
1499 if (!netif_running(pdata->netdev))
1500 return;
1501
1502 xgbe_stop(pdata);
1503
1504 xgbe_free_memory(pdata);
1505 xgbe_alloc_memory(pdata);
1506
1507 xgbe_start(pdata);
1508 }
1509
xgbe_restart_dev(struct xgbe_prv_data * pdata)1510 void xgbe_restart_dev(struct xgbe_prv_data *pdata)
1511 {
1512 /* If not running, "restart" will happen on open */
1513 if (!netif_running(pdata->netdev))
1514 return;
1515
1516 xgbe_stop(pdata);
1517
1518 xgbe_free_tx_data(pdata);
1519 xgbe_free_rx_data(pdata);
1520
1521 xgbe_start(pdata);
1522 }
1523
xgbe_restart(struct work_struct * work)1524 static void xgbe_restart(struct work_struct *work)
1525 {
1526 struct xgbe_prv_data *pdata = container_of(work,
1527 struct xgbe_prv_data,
1528 restart_work);
1529
1530 rtnl_lock();
1531
1532 xgbe_restart_dev(pdata);
1533
1534 rtnl_unlock();
1535 }
1536
xgbe_tx_tstamp(struct work_struct * work)1537 static void xgbe_tx_tstamp(struct work_struct *work)
1538 {
1539 struct xgbe_prv_data *pdata = container_of(work,
1540 struct xgbe_prv_data,
1541 tx_tstamp_work);
1542 struct skb_shared_hwtstamps hwtstamps;
1543 u64 nsec;
1544 unsigned long flags;
1545
1546 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1547 if (!pdata->tx_tstamp_skb)
1548 goto unlock;
1549
1550 if (pdata->tx_tstamp) {
1551 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
1552 pdata->tx_tstamp);
1553
1554 memset(&hwtstamps, 0, sizeof(hwtstamps));
1555 hwtstamps.hwtstamp = ns_to_ktime(nsec);
1556 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
1557 }
1558
1559 dev_kfree_skb_any(pdata->tx_tstamp_skb);
1560
1561 pdata->tx_tstamp_skb = NULL;
1562
1563 unlock:
1564 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1565 }
1566
xgbe_get_hwtstamp_settings(struct xgbe_prv_data * pdata,struct ifreq * ifreq)1567 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1568 struct ifreq *ifreq)
1569 {
1570 if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1571 sizeof(pdata->tstamp_config)))
1572 return -EFAULT;
1573
1574 return 0;
1575 }
1576
xgbe_set_hwtstamp_settings(struct xgbe_prv_data * pdata,struct ifreq * ifreq)1577 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1578 struct ifreq *ifreq)
1579 {
1580 struct hwtstamp_config config;
1581 unsigned int mac_tscr;
1582
1583 if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1584 return -EFAULT;
1585
1586 if (config.flags)
1587 return -EINVAL;
1588
1589 mac_tscr = 0;
1590
1591 switch (config.tx_type) {
1592 case HWTSTAMP_TX_OFF:
1593 break;
1594
1595 case HWTSTAMP_TX_ON:
1596 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1597 break;
1598
1599 default:
1600 return -ERANGE;
1601 }
1602
1603 switch (config.rx_filter) {
1604 case HWTSTAMP_FILTER_NONE:
1605 break;
1606
1607 case HWTSTAMP_FILTER_NTP_ALL:
1608 case HWTSTAMP_FILTER_ALL:
1609 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1610 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1611 break;
1612
1613 /* PTP v2, UDP, any kind of event packet */
1614 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1615 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1616 /* PTP v1, UDP, any kind of event packet */
1617 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1618 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1619 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1620 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1621 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1622 break;
1623
1624 /* PTP v2, UDP, Sync packet */
1625 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1626 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1627 /* PTP v1, UDP, Sync packet */
1628 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1629 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1630 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1631 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1632 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1633 break;
1634
1635 /* PTP v2, UDP, Delay_req packet */
1636 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1637 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1638 /* PTP v1, UDP, Delay_req packet */
1639 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1640 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1641 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1642 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1643 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1644 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1645 break;
1646
1647 /* 802.AS1, Ethernet, any kind of event packet */
1648 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1649 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1650 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1651 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1652 break;
1653
1654 /* 802.AS1, Ethernet, Sync packet */
1655 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1656 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1657 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1658 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1659 break;
1660
1661 /* 802.AS1, Ethernet, Delay_req packet */
1662 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1663 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1664 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1665 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1666 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1667 break;
1668
1669 /* PTP v2/802.AS1, any layer, any kind of event packet */
1670 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1671 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1672 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1673 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1674 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1675 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1676 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1677 break;
1678
1679 /* PTP v2/802.AS1, any layer, Sync packet */
1680 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1681 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1682 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1683 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1684 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1685 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1686 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1687 break;
1688
1689 /* PTP v2/802.AS1, any layer, Delay_req packet */
1690 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1691 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1692 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1693 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1694 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1695 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1696 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1697 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1698 break;
1699
1700 default:
1701 return -ERANGE;
1702 }
1703
1704 pdata->hw_if.config_tstamp(pdata, mac_tscr);
1705
1706 memcpy(&pdata->tstamp_config, &config, sizeof(config));
1707
1708 return 0;
1709 }
1710
xgbe_prep_tx_tstamp(struct xgbe_prv_data * pdata,struct sk_buff * skb,struct xgbe_packet_data * packet)1711 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1712 struct sk_buff *skb,
1713 struct xgbe_packet_data *packet)
1714 {
1715 unsigned long flags;
1716
1717 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1718 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1719 if (pdata->tx_tstamp_skb) {
1720 /* Another timestamp in progress, ignore this one */
1721 XGMAC_SET_BITS(packet->attributes,
1722 TX_PACKET_ATTRIBUTES, PTP, 0);
1723 } else {
1724 pdata->tx_tstamp_skb = skb_get(skb);
1725 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1726 }
1727 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1728 }
1729
1730 skb_tx_timestamp(skb);
1731 }
1732
xgbe_prep_vlan(struct sk_buff * skb,struct xgbe_packet_data * packet)1733 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1734 {
1735 if (skb_vlan_tag_present(skb))
1736 packet->vlan_ctag = skb_vlan_tag_get(skb);
1737 }
1738
xgbe_prep_tso(struct sk_buff * skb,struct xgbe_packet_data * packet)1739 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1740 {
1741 int ret;
1742
1743 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1744 TSO_ENABLE))
1745 return 0;
1746
1747 ret = skb_cow_head(skb, 0);
1748 if (ret)
1749 return ret;
1750
1751 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, VXLAN)) {
1752 packet->header_len = skb_inner_transport_offset(skb) +
1753 inner_tcp_hdrlen(skb);
1754 packet->tcp_header_len = inner_tcp_hdrlen(skb);
1755 } else {
1756 packet->header_len = skb_transport_offset(skb) +
1757 tcp_hdrlen(skb);
1758 packet->tcp_header_len = tcp_hdrlen(skb);
1759 }
1760 packet->tcp_payload_len = skb->len - packet->header_len;
1761 packet->mss = skb_shinfo(skb)->gso_size;
1762
1763 DBGPR(" packet->header_len=%u\n", packet->header_len);
1764 DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1765 packet->tcp_header_len, packet->tcp_payload_len);
1766 DBGPR(" packet->mss=%u\n", packet->mss);
1767
1768 /* Update the number of packets that will ultimately be transmitted
1769 * along with the extra bytes for each extra packet
1770 */
1771 packet->tx_packets = skb_shinfo(skb)->gso_segs;
1772 packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1773
1774 return 0;
1775 }
1776
xgbe_is_vxlan(struct xgbe_prv_data * pdata,struct sk_buff * skb)1777 static bool xgbe_is_vxlan(struct xgbe_prv_data *pdata, struct sk_buff *skb)
1778 {
1779 struct xgbe_vxlan_data *vdata;
1780
1781 if (pdata->vxlan_force_disable)
1782 return false;
1783
1784 if (!skb->encapsulation)
1785 return false;
1786
1787 if (skb->ip_summed != CHECKSUM_PARTIAL)
1788 return false;
1789
1790 switch (skb->protocol) {
1791 case htons(ETH_P_IP):
1792 if (ip_hdr(skb)->protocol != IPPROTO_UDP)
1793 return false;
1794 break;
1795
1796 case htons(ETH_P_IPV6):
1797 if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP)
1798 return false;
1799 break;
1800
1801 default:
1802 return false;
1803 }
1804
1805 /* See if we have the UDP port in our list */
1806 list_for_each_entry(vdata, &pdata->vxlan_ports, list) {
1807 if ((skb->protocol == htons(ETH_P_IP)) &&
1808 (vdata->sa_family == AF_INET) &&
1809 (vdata->port == udp_hdr(skb)->dest))
1810 return true;
1811 else if ((skb->protocol == htons(ETH_P_IPV6)) &&
1812 (vdata->sa_family == AF_INET6) &&
1813 (vdata->port == udp_hdr(skb)->dest))
1814 return true;
1815 }
1816
1817 return false;
1818 }
1819
xgbe_is_tso(struct sk_buff * skb)1820 static int xgbe_is_tso(struct sk_buff *skb)
1821 {
1822 if (skb->ip_summed != CHECKSUM_PARTIAL)
1823 return 0;
1824
1825 if (!skb_is_gso(skb))
1826 return 0;
1827
1828 DBGPR(" TSO packet to be processed\n");
1829
1830 return 1;
1831 }
1832
xgbe_packet_info(struct xgbe_prv_data * pdata,struct xgbe_ring * ring,struct sk_buff * skb,struct xgbe_packet_data * packet)1833 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1834 struct xgbe_ring *ring, struct sk_buff *skb,
1835 struct xgbe_packet_data *packet)
1836 {
1837 struct skb_frag_struct *frag;
1838 unsigned int context_desc;
1839 unsigned int len;
1840 unsigned int i;
1841
1842 packet->skb = skb;
1843
1844 context_desc = 0;
1845 packet->rdesc_count = 0;
1846
1847 packet->tx_packets = 1;
1848 packet->tx_bytes = skb->len;
1849
1850 if (xgbe_is_tso(skb)) {
1851 /* TSO requires an extra descriptor if mss is different */
1852 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1853 context_desc = 1;
1854 packet->rdesc_count++;
1855 }
1856
1857 /* TSO requires an extra descriptor for TSO header */
1858 packet->rdesc_count++;
1859
1860 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1861 TSO_ENABLE, 1);
1862 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1863 CSUM_ENABLE, 1);
1864 } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1865 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1866 CSUM_ENABLE, 1);
1867
1868 if (xgbe_is_vxlan(pdata, skb))
1869 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1870 VXLAN, 1);
1871
1872 if (skb_vlan_tag_present(skb)) {
1873 /* VLAN requires an extra descriptor if tag is different */
1874 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1875 /* We can share with the TSO context descriptor */
1876 if (!context_desc) {
1877 context_desc = 1;
1878 packet->rdesc_count++;
1879 }
1880
1881 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1882 VLAN_CTAG, 1);
1883 }
1884
1885 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1886 (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1887 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1888 PTP, 1);
1889
1890 for (len = skb_headlen(skb); len;) {
1891 packet->rdesc_count++;
1892 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1893 }
1894
1895 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1896 frag = &skb_shinfo(skb)->frags[i];
1897 for (len = skb_frag_size(frag); len; ) {
1898 packet->rdesc_count++;
1899 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1900 }
1901 }
1902 }
1903
xgbe_open(struct net_device * netdev)1904 static int xgbe_open(struct net_device *netdev)
1905 {
1906 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1907 int ret;
1908
1909 /* Create the various names based on netdev name */
1910 snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
1911 netdev_name(netdev));
1912
1913 snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc",
1914 netdev_name(netdev));
1915
1916 snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c",
1917 netdev_name(netdev));
1918
1919 /* Create workqueues */
1920 pdata->dev_workqueue =
1921 create_singlethread_workqueue(netdev_name(netdev));
1922 if (!pdata->dev_workqueue) {
1923 netdev_err(netdev, "device workqueue creation failed\n");
1924 return -ENOMEM;
1925 }
1926
1927 pdata->an_workqueue =
1928 create_singlethread_workqueue(pdata->an_name);
1929 if (!pdata->an_workqueue) {
1930 netdev_err(netdev, "phy workqueue creation failed\n");
1931 ret = -ENOMEM;
1932 goto err_dev_wq;
1933 }
1934
1935 /* Reset the phy settings */
1936 ret = xgbe_phy_reset(pdata);
1937 if (ret)
1938 goto err_an_wq;
1939
1940 /* Enable the clocks */
1941 ret = clk_prepare_enable(pdata->sysclk);
1942 if (ret) {
1943 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1944 goto err_an_wq;
1945 }
1946
1947 ret = clk_prepare_enable(pdata->ptpclk);
1948 if (ret) {
1949 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1950 goto err_sysclk;
1951 }
1952
1953 INIT_WORK(&pdata->service_work, xgbe_service);
1954 INIT_WORK(&pdata->restart_work, xgbe_restart);
1955 INIT_WORK(&pdata->stopdev_work, xgbe_stopdev);
1956 INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1957
1958 ret = xgbe_alloc_memory(pdata);
1959 if (ret)
1960 goto err_ptpclk;
1961
1962 ret = xgbe_start(pdata);
1963 if (ret)
1964 goto err_mem;
1965
1966 clear_bit(XGBE_DOWN, &pdata->dev_state);
1967
1968 return 0;
1969
1970 err_mem:
1971 xgbe_free_memory(pdata);
1972
1973 err_ptpclk:
1974 clk_disable_unprepare(pdata->ptpclk);
1975
1976 err_sysclk:
1977 clk_disable_unprepare(pdata->sysclk);
1978
1979 err_an_wq:
1980 destroy_workqueue(pdata->an_workqueue);
1981
1982 err_dev_wq:
1983 destroy_workqueue(pdata->dev_workqueue);
1984
1985 return ret;
1986 }
1987
xgbe_close(struct net_device * netdev)1988 static int xgbe_close(struct net_device *netdev)
1989 {
1990 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1991
1992 /* Stop the device */
1993 xgbe_stop(pdata);
1994
1995 xgbe_free_memory(pdata);
1996
1997 /* Disable the clocks */
1998 clk_disable_unprepare(pdata->ptpclk);
1999 clk_disable_unprepare(pdata->sysclk);
2000
2001 flush_workqueue(pdata->an_workqueue);
2002 destroy_workqueue(pdata->an_workqueue);
2003
2004 flush_workqueue(pdata->dev_workqueue);
2005 destroy_workqueue(pdata->dev_workqueue);
2006
2007 set_bit(XGBE_DOWN, &pdata->dev_state);
2008
2009 return 0;
2010 }
2011
xgbe_xmit(struct sk_buff * skb,struct net_device * netdev)2012 static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
2013 {
2014 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2015 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2016 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2017 struct xgbe_channel *channel;
2018 struct xgbe_ring *ring;
2019 struct xgbe_packet_data *packet;
2020 struct netdev_queue *txq;
2021 int ret;
2022
2023 DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
2024
2025 channel = pdata->channel[skb->queue_mapping];
2026 txq = netdev_get_tx_queue(netdev, channel->queue_index);
2027 ring = channel->tx_ring;
2028 packet = &ring->packet_data;
2029
2030 ret = NETDEV_TX_OK;
2031
2032 if (skb->len == 0) {
2033 netif_err(pdata, tx_err, netdev,
2034 "empty skb received from stack\n");
2035 dev_kfree_skb_any(skb);
2036 goto tx_netdev_return;
2037 }
2038
2039 /* Calculate preliminary packet info */
2040 memset(packet, 0, sizeof(*packet));
2041 xgbe_packet_info(pdata, ring, skb, packet);
2042
2043 /* Check that there are enough descriptors available */
2044 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
2045 if (ret)
2046 goto tx_netdev_return;
2047
2048 ret = xgbe_prep_tso(skb, packet);
2049 if (ret) {
2050 netif_err(pdata, tx_err, netdev,
2051 "error processing TSO packet\n");
2052 dev_kfree_skb_any(skb);
2053 goto tx_netdev_return;
2054 }
2055 xgbe_prep_vlan(skb, packet);
2056
2057 if (!desc_if->map_tx_skb(channel, skb)) {
2058 dev_kfree_skb_any(skb);
2059 goto tx_netdev_return;
2060 }
2061
2062 xgbe_prep_tx_tstamp(pdata, skb, packet);
2063
2064 /* Report on the actual number of bytes (to be) sent */
2065 netdev_tx_sent_queue(txq, packet->tx_bytes);
2066
2067 /* Configure required descriptor fields for transmission */
2068 hw_if->dev_xmit(channel);
2069
2070 if (netif_msg_pktdata(pdata))
2071 xgbe_print_pkt(netdev, skb, true);
2072
2073 /* Stop the queue in advance if there may not be enough descriptors */
2074 xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
2075
2076 ret = NETDEV_TX_OK;
2077
2078 tx_netdev_return:
2079 return ret;
2080 }
2081
xgbe_set_rx_mode(struct net_device * netdev)2082 static void xgbe_set_rx_mode(struct net_device *netdev)
2083 {
2084 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2085 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2086
2087 DBGPR("-->xgbe_set_rx_mode\n");
2088
2089 hw_if->config_rx_mode(pdata);
2090
2091 DBGPR("<--xgbe_set_rx_mode\n");
2092 }
2093
xgbe_set_mac_address(struct net_device * netdev,void * addr)2094 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
2095 {
2096 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2097 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2098 struct sockaddr *saddr = addr;
2099
2100 DBGPR("-->xgbe_set_mac_address\n");
2101
2102 if (!is_valid_ether_addr(saddr->sa_data))
2103 return -EADDRNOTAVAIL;
2104
2105 memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
2106
2107 hw_if->set_mac_address(pdata, netdev->dev_addr);
2108
2109 DBGPR("<--xgbe_set_mac_address\n");
2110
2111 return 0;
2112 }
2113
xgbe_ioctl(struct net_device * netdev,struct ifreq * ifreq,int cmd)2114 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
2115 {
2116 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2117 int ret;
2118
2119 switch (cmd) {
2120 case SIOCGHWTSTAMP:
2121 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
2122 break;
2123
2124 case SIOCSHWTSTAMP:
2125 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
2126 break;
2127
2128 default:
2129 ret = -EOPNOTSUPP;
2130 }
2131
2132 return ret;
2133 }
2134
xgbe_change_mtu(struct net_device * netdev,int mtu)2135 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
2136 {
2137 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2138 int ret;
2139
2140 DBGPR("-->xgbe_change_mtu\n");
2141
2142 ret = xgbe_calc_rx_buf_size(netdev, mtu);
2143 if (ret < 0)
2144 return ret;
2145
2146 pdata->rx_buf_size = ret;
2147 netdev->mtu = mtu;
2148
2149 xgbe_restart_dev(pdata);
2150
2151 DBGPR("<--xgbe_change_mtu\n");
2152
2153 return 0;
2154 }
2155
xgbe_tx_timeout(struct net_device * netdev)2156 static void xgbe_tx_timeout(struct net_device *netdev)
2157 {
2158 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2159
2160 netdev_warn(netdev, "tx timeout, device restarting\n");
2161 schedule_work(&pdata->restart_work);
2162 }
2163
xgbe_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * s)2164 static void xgbe_get_stats64(struct net_device *netdev,
2165 struct rtnl_link_stats64 *s)
2166 {
2167 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2168 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2169
2170 DBGPR("-->%s\n", __func__);
2171
2172 pdata->hw_if.read_mmc_stats(pdata);
2173
2174 s->rx_packets = pstats->rxframecount_gb;
2175 s->rx_bytes = pstats->rxoctetcount_gb;
2176 s->rx_errors = pstats->rxframecount_gb -
2177 pstats->rxbroadcastframes_g -
2178 pstats->rxmulticastframes_g -
2179 pstats->rxunicastframes_g;
2180 s->multicast = pstats->rxmulticastframes_g;
2181 s->rx_length_errors = pstats->rxlengtherror;
2182 s->rx_crc_errors = pstats->rxcrcerror;
2183 s->rx_fifo_errors = pstats->rxfifooverflow;
2184
2185 s->tx_packets = pstats->txframecount_gb;
2186 s->tx_bytes = pstats->txoctetcount_gb;
2187 s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
2188 s->tx_dropped = netdev->stats.tx_dropped;
2189
2190 DBGPR("<--%s\n", __func__);
2191 }
2192
xgbe_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)2193 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
2194 u16 vid)
2195 {
2196 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2197 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2198
2199 DBGPR("-->%s\n", __func__);
2200
2201 set_bit(vid, pdata->active_vlans);
2202 hw_if->update_vlan_hash_table(pdata);
2203
2204 DBGPR("<--%s\n", __func__);
2205
2206 return 0;
2207 }
2208
xgbe_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)2209 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
2210 u16 vid)
2211 {
2212 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2213 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2214
2215 DBGPR("-->%s\n", __func__);
2216
2217 clear_bit(vid, pdata->active_vlans);
2218 hw_if->update_vlan_hash_table(pdata);
2219
2220 DBGPR("<--%s\n", __func__);
2221
2222 return 0;
2223 }
2224
2225 #ifdef CONFIG_NET_POLL_CONTROLLER
xgbe_poll_controller(struct net_device * netdev)2226 static void xgbe_poll_controller(struct net_device *netdev)
2227 {
2228 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2229 struct xgbe_channel *channel;
2230 unsigned int i;
2231
2232 DBGPR("-->xgbe_poll_controller\n");
2233
2234 if (pdata->per_channel_irq) {
2235 for (i = 0; i < pdata->channel_count; i++) {
2236 channel = pdata->channel[i];
2237 xgbe_dma_isr(channel->dma_irq, channel);
2238 }
2239 } else {
2240 disable_irq(pdata->dev_irq);
2241 xgbe_isr(pdata->dev_irq, pdata);
2242 enable_irq(pdata->dev_irq);
2243 }
2244
2245 DBGPR("<--xgbe_poll_controller\n");
2246 }
2247 #endif /* End CONFIG_NET_POLL_CONTROLLER */
2248
xgbe_setup_tc(struct net_device * netdev,enum tc_setup_type type,void * type_data)2249 static int xgbe_setup_tc(struct net_device *netdev, enum tc_setup_type type,
2250 void *type_data)
2251 {
2252 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2253 struct tc_mqprio_qopt *mqprio = type_data;
2254 u8 tc;
2255
2256 if (type != TC_SETUP_QDISC_MQPRIO)
2257 return -EOPNOTSUPP;
2258
2259 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2260 tc = mqprio->num_tc;
2261
2262 if (tc > pdata->hw_feat.tc_cnt)
2263 return -EINVAL;
2264
2265 pdata->num_tcs = tc;
2266 pdata->hw_if.config_tc(pdata);
2267
2268 return 0;
2269 }
2270
xgbe_fix_features(struct net_device * netdev,netdev_features_t features)2271 static netdev_features_t xgbe_fix_features(struct net_device *netdev,
2272 netdev_features_t features)
2273 {
2274 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2275 netdev_features_t vxlan_base, vxlan_mask;
2276
2277 vxlan_base = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RX_UDP_TUNNEL_PORT;
2278 vxlan_mask = vxlan_base | NETIF_F_GSO_UDP_TUNNEL_CSUM;
2279
2280 pdata->vxlan_features = features & vxlan_mask;
2281
2282 /* Only fix VXLAN-related features */
2283 if (!pdata->vxlan_features)
2284 return features;
2285
2286 /* If VXLAN isn't supported then clear any features:
2287 * This is needed because NETIF_F_RX_UDP_TUNNEL_PORT gets
2288 * automatically set if ndo_udp_tunnel_add is set.
2289 */
2290 if (!pdata->hw_feat.vxn)
2291 return features & ~vxlan_mask;
2292
2293 /* VXLAN CSUM requires VXLAN base */
2294 if ((features & NETIF_F_GSO_UDP_TUNNEL_CSUM) &&
2295 !(features & NETIF_F_GSO_UDP_TUNNEL)) {
2296 netdev_notice(netdev,
2297 "forcing tx udp tunnel support\n");
2298 features |= NETIF_F_GSO_UDP_TUNNEL;
2299 }
2300
2301 /* Can't do one without doing the other */
2302 if ((features & vxlan_base) != vxlan_base) {
2303 netdev_notice(netdev,
2304 "forcing both tx and rx udp tunnel support\n");
2305 features |= vxlan_base;
2306 }
2307
2308 if (features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
2309 if (!(features & NETIF_F_GSO_UDP_TUNNEL_CSUM)) {
2310 netdev_notice(netdev,
2311 "forcing tx udp tunnel checksumming on\n");
2312 features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
2313 }
2314 } else {
2315 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) {
2316 netdev_notice(netdev,
2317 "forcing tx udp tunnel checksumming off\n");
2318 features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
2319 }
2320 }
2321
2322 pdata->vxlan_features = features & vxlan_mask;
2323
2324 /* Adjust UDP Tunnel based on current state */
2325 if (pdata->vxlan_force_disable) {
2326 netdev_notice(netdev,
2327 "VXLAN acceleration disabled, turning off udp tunnel features\n");
2328 features &= ~vxlan_mask;
2329 }
2330
2331 return features;
2332 }
2333
xgbe_set_features(struct net_device * netdev,netdev_features_t features)2334 static int xgbe_set_features(struct net_device *netdev,
2335 netdev_features_t features)
2336 {
2337 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2338 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2339 netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
2340 netdev_features_t udp_tunnel;
2341 int ret = 0;
2342
2343 rxhash = pdata->netdev_features & NETIF_F_RXHASH;
2344 rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
2345 rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
2346 rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
2347 udp_tunnel = pdata->netdev_features & NETIF_F_GSO_UDP_TUNNEL;
2348
2349 if ((features & NETIF_F_RXHASH) && !rxhash)
2350 ret = hw_if->enable_rss(pdata);
2351 else if (!(features & NETIF_F_RXHASH) && rxhash)
2352 ret = hw_if->disable_rss(pdata);
2353 if (ret)
2354 return ret;
2355
2356 if ((features & NETIF_F_RXCSUM) && !rxcsum)
2357 hw_if->enable_rx_csum(pdata);
2358 else if (!(features & NETIF_F_RXCSUM) && rxcsum)
2359 hw_if->disable_rx_csum(pdata);
2360
2361 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
2362 hw_if->enable_rx_vlan_stripping(pdata);
2363 else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
2364 hw_if->disable_rx_vlan_stripping(pdata);
2365
2366 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
2367 hw_if->enable_rx_vlan_filtering(pdata);
2368 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
2369 hw_if->disable_rx_vlan_filtering(pdata);
2370
2371 if ((features & NETIF_F_GSO_UDP_TUNNEL) && !udp_tunnel)
2372 xgbe_enable_vxlan_accel(pdata);
2373 else if (!(features & NETIF_F_GSO_UDP_TUNNEL) && udp_tunnel)
2374 xgbe_disable_vxlan_accel(pdata);
2375
2376 pdata->netdev_features = features;
2377
2378 DBGPR("<--xgbe_set_features\n");
2379
2380 return 0;
2381 }
2382
xgbe_udp_tunnel_add(struct net_device * netdev,struct udp_tunnel_info * ti)2383 static void xgbe_udp_tunnel_add(struct net_device *netdev,
2384 struct udp_tunnel_info *ti)
2385 {
2386 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2387 struct xgbe_vxlan_data *vdata;
2388
2389 if (!pdata->hw_feat.vxn)
2390 return;
2391
2392 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2393 return;
2394
2395 pdata->vxlan_port_count++;
2396
2397 netif_dbg(pdata, drv, netdev,
2398 "adding VXLAN tunnel, family=%hx/port=%hx\n",
2399 ti->sa_family, be16_to_cpu(ti->port));
2400
2401 if (pdata->vxlan_force_disable)
2402 return;
2403
2404 vdata = kzalloc(sizeof(*vdata), GFP_ATOMIC);
2405 if (!vdata) {
2406 /* Can no longer properly track VXLAN ports */
2407 pdata->vxlan_force_disable = 1;
2408 netif_dbg(pdata, drv, netdev,
2409 "internal error, disabling VXLAN accelerations\n");
2410
2411 xgbe_disable_vxlan_accel(pdata);
2412
2413 return;
2414 }
2415 vdata->sa_family = ti->sa_family;
2416 vdata->port = ti->port;
2417
2418 list_add_tail(&vdata->list, &pdata->vxlan_ports);
2419
2420 /* First port added? */
2421 if (pdata->vxlan_port_count == 1) {
2422 xgbe_enable_vxlan_accel(pdata);
2423
2424 return;
2425 }
2426 }
2427
xgbe_udp_tunnel_del(struct net_device * netdev,struct udp_tunnel_info * ti)2428 static void xgbe_udp_tunnel_del(struct net_device *netdev,
2429 struct udp_tunnel_info *ti)
2430 {
2431 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2432 struct xgbe_vxlan_data *vdata;
2433
2434 if (!pdata->hw_feat.vxn)
2435 return;
2436
2437 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2438 return;
2439
2440 netif_dbg(pdata, drv, netdev,
2441 "deleting VXLAN tunnel, family=%hx/port=%hx\n",
2442 ti->sa_family, be16_to_cpu(ti->port));
2443
2444 /* Don't need safe version since loop terminates with deletion */
2445 list_for_each_entry(vdata, &pdata->vxlan_ports, list) {
2446 if (vdata->sa_family != ti->sa_family)
2447 continue;
2448
2449 if (vdata->port != ti->port)
2450 continue;
2451
2452 list_del(&vdata->list);
2453 kfree(vdata);
2454
2455 break;
2456 }
2457
2458 pdata->vxlan_port_count--;
2459 if (!pdata->vxlan_port_count) {
2460 xgbe_reset_vxlan_accel(pdata);
2461
2462 return;
2463 }
2464
2465 if (pdata->vxlan_force_disable)
2466 return;
2467
2468 /* See if VXLAN tunnel id needs to be changed */
2469 vdata = list_first_entry(&pdata->vxlan_ports,
2470 struct xgbe_vxlan_data, list);
2471 if (pdata->vxlan_port == be16_to_cpu(vdata->port))
2472 return;
2473
2474 pdata->vxlan_port = be16_to_cpu(vdata->port);
2475 pdata->hw_if.set_vxlan_id(pdata);
2476 }
2477
xgbe_features_check(struct sk_buff * skb,struct net_device * netdev,netdev_features_t features)2478 static netdev_features_t xgbe_features_check(struct sk_buff *skb,
2479 struct net_device *netdev,
2480 netdev_features_t features)
2481 {
2482 features = vlan_features_check(skb, features);
2483 features = vxlan_features_check(skb, features);
2484
2485 return features;
2486 }
2487
2488 static const struct net_device_ops xgbe_netdev_ops = {
2489 .ndo_open = xgbe_open,
2490 .ndo_stop = xgbe_close,
2491 .ndo_start_xmit = xgbe_xmit,
2492 .ndo_set_rx_mode = xgbe_set_rx_mode,
2493 .ndo_set_mac_address = xgbe_set_mac_address,
2494 .ndo_validate_addr = eth_validate_addr,
2495 .ndo_do_ioctl = xgbe_ioctl,
2496 .ndo_change_mtu = xgbe_change_mtu,
2497 .ndo_tx_timeout = xgbe_tx_timeout,
2498 .ndo_get_stats64 = xgbe_get_stats64,
2499 .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid,
2500 .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid,
2501 #ifdef CONFIG_NET_POLL_CONTROLLER
2502 .ndo_poll_controller = xgbe_poll_controller,
2503 #endif
2504 .ndo_setup_tc = xgbe_setup_tc,
2505 .ndo_fix_features = xgbe_fix_features,
2506 .ndo_set_features = xgbe_set_features,
2507 .ndo_udp_tunnel_add = xgbe_udp_tunnel_add,
2508 .ndo_udp_tunnel_del = xgbe_udp_tunnel_del,
2509 .ndo_features_check = xgbe_features_check,
2510 };
2511
xgbe_get_netdev_ops(void)2512 const struct net_device_ops *xgbe_get_netdev_ops(void)
2513 {
2514 return &xgbe_netdev_ops;
2515 }
2516
xgbe_rx_refresh(struct xgbe_channel * channel)2517 static void xgbe_rx_refresh(struct xgbe_channel *channel)
2518 {
2519 struct xgbe_prv_data *pdata = channel->pdata;
2520 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2521 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2522 struct xgbe_ring *ring = channel->rx_ring;
2523 struct xgbe_ring_data *rdata;
2524
2525 while (ring->dirty != ring->cur) {
2526 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2527
2528 /* Reset rdata values */
2529 desc_if->unmap_rdata(pdata, rdata);
2530
2531 if (desc_if->map_rx_buffer(pdata, ring, rdata))
2532 break;
2533
2534 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
2535
2536 ring->dirty++;
2537 }
2538
2539 /* Make sure everything is written before the register write */
2540 wmb();
2541
2542 /* Update the Rx Tail Pointer Register with address of
2543 * the last cleaned entry */
2544 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
2545 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
2546 lower_32_bits(rdata->rdesc_dma));
2547 }
2548
xgbe_create_skb(struct xgbe_prv_data * pdata,struct napi_struct * napi,struct xgbe_ring_data * rdata,unsigned int len)2549 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
2550 struct napi_struct *napi,
2551 struct xgbe_ring_data *rdata,
2552 unsigned int len)
2553 {
2554 struct sk_buff *skb;
2555 u8 *packet;
2556
2557 skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
2558 if (!skb)
2559 return NULL;
2560
2561 /* Pull in the header buffer which may contain just the header
2562 * or the header plus data
2563 */
2564 dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
2565 rdata->rx.hdr.dma_off,
2566 rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
2567
2568 packet = page_address(rdata->rx.hdr.pa.pages) +
2569 rdata->rx.hdr.pa.pages_offset;
2570 skb_copy_to_linear_data(skb, packet, len);
2571 skb_put(skb, len);
2572
2573 return skb;
2574 }
2575
xgbe_rx_buf1_len(struct xgbe_ring_data * rdata,struct xgbe_packet_data * packet)2576 static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata,
2577 struct xgbe_packet_data *packet)
2578 {
2579 /* Always zero if not the first descriptor */
2580 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST))
2581 return 0;
2582
2583 /* First descriptor with split header, return header length */
2584 if (rdata->rx.hdr_len)
2585 return rdata->rx.hdr_len;
2586
2587 /* First descriptor but not the last descriptor and no split header,
2588 * so the full buffer was used
2589 */
2590 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2591 return rdata->rx.hdr.dma_len;
2592
2593 /* First descriptor and last descriptor and no split header, so
2594 * calculate how much of the buffer was used
2595 */
2596 return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len);
2597 }
2598
xgbe_rx_buf2_len(struct xgbe_ring_data * rdata,struct xgbe_packet_data * packet,unsigned int len)2599 static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata,
2600 struct xgbe_packet_data *packet,
2601 unsigned int len)
2602 {
2603 /* Always the full buffer if not the last descriptor */
2604 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2605 return rdata->rx.buf.dma_len;
2606
2607 /* Last descriptor so calculate how much of the buffer was used
2608 * for the last bit of data
2609 */
2610 return rdata->rx.len - len;
2611 }
2612
xgbe_tx_poll(struct xgbe_channel * channel)2613 static int xgbe_tx_poll(struct xgbe_channel *channel)
2614 {
2615 struct xgbe_prv_data *pdata = channel->pdata;
2616 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2617 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2618 struct xgbe_ring *ring = channel->tx_ring;
2619 struct xgbe_ring_data *rdata;
2620 struct xgbe_ring_desc *rdesc;
2621 struct net_device *netdev = pdata->netdev;
2622 struct netdev_queue *txq;
2623 int processed = 0;
2624 unsigned int tx_packets = 0, tx_bytes = 0;
2625 unsigned int cur;
2626
2627 DBGPR("-->xgbe_tx_poll\n");
2628
2629 /* Nothing to do if there isn't a Tx ring for this channel */
2630 if (!ring)
2631 return 0;
2632
2633 cur = ring->cur;
2634
2635 /* Be sure we get ring->cur before accessing descriptor data */
2636 smp_rmb();
2637
2638 txq = netdev_get_tx_queue(netdev, channel->queue_index);
2639
2640 while ((processed < XGBE_TX_DESC_MAX_PROC) &&
2641 (ring->dirty != cur)) {
2642 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2643 rdesc = rdata->rdesc;
2644
2645 if (!hw_if->tx_complete(rdesc))
2646 break;
2647
2648 /* Make sure descriptor fields are read after reading the OWN
2649 * bit */
2650 dma_rmb();
2651
2652 if (netif_msg_tx_done(pdata))
2653 xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
2654
2655 if (hw_if->is_last_desc(rdesc)) {
2656 tx_packets += rdata->tx.packets;
2657 tx_bytes += rdata->tx.bytes;
2658 }
2659
2660 /* Free the SKB and reset the descriptor for re-use */
2661 desc_if->unmap_rdata(pdata, rdata);
2662 hw_if->tx_desc_reset(rdata);
2663
2664 processed++;
2665 ring->dirty++;
2666 }
2667
2668 if (!processed)
2669 return 0;
2670
2671 netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
2672
2673 if ((ring->tx.queue_stopped == 1) &&
2674 (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
2675 ring->tx.queue_stopped = 0;
2676 netif_tx_wake_queue(txq);
2677 }
2678
2679 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
2680
2681 return processed;
2682 }
2683
xgbe_rx_poll(struct xgbe_channel * channel,int budget)2684 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
2685 {
2686 struct xgbe_prv_data *pdata = channel->pdata;
2687 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2688 struct xgbe_ring *ring = channel->rx_ring;
2689 struct xgbe_ring_data *rdata;
2690 struct xgbe_packet_data *packet;
2691 struct net_device *netdev = pdata->netdev;
2692 struct napi_struct *napi;
2693 struct sk_buff *skb;
2694 struct skb_shared_hwtstamps *hwtstamps;
2695 unsigned int last, error, context_next, context;
2696 unsigned int len, buf1_len, buf2_len, max_len;
2697 unsigned int received = 0;
2698 int packet_count = 0;
2699
2700 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
2701
2702 /* Nothing to do if there isn't a Rx ring for this channel */
2703 if (!ring)
2704 return 0;
2705
2706 last = 0;
2707 context_next = 0;
2708
2709 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
2710
2711 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2712 packet = &ring->packet_data;
2713 while (packet_count < budget) {
2714 DBGPR(" cur = %d\n", ring->cur);
2715
2716 /* First time in loop see if we need to restore state */
2717 if (!received && rdata->state_saved) {
2718 skb = rdata->state.skb;
2719 error = rdata->state.error;
2720 len = rdata->state.len;
2721 } else {
2722 memset(packet, 0, sizeof(*packet));
2723 skb = NULL;
2724 error = 0;
2725 len = 0;
2726 }
2727
2728 read_again:
2729 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2730
2731 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
2732 xgbe_rx_refresh(channel);
2733
2734 if (hw_if->dev_read(channel))
2735 break;
2736
2737 received++;
2738 ring->cur++;
2739
2740 last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2741 LAST);
2742 context_next = XGMAC_GET_BITS(packet->attributes,
2743 RX_PACKET_ATTRIBUTES,
2744 CONTEXT_NEXT);
2745 context = XGMAC_GET_BITS(packet->attributes,
2746 RX_PACKET_ATTRIBUTES,
2747 CONTEXT);
2748
2749 /* Earlier error, just drain the remaining data */
2750 if ((!last || context_next) && error)
2751 goto read_again;
2752
2753 if (error || packet->errors) {
2754 if (packet->errors)
2755 netif_err(pdata, rx_err, netdev,
2756 "error in received packet\n");
2757 dev_kfree_skb(skb);
2758 goto next_packet;
2759 }
2760
2761 if (!context) {
2762 /* Get the data length in the descriptor buffers */
2763 buf1_len = xgbe_rx_buf1_len(rdata, packet);
2764 len += buf1_len;
2765 buf2_len = xgbe_rx_buf2_len(rdata, packet, len);
2766 len += buf2_len;
2767
2768 if (!skb) {
2769 skb = xgbe_create_skb(pdata, napi, rdata,
2770 buf1_len);
2771 if (!skb) {
2772 error = 1;
2773 goto skip_data;
2774 }
2775 }
2776
2777 if (buf2_len) {
2778 dma_sync_single_range_for_cpu(pdata->dev,
2779 rdata->rx.buf.dma_base,
2780 rdata->rx.buf.dma_off,
2781 rdata->rx.buf.dma_len,
2782 DMA_FROM_DEVICE);
2783
2784 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
2785 rdata->rx.buf.pa.pages,
2786 rdata->rx.buf.pa.pages_offset,
2787 buf2_len,
2788 rdata->rx.buf.dma_len);
2789 rdata->rx.buf.pa.pages = NULL;
2790 }
2791 }
2792
2793 skip_data:
2794 if (!last || context_next)
2795 goto read_again;
2796
2797 if (!skb)
2798 goto next_packet;
2799
2800 /* Be sure we don't exceed the configured MTU */
2801 max_len = netdev->mtu + ETH_HLEN;
2802 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2803 (skb->protocol == htons(ETH_P_8021Q)))
2804 max_len += VLAN_HLEN;
2805
2806 if (skb->len > max_len) {
2807 netif_err(pdata, rx_err, netdev,
2808 "packet length exceeds configured MTU\n");
2809 dev_kfree_skb(skb);
2810 goto next_packet;
2811 }
2812
2813 if (netif_msg_pktdata(pdata))
2814 xgbe_print_pkt(netdev, skb, false);
2815
2816 skb_checksum_none_assert(skb);
2817 if (XGMAC_GET_BITS(packet->attributes,
2818 RX_PACKET_ATTRIBUTES, CSUM_DONE))
2819 skb->ip_summed = CHECKSUM_UNNECESSARY;
2820
2821 if (XGMAC_GET_BITS(packet->attributes,
2822 RX_PACKET_ATTRIBUTES, TNP)) {
2823 skb->encapsulation = 1;
2824
2825 if (XGMAC_GET_BITS(packet->attributes,
2826 RX_PACKET_ATTRIBUTES, TNPCSUM_DONE))
2827 skb->csum_level = 1;
2828 }
2829
2830 if (XGMAC_GET_BITS(packet->attributes,
2831 RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2832 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2833 packet->vlan_ctag);
2834
2835 if (XGMAC_GET_BITS(packet->attributes,
2836 RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2837 u64 nsec;
2838
2839 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2840 packet->rx_tstamp);
2841 hwtstamps = skb_hwtstamps(skb);
2842 hwtstamps->hwtstamp = ns_to_ktime(nsec);
2843 }
2844
2845 if (XGMAC_GET_BITS(packet->attributes,
2846 RX_PACKET_ATTRIBUTES, RSS_HASH))
2847 skb_set_hash(skb, packet->rss_hash,
2848 packet->rss_hash_type);
2849
2850 skb->dev = netdev;
2851 skb->protocol = eth_type_trans(skb, netdev);
2852 skb_record_rx_queue(skb, channel->queue_index);
2853
2854 napi_gro_receive(napi, skb);
2855
2856 next_packet:
2857 packet_count++;
2858 }
2859
2860 /* Check if we need to save state before leaving */
2861 if (received && (!last || context_next)) {
2862 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2863 rdata->state_saved = 1;
2864 rdata->state.skb = skb;
2865 rdata->state.len = len;
2866 rdata->state.error = error;
2867 }
2868
2869 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2870
2871 return packet_count;
2872 }
2873
xgbe_one_poll(struct napi_struct * napi,int budget)2874 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2875 {
2876 struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2877 napi);
2878 struct xgbe_prv_data *pdata = channel->pdata;
2879 int processed = 0;
2880
2881 DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2882
2883 /* Cleanup Tx ring first */
2884 xgbe_tx_poll(channel);
2885
2886 /* Process Rx ring next */
2887 processed = xgbe_rx_poll(channel, budget);
2888
2889 /* If we processed everything, we are done */
2890 if ((processed < budget) && napi_complete_done(napi, processed)) {
2891 /* Enable Tx and Rx interrupts */
2892 if (pdata->channel_irq_mode)
2893 xgbe_enable_rx_tx_int(pdata, channel);
2894 else
2895 enable_irq(channel->dma_irq);
2896 }
2897
2898 DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2899
2900 return processed;
2901 }
2902
xgbe_all_poll(struct napi_struct * napi,int budget)2903 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2904 {
2905 struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2906 napi);
2907 struct xgbe_channel *channel;
2908 int ring_budget;
2909 int processed, last_processed;
2910 unsigned int i;
2911
2912 DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2913
2914 processed = 0;
2915 ring_budget = budget / pdata->rx_ring_count;
2916 do {
2917 last_processed = processed;
2918
2919 for (i = 0; i < pdata->channel_count; i++) {
2920 channel = pdata->channel[i];
2921
2922 /* Cleanup Tx ring first */
2923 xgbe_tx_poll(channel);
2924
2925 /* Process Rx ring next */
2926 if (ring_budget > (budget - processed))
2927 ring_budget = budget - processed;
2928 processed += xgbe_rx_poll(channel, ring_budget);
2929 }
2930 } while ((processed < budget) && (processed != last_processed));
2931
2932 /* If we processed everything, we are done */
2933 if ((processed < budget) && napi_complete_done(napi, processed)) {
2934 /* Enable Tx and Rx interrupts */
2935 xgbe_enable_rx_tx_ints(pdata);
2936 }
2937
2938 DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2939
2940 return processed;
2941 }
2942
xgbe_dump_tx_desc(struct xgbe_prv_data * pdata,struct xgbe_ring * ring,unsigned int idx,unsigned int count,unsigned int flag)2943 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2944 unsigned int idx, unsigned int count, unsigned int flag)
2945 {
2946 struct xgbe_ring_data *rdata;
2947 struct xgbe_ring_desc *rdesc;
2948
2949 while (count--) {
2950 rdata = XGBE_GET_DESC_DATA(ring, idx);
2951 rdesc = rdata->rdesc;
2952 netdev_dbg(pdata->netdev,
2953 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2954 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2955 le32_to_cpu(rdesc->desc0),
2956 le32_to_cpu(rdesc->desc1),
2957 le32_to_cpu(rdesc->desc2),
2958 le32_to_cpu(rdesc->desc3));
2959 idx++;
2960 }
2961 }
2962
xgbe_dump_rx_desc(struct xgbe_prv_data * pdata,struct xgbe_ring * ring,unsigned int idx)2963 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2964 unsigned int idx)
2965 {
2966 struct xgbe_ring_data *rdata;
2967 struct xgbe_ring_desc *rdesc;
2968
2969 rdata = XGBE_GET_DESC_DATA(ring, idx);
2970 rdesc = rdata->rdesc;
2971 netdev_dbg(pdata->netdev,
2972 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2973 idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2974 le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2975 }
2976
xgbe_print_pkt(struct net_device * netdev,struct sk_buff * skb,bool tx_rx)2977 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2978 {
2979 struct ethhdr *eth = (struct ethhdr *)skb->data;
2980 unsigned char buffer[128];
2981 unsigned int i;
2982
2983 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2984
2985 netdev_dbg(netdev, "%s packet of %d bytes\n",
2986 (tx_rx ? "TX" : "RX"), skb->len);
2987
2988 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2989 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
2990 netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
2991
2992 for (i = 0; i < skb->len; i += 32) {
2993 unsigned int len = min(skb->len - i, 32U);
2994
2995 hex_dump_to_buffer(&skb->data[i], len, 32, 1,
2996 buffer, sizeof(buffer), false);
2997 netdev_dbg(netdev, " %#06x: %s\n", i, buffer);
2998 }
2999
3000 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
3001 }
3002
