1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DISPLAY_MODE_STRUCTS_H__ 26 #define __DISPLAY_MODE_STRUCTS_H__ 27 28 typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st; 29 typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st; 30 typedef struct _vcs_dpi_ip_params_st ip_params_st; 31 typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st; 32 typedef struct _vcs_dpi_display_output_params_st display_output_params_st; 33 typedef struct _vcs_dpi_display_bandwidth_st display_bandwidth_st; 34 typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st; 35 typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st; 36 typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st; 37 typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st; 38 typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st; 39 typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st; 40 typedef struct _vcs_dpi_dchub_buffer_sizing_st dchub_buffer_sizing_st; 41 typedef struct _vcs_dpi_watermarks_perf_st watermarks_perf_st; 42 typedef struct _vcs_dpi_cstate_pstate_watermarks_st cstate_pstate_watermarks_st; 43 typedef struct _vcs_dpi_wm_calc_pipe_params_st wm_calc_pipe_params_st; 44 typedef struct _vcs_dpi_vratio_pre_st vratio_pre_st; 45 typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st; 46 typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st; 47 typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st; 48 typedef struct _vcs_dpi_display_cur_rq_dlg_params_st display_cur_rq_dlg_params_st; 49 typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st; 50 typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st; 51 typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st; 52 typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st; 53 typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st; 54 typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st; 55 typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st; 56 typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st; 57 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st; 58 typedef struct _vcs_dpi_display_dlg_prefetch_param_st display_dlg_prefetch_param_st; 59 typedef struct _vcs_dpi_display_pipe_clock_st display_pipe_clock_st; 60 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st; 61 62 struct _vcs_dpi_voltage_scaling_st { 63 int state; 64 double dscclk_mhz; 65 double dcfclk_mhz; 66 double socclk_mhz; 67 double dram_speed_mts; 68 double fabricclk_mhz; 69 double dispclk_mhz; 70 double phyclk_mhz; 71 double dppclk_mhz; 72 }; 73 74 struct _vcs_dpi_soc_bounding_box_st { 75 double sr_exit_time_us; 76 double sr_enter_plus_exit_time_us; 77 double urgent_latency_us; 78 double urgent_latency_pixel_data_only_us; 79 double urgent_latency_pixel_mixed_with_vm_data_us; 80 double urgent_latency_vm_data_only_us; 81 double writeback_latency_us; 82 double ideal_dram_bw_after_urgent_percent; 83 double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly 84 double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; 85 double pct_ideal_dram_sdp_bw_after_urgent_vm_only; 86 double max_avg_sdp_bw_use_normal_percent; 87 double max_avg_dram_bw_use_normal_percent; 88 unsigned int max_request_size_bytes; 89 double downspread_percent; 90 double dram_page_open_time_ns; 91 double dram_rw_turnaround_time_ns; 92 double dram_return_buffer_per_channel_bytes; 93 double dram_channel_width_bytes; 94 double fabric_datapath_to_dcn_data_return_bytes; 95 double dcn_downspread_percent; 96 double dispclk_dppclk_vco_speed_mhz; 97 double dfs_vco_period_ps; 98 unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes; 99 unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; 100 unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes; 101 unsigned int round_trip_ping_latency_dcfclk_cycles; 102 unsigned int urgent_out_of_order_return_per_channel_bytes; 103 unsigned int channel_interleave_bytes; 104 unsigned int num_banks; 105 unsigned int num_chans; 106 unsigned int vmm_page_size_bytes; 107 double dram_clock_change_latency_us; 108 double writeback_dram_clock_change_latency_us; 109 unsigned int return_bus_width_bytes; 110 unsigned int voltage_override; 111 double xfc_bus_transport_time_us; 112 double xfc_xbuf_latency_tolerance_us; 113 int use_urgent_burst_bw; 114 double max_hscl_ratio; 115 double max_vscl_ratio; 116 struct _vcs_dpi_voltage_scaling_st clock_limits[7]; 117 }; 118 119 struct _vcs_dpi_ip_params_st { 120 bool gpuvm_enable; 121 bool hostvm_enable; 122 unsigned int gpuvm_max_page_table_levels; 123 unsigned int hostvm_max_page_table_levels; 124 unsigned int hostvm_cached_page_table_levels; 125 unsigned int pte_group_size_bytes; 126 unsigned int max_inter_dcn_tile_repeaters; 127 unsigned int num_dsc; 128 unsigned int odm_capable; 129 unsigned int rob_buffer_size_kbytes; 130 unsigned int det_buffer_size_kbytes; 131 unsigned int dpte_buffer_size_in_pte_reqs; 132 unsigned int pde_proc_buffer_size_64k_reqs; 133 unsigned int dpp_output_buffer_pixels; 134 unsigned int opp_output_buffer_lines; 135 unsigned int pixel_chunk_size_kbytes; 136 unsigned char pte_enable; 137 unsigned int pte_chunk_size_kbytes; 138 unsigned int meta_chunk_size_kbytes; 139 unsigned int writeback_chunk_size_kbytes; 140 unsigned int line_buffer_size_bits; 141 unsigned int max_line_buffer_lines; 142 unsigned int writeback_luma_buffer_size_kbytes; 143 unsigned int writeback_chroma_buffer_size_kbytes; 144 unsigned int writeback_chroma_line_buffer_width_pixels; 145 unsigned int max_page_table_levels; 146 unsigned int max_num_dpp; 147 unsigned int max_num_otg; 148 unsigned int cursor_chunk_size; 149 unsigned int cursor_buffer_size; 150 unsigned int max_num_wb; 151 unsigned int max_dchub_pscl_bw_pix_per_clk; 152 unsigned int max_pscl_lb_bw_pix_per_clk; 153 unsigned int max_lb_vscl_bw_pix_per_clk; 154 unsigned int max_vscl_hscl_bw_pix_per_clk; 155 double max_hscl_ratio; 156 double max_vscl_ratio; 157 unsigned int hscl_mults; 158 unsigned int vscl_mults; 159 unsigned int max_hscl_taps; 160 unsigned int max_vscl_taps; 161 unsigned int xfc_supported; 162 unsigned int xfc_fill_constant_bytes; 163 double dispclk_ramp_margin_percent; 164 double xfc_fill_bw_overhead_percent; 165 double underscan_factor; 166 unsigned int min_vblank_lines; 167 unsigned int dppclk_delay_subtotal; 168 unsigned int dispclk_delay_subtotal; 169 unsigned int dcfclk_cstate_latency; 170 unsigned int dppclk_delay_scl; 171 unsigned int dppclk_delay_scl_lb_only; 172 unsigned int dppclk_delay_cnvc_formatter; 173 unsigned int dppclk_delay_cnvc_cursor; 174 unsigned int is_line_buffer_bpp_fixed; 175 unsigned int line_buffer_fixed_bpp; 176 unsigned int dcc_supported; 177 178 unsigned int IsLineBufferBppFixed; 179 unsigned int LineBufferFixedBpp; 180 unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 181 unsigned int bug_forcing_LC_req_same_size_fixed; 182 }; 183 184 struct _vcs_dpi_display_xfc_params_st { 185 double xfc_tslv_vready_offset_us; 186 double xfc_tslv_vupdate_width_us; 187 double xfc_tslv_vupdate_offset_us; 188 int xfc_slv_chunk_size_bytes; 189 }; 190 191 struct _vcs_dpi_display_pipe_source_params_st { 192 int source_format; 193 unsigned char dcc; 194 unsigned int dcc_override; 195 unsigned int dcc_rate; 196 unsigned char dcc_use_global; 197 unsigned char vm; 198 bool gpuvm; // gpuvm enabled 199 bool hostvm; // hostvm enabled 200 bool gpuvm_levels_force_en; 201 unsigned int gpuvm_levels_force; 202 bool hostvm_levels_force_en; 203 unsigned int hostvm_levels_force; 204 int source_scan; 205 int sw_mode; 206 int macro_tile_size; 207 unsigned char is_display_sw; 208 unsigned int viewport_width; 209 unsigned int viewport_height; 210 unsigned int viewport_y_y; 211 unsigned int viewport_y_c; 212 unsigned int viewport_width_c; 213 unsigned int viewport_height_c; 214 unsigned int data_pitch; 215 unsigned int data_pitch_c; 216 unsigned int meta_pitch; 217 unsigned int meta_pitch_c; 218 unsigned int cur0_src_width; 219 int cur0_bpp; 220 unsigned int cur1_src_width; 221 int cur1_bpp; 222 int num_cursors; 223 unsigned char is_hsplit; 224 unsigned char dynamic_metadata_enable; 225 unsigned int dynamic_metadata_lines_before_active; 226 unsigned int dynamic_metadata_xmit_bytes; 227 unsigned int hsplit_grp; 228 unsigned char xfc_enable; 229 unsigned char xfc_slave; 230 struct _vcs_dpi_display_xfc_params_st xfc_params; 231 }; 232 struct writeback_st { 233 int wb_src_height; 234 int wb_dst_width; 235 int wb_dst_height; 236 int wb_pixel_format; 237 int wb_htaps_luma; 238 int wb_vtaps_luma; 239 int wb_htaps_chroma; 240 int wb_vtaps_chroma; 241 double wb_hratio; 242 double wb_vratio; 243 }; 244 245 struct _vcs_dpi_display_output_params_st { 246 int dp_lanes; 247 int output_bpp; 248 int dsc_enable; 249 int wb_enable; 250 int num_active_wb; 251 int output_bpc; 252 int output_type; 253 int output_format; 254 int output_standard; 255 int dsc_slices; 256 struct writeback_st wb; 257 }; 258 259 struct _vcs_dpi_display_bandwidth_st { 260 double total_bw_consumed_gbps; 261 double guaranteed_urgent_return_bw_gbps; 262 }; 263 264 struct _vcs_dpi_scaler_ratio_depth_st { 265 double hscl_ratio; 266 double vscl_ratio; 267 double hscl_ratio_c; 268 double vscl_ratio_c; 269 double vinit; 270 double vinit_c; 271 double vinit_bot; 272 double vinit_bot_c; 273 int lb_depth; 274 int scl_enable; 275 }; 276 277 struct _vcs_dpi_scaler_taps_st { 278 unsigned int htaps; 279 unsigned int vtaps; 280 unsigned int htaps_c; 281 unsigned int vtaps_c; 282 }; 283 284 struct _vcs_dpi_display_pipe_dest_params_st { 285 unsigned int recout_width; 286 unsigned int recout_height; 287 unsigned int full_recout_width; 288 unsigned int full_recout_height; 289 unsigned int hblank_start; 290 unsigned int hblank_end; 291 unsigned int vblank_start; 292 unsigned int vblank_end; 293 unsigned int htotal; 294 unsigned int vtotal; 295 unsigned int vactive; 296 unsigned int hactive; 297 unsigned int vstartup_start; 298 unsigned int vupdate_offset; 299 unsigned int vupdate_width; 300 unsigned int vready_offset; 301 unsigned char interlaced; 302 unsigned char underscan; 303 double pixel_rate_mhz; 304 unsigned char synchronized_vblank_all_planes; 305 unsigned char otg_inst; 306 unsigned char odm_split_cnt; 307 unsigned char odm_combine; 308 unsigned char use_maximum_vstartup; 309 }; 310 311 struct _vcs_dpi_display_pipe_params_st { 312 display_pipe_source_params_st src; 313 display_pipe_dest_params_st dest; 314 scaler_ratio_depth_st scale_ratio_depth; 315 scaler_taps_st scale_taps; 316 }; 317 318 struct _vcs_dpi_display_clocks_and_cfg_st { 319 int voltage; 320 double dppclk_mhz; 321 double refclk_mhz; 322 double dispclk_mhz; 323 double dcfclk_mhz; 324 double socclk_mhz; 325 }; 326 327 struct _vcs_dpi_display_e2e_pipe_params_st { 328 display_pipe_params_st pipe; 329 display_output_params_st dout; 330 display_clocks_and_cfg_st clks_cfg; 331 }; 332 333 struct _vcs_dpi_dchub_buffer_sizing_st { 334 unsigned int swath_width_y; 335 unsigned int swath_height_y; 336 unsigned int swath_height_c; 337 unsigned int detail_buffer_size_y; 338 }; 339 340 struct _vcs_dpi_watermarks_perf_st { 341 double stutter_eff_in_active_region_percent; 342 double urgent_latency_supported_us; 343 double non_urgent_latency_supported_us; 344 double dram_clock_change_margin_us; 345 double dram_access_eff_percent; 346 }; 347 348 struct _vcs_dpi_cstate_pstate_watermarks_st { 349 double cstate_exit_us; 350 double cstate_enter_plus_exit_us; 351 double pstate_change_us; 352 }; 353 354 struct _vcs_dpi_wm_calc_pipe_params_st { 355 unsigned int num_dpp; 356 int voltage; 357 int output_type; 358 double dcfclk_mhz; 359 double socclk_mhz; 360 double dppclk_mhz; 361 double pixclk_mhz; 362 unsigned char interlace_en; 363 unsigned char pte_enable; 364 unsigned char dcc_enable; 365 double dcc_rate; 366 double bytes_per_pixel_c; 367 double bytes_per_pixel_y; 368 unsigned int swath_width_y; 369 unsigned int swath_height_y; 370 unsigned int swath_height_c; 371 unsigned int det_buffer_size_y; 372 double h_ratio; 373 double v_ratio; 374 unsigned int h_taps; 375 unsigned int h_total; 376 unsigned int v_total; 377 unsigned int v_active; 378 unsigned int e2e_index; 379 double display_pipe_line_delivery_time; 380 double read_bw; 381 unsigned int lines_in_det_y; 382 unsigned int lines_in_det_y_rounded_down_to_swath; 383 double full_det_buffering_time; 384 double dcfclk_deepsleep_mhz_per_plane; 385 }; 386 387 struct _vcs_dpi_vratio_pre_st { 388 double vratio_pre_l; 389 double vratio_pre_c; 390 }; 391 392 struct _vcs_dpi_display_data_rq_misc_params_st { 393 unsigned int full_swath_bytes; 394 unsigned int stored_swath_bytes; 395 unsigned int blk256_height; 396 unsigned int blk256_width; 397 unsigned int req_height; 398 unsigned int req_width; 399 }; 400 401 struct _vcs_dpi_display_data_rq_sizing_params_st { 402 unsigned int chunk_bytes; 403 unsigned int min_chunk_bytes; 404 unsigned int meta_chunk_bytes; 405 unsigned int min_meta_chunk_bytes; 406 unsigned int mpte_group_bytes; 407 unsigned int dpte_group_bytes; 408 }; 409 410 struct _vcs_dpi_display_data_rq_dlg_params_st { 411 unsigned int swath_width_ub; 412 unsigned int swath_height; 413 unsigned int req_per_swath_ub; 414 unsigned int meta_pte_bytes_per_frame_ub; 415 unsigned int dpte_req_per_row_ub; 416 unsigned int dpte_groups_per_row_ub; 417 unsigned int dpte_row_height; 418 unsigned int dpte_bytes_per_row_ub; 419 unsigned int meta_chunks_per_row_ub; 420 unsigned int meta_req_per_row_ub; 421 unsigned int meta_row_height; 422 unsigned int meta_bytes_per_row_ub; 423 }; 424 425 struct _vcs_dpi_display_cur_rq_dlg_params_st { 426 unsigned char enable; 427 unsigned int swath_height; 428 unsigned int req_per_line; 429 }; 430 431 struct _vcs_dpi_display_rq_dlg_params_st { 432 display_data_rq_dlg_params_st rq_l; 433 display_data_rq_dlg_params_st rq_c; 434 display_cur_rq_dlg_params_st rq_cur0; 435 }; 436 437 struct _vcs_dpi_display_rq_sizing_params_st { 438 display_data_rq_sizing_params_st rq_l; 439 display_data_rq_sizing_params_st rq_c; 440 }; 441 442 struct _vcs_dpi_display_rq_misc_params_st { 443 display_data_rq_misc_params_st rq_l; 444 display_data_rq_misc_params_st rq_c; 445 }; 446 447 struct _vcs_dpi_display_rq_params_st { 448 unsigned char yuv420; 449 unsigned char yuv420_10bpc; 450 display_rq_misc_params_st misc; 451 display_rq_sizing_params_st sizing; 452 display_rq_dlg_params_st dlg; 453 }; 454 455 struct _vcs_dpi_display_dlg_regs_st { 456 unsigned int refcyc_h_blank_end; 457 unsigned int dlg_vblank_end; 458 unsigned int min_dst_y_next_start; 459 unsigned int refcyc_per_htotal; 460 unsigned int refcyc_x_after_scaler; 461 unsigned int dst_y_after_scaler; 462 unsigned int dst_y_prefetch; 463 unsigned int dst_y_per_vm_vblank; 464 unsigned int dst_y_per_row_vblank; 465 unsigned int dst_y_per_vm_flip; 466 unsigned int dst_y_per_row_flip; 467 unsigned int ref_freq_to_pix_freq; 468 unsigned int vratio_prefetch; 469 unsigned int vratio_prefetch_c; 470 unsigned int refcyc_per_pte_group_vblank_l; 471 unsigned int refcyc_per_pte_group_vblank_c; 472 unsigned int refcyc_per_meta_chunk_vblank_l; 473 unsigned int refcyc_per_meta_chunk_vblank_c; 474 unsigned int refcyc_per_pte_group_flip_l; 475 unsigned int refcyc_per_pte_group_flip_c; 476 unsigned int refcyc_per_meta_chunk_flip_l; 477 unsigned int refcyc_per_meta_chunk_flip_c; 478 unsigned int dst_y_per_pte_row_nom_l; 479 unsigned int dst_y_per_pte_row_nom_c; 480 unsigned int refcyc_per_pte_group_nom_l; 481 unsigned int refcyc_per_pte_group_nom_c; 482 unsigned int dst_y_per_meta_row_nom_l; 483 unsigned int dst_y_per_meta_row_nom_c; 484 unsigned int refcyc_per_meta_chunk_nom_l; 485 unsigned int refcyc_per_meta_chunk_nom_c; 486 unsigned int refcyc_per_line_delivery_pre_l; 487 unsigned int refcyc_per_line_delivery_pre_c; 488 unsigned int refcyc_per_line_delivery_l; 489 unsigned int refcyc_per_line_delivery_c; 490 unsigned int chunk_hdl_adjust_cur0; 491 unsigned int chunk_hdl_adjust_cur1; 492 unsigned int vready_after_vcount0; 493 unsigned int dst_y_offset_cur0; 494 unsigned int dst_y_offset_cur1; 495 unsigned int xfc_reg_transfer_delay; 496 unsigned int xfc_reg_precharge_delay; 497 unsigned int xfc_reg_remote_surface_flip_latency; 498 unsigned int xfc_reg_prefetch_margin; 499 unsigned int dst_y_delta_drq_limit; 500 }; 501 502 struct _vcs_dpi_display_ttu_regs_st { 503 unsigned int qos_level_low_wm; 504 unsigned int qos_level_high_wm; 505 unsigned int min_ttu_vblank; 506 unsigned int qos_level_flip; 507 unsigned int refcyc_per_req_delivery_l; 508 unsigned int refcyc_per_req_delivery_c; 509 unsigned int refcyc_per_req_delivery_cur0; 510 unsigned int refcyc_per_req_delivery_cur1; 511 unsigned int refcyc_per_req_delivery_pre_l; 512 unsigned int refcyc_per_req_delivery_pre_c; 513 unsigned int refcyc_per_req_delivery_pre_cur0; 514 unsigned int refcyc_per_req_delivery_pre_cur1; 515 unsigned int qos_level_fixed_l; 516 unsigned int qos_level_fixed_c; 517 unsigned int qos_level_fixed_cur0; 518 unsigned int qos_level_fixed_cur1; 519 unsigned int qos_ramp_disable_l; 520 unsigned int qos_ramp_disable_c; 521 unsigned int qos_ramp_disable_cur0; 522 unsigned int qos_ramp_disable_cur1; 523 }; 524 525 struct _vcs_dpi_display_data_rq_regs_st { 526 unsigned int chunk_size; 527 unsigned int min_chunk_size; 528 unsigned int meta_chunk_size; 529 unsigned int min_meta_chunk_size; 530 unsigned int dpte_group_size; 531 unsigned int mpte_group_size; 532 unsigned int swath_height; 533 unsigned int pte_row_height_linear; 534 }; 535 536 struct _vcs_dpi_display_rq_regs_st { 537 display_data_rq_regs_st rq_regs_l; 538 display_data_rq_regs_st rq_regs_c; 539 unsigned int drq_expansion_mode; 540 unsigned int prq_expansion_mode; 541 unsigned int mrq_expansion_mode; 542 unsigned int crq_expansion_mode; 543 unsigned int plane1_base_address; 544 }; 545 546 struct _vcs_dpi_display_dlg_sys_params_st { 547 double t_mclk_wm_us; 548 double t_urg_wm_us; 549 double t_sr_wm_us; 550 double t_extra_us; 551 double mem_trip_us; 552 double t_srx_delay_us; 553 double deepsleep_dcfclk_mhz; 554 double total_flip_bw; 555 unsigned int total_flip_bytes; 556 }; 557 558 struct _vcs_dpi_display_dlg_prefetch_param_st { 559 double prefetch_bw; 560 unsigned int flip_bytes; 561 }; 562 563 struct _vcs_dpi_display_pipe_clock_st { 564 double dcfclk_mhz; 565 double dispclk_mhz; 566 double socclk_mhz; 567 double dscclk_mhz[6]; 568 double dppclk_mhz[6]; 569 }; 570 571 struct _vcs_dpi_display_arb_params_st { 572 int max_req_outstanding; 573 int min_req_outstanding; 574 int sat_level_us; 575 }; 576 577 #endif /*__DISPLAY_MODE_STRUCTS_H__*/ 578
