1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Realtek PCI-Express card reader
4 *
5 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
6 *
7 * Author:
8 * Wei WANG (wei_wang@realsil.com.cn)
9 * Micky Ching (micky_ching@realsil.com.cn)
10 */
11
12 #include <linux/blkdev.h>
13 #include <linux/kthread.h>
14 #include <linux/sched.h>
15 #include <linux/vmalloc.h>
16
17 #include "rtsx.h"
18 #include "rtsx_transport.h"
19 #include "rtsx_scsi.h"
20 #include "rtsx_card.h"
21 #include "xd.h"
22
23 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no);
24 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff,
25 u8 start_page, u8 end_page);
26
xd_set_err_code(struct rtsx_chip * chip,u8 err_code)27 static inline void xd_set_err_code(struct rtsx_chip *chip, u8 err_code)
28 {
29 struct xd_info *xd_card = &chip->xd_card;
30
31 xd_card->err_code = err_code;
32 }
33
xd_check_err_code(struct rtsx_chip * chip,u8 err_code)34 static inline int xd_check_err_code(struct rtsx_chip *chip, u8 err_code)
35 {
36 struct xd_info *xd_card = &chip->xd_card;
37
38 return (xd_card->err_code == err_code);
39 }
40
xd_set_init_para(struct rtsx_chip * chip)41 static int xd_set_init_para(struct rtsx_chip *chip)
42 {
43 struct xd_info *xd_card = &chip->xd_card;
44 int retval;
45
46 if (chip->asic_code)
47 xd_card->xd_clock = 47;
48 else
49 xd_card->xd_clock = CLK_50;
50
51 retval = switch_clock(chip, xd_card->xd_clock);
52 if (retval != STATUS_SUCCESS)
53 return STATUS_FAIL;
54
55 return STATUS_SUCCESS;
56 }
57
xd_switch_clock(struct rtsx_chip * chip)58 static int xd_switch_clock(struct rtsx_chip *chip)
59 {
60 struct xd_info *xd_card = &chip->xd_card;
61 int retval;
62
63 retval = select_card(chip, XD_CARD);
64 if (retval != STATUS_SUCCESS)
65 return STATUS_FAIL;
66
67 retval = switch_clock(chip, xd_card->xd_clock);
68 if (retval != STATUS_SUCCESS)
69 return STATUS_FAIL;
70
71 return STATUS_SUCCESS;
72 }
73
xd_read_id(struct rtsx_chip * chip,u8 id_cmd,u8 * id_buf,u8 buf_len)74 static int xd_read_id(struct rtsx_chip *chip, u8 id_cmd, u8 *id_buf, u8 buf_len)
75 {
76 int retval, i;
77 u8 *ptr;
78
79 rtsx_init_cmd(chip);
80
81 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd);
82 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
83 XD_TRANSFER_START | XD_READ_ID);
84 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
85 XD_TRANSFER_END);
86
87 for (i = 0; i < 4; i++)
88 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0);
89
90 retval = rtsx_send_cmd(chip, XD_CARD, 20);
91 if (retval < 0)
92 return STATUS_FAIL;
93
94 ptr = rtsx_get_cmd_data(chip) + 1;
95 if (id_buf && buf_len) {
96 if (buf_len > 4)
97 buf_len = 4;
98 memcpy(id_buf, ptr, buf_len);
99 }
100
101 return STATUS_SUCCESS;
102 }
103
xd_assign_phy_addr(struct rtsx_chip * chip,u32 addr,u8 mode)104 static void xd_assign_phy_addr(struct rtsx_chip *chip, u32 addr, u8 mode)
105 {
106 struct xd_info *xd_card = &chip->xd_card;
107
108 switch (mode) {
109 case XD_RW_ADDR:
110 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0);
111 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr);
112 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2,
113 0xFF, (u8)(addr >> 8));
114 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3,
115 0xFF, (u8)(addr >> 16));
116 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
117 xd_card->addr_cycle |
118 XD_CALC_ECC |
119 XD_BA_NO_TRANSFORM);
120 break;
121
122 case XD_ERASE_ADDR:
123 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr);
124 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1,
125 0xFF, (u8)(addr >> 8));
126 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2,
127 0xFF, (u8)(addr >> 16));
128 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
129 (xd_card->addr_cycle - 1) | XD_CALC_ECC |
130 XD_BA_NO_TRANSFORM);
131 break;
132
133 default:
134 break;
135 }
136 }
137
xd_read_redundant(struct rtsx_chip * chip,u32 page_addr,u8 * buf,int buf_len)138 static int xd_read_redundant(struct rtsx_chip *chip, u32 page_addr,
139 u8 *buf, int buf_len)
140 {
141 int retval, i;
142
143 rtsx_init_cmd(chip);
144
145 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
146
147 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
148 0xFF, XD_TRANSFER_START | XD_READ_REDUNDANT);
149 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
150 XD_TRANSFER_END, XD_TRANSFER_END);
151
152 for (i = 0; i < 6; i++)
153 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i),
154 0, 0);
155 for (i = 0; i < 4; i++)
156 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i),
157 0, 0);
158 rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0);
159
160 retval = rtsx_send_cmd(chip, XD_CARD, 500);
161 if (retval < 0)
162 return STATUS_FAIL;
163
164 if (buf && buf_len) {
165 u8 *ptr = rtsx_get_cmd_data(chip) + 1;
166
167 if (buf_len > 11)
168 buf_len = 11;
169 memcpy(buf, ptr, buf_len);
170 }
171
172 return STATUS_SUCCESS;
173 }
174
xd_read_data_from_ppb(struct rtsx_chip * chip,int offset,u8 * buf,int buf_len)175 static int xd_read_data_from_ppb(struct rtsx_chip *chip, int offset,
176 u8 *buf, int buf_len)
177 {
178 int retval, i;
179
180 if (!buf || (buf_len < 0))
181 return STATUS_FAIL;
182
183 rtsx_init_cmd(chip);
184
185 for (i = 0; i < buf_len; i++)
186 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i,
187 0, 0);
188
189 retval = rtsx_send_cmd(chip, 0, 250);
190 if (retval < 0) {
191 rtsx_clear_xd_error(chip);
192 return STATUS_FAIL;
193 }
194
195 memcpy(buf, rtsx_get_cmd_data(chip), buf_len);
196
197 return STATUS_SUCCESS;
198 }
199
xd_read_cis(struct rtsx_chip * chip,u32 page_addr,u8 * buf,int buf_len)200 static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf,
201 int buf_len)
202 {
203 int retval;
204 u8 reg;
205
206 if (!buf || (buf_len < 10))
207 return STATUS_FAIL;
208
209 rtsx_init_cmd(chip);
210
211 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
212
213 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
214 0x01, PINGPONG_BUFFER);
215 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
216 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
217 XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
218
219 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
220 XD_TRANSFER_START | XD_READ_PAGES);
221 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
222 XD_TRANSFER_END);
223
224 retval = rtsx_send_cmd(chip, XD_CARD, 250);
225 if (retval == -ETIMEDOUT) {
226 rtsx_clear_xd_error(chip);
227 return STATUS_FAIL;
228 }
229
230 retval = rtsx_read_register(chip, XD_PAGE_STATUS, ®);
231 if (retval)
232 return retval;
233 if (reg != XD_GPG) {
234 rtsx_clear_xd_error(chip);
235 return STATUS_FAIL;
236 }
237
238 retval = rtsx_read_register(chip, XD_CTL, ®);
239 if (retval)
240 return retval;
241 if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) {
242 retval = xd_read_data_from_ppb(chip, 0, buf, buf_len);
243 if (retval != STATUS_SUCCESS)
244 return STATUS_FAIL;
245 if (reg & XD_ECC1_ERROR) {
246 u8 ecc_bit, ecc_byte;
247
248 retval = rtsx_read_register(chip, XD_ECC_BIT1,
249 &ecc_bit);
250 if (retval)
251 return retval;
252 retval = rtsx_read_register(chip, XD_ECC_BYTE1,
253 &ecc_byte);
254 if (retval)
255 return retval;
256
257 dev_dbg(rtsx_dev(chip), "ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n",
258 ecc_bit, ecc_byte);
259 if (ecc_byte < buf_len) {
260 dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n",
261 buf[ecc_byte]);
262 buf[ecc_byte] ^= (1 << ecc_bit);
263 dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n",
264 buf[ecc_byte]);
265 }
266 }
267 } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) {
268 rtsx_clear_xd_error(chip);
269
270 retval = xd_read_data_from_ppb(chip, 256, buf, buf_len);
271 if (retval != STATUS_SUCCESS)
272 return STATUS_FAIL;
273 if (reg & XD_ECC2_ERROR) {
274 u8 ecc_bit, ecc_byte;
275
276 retval = rtsx_read_register(chip, XD_ECC_BIT2,
277 &ecc_bit);
278 if (retval)
279 return retval;
280 retval = rtsx_read_register(chip, XD_ECC_BYTE2,
281 &ecc_byte);
282 if (retval)
283 return retval;
284
285 dev_dbg(rtsx_dev(chip), "ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n",
286 ecc_bit, ecc_byte);
287 if (ecc_byte < buf_len) {
288 dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n",
289 buf[ecc_byte]);
290 buf[ecc_byte] ^= (1 << ecc_bit);
291 dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n",
292 buf[ecc_byte]);
293 }
294 }
295 } else {
296 rtsx_clear_xd_error(chip);
297 return STATUS_FAIL;
298 }
299
300 return STATUS_SUCCESS;
301 }
302
xd_fill_pull_ctl_disable(struct rtsx_chip * chip)303 static void xd_fill_pull_ctl_disable(struct rtsx_chip *chip)
304 {
305 if (CHECK_PID(chip, 0x5208)) {
306 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
307 XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
308 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
309 XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
310 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
311 XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
312 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
313 XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD);
314 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
315 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
316 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
317 MS_D5_PD | MS_D4_PD);
318 } else if (CHECK_PID(chip, 0x5288)) {
319 if (CHECK_BARO_PKG(chip, QFN)) {
320 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1,
321 0xFF, 0x55);
322 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2,
323 0xFF, 0x55);
324 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3,
325 0xFF, 0x4B);
326 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4,
327 0xFF, 0x69);
328 }
329 }
330 }
331
xd_fill_pull_ctl_stage1_barossa(struct rtsx_chip * chip)332 static void xd_fill_pull_ctl_stage1_barossa(struct rtsx_chip *chip)
333 {
334 if (CHECK_BARO_PKG(chip, QFN)) {
335 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
336 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
337 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B);
338 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
339 }
340 }
341
xd_fill_pull_ctl_enable(struct rtsx_chip * chip)342 static void xd_fill_pull_ctl_enable(struct rtsx_chip *chip)
343 {
344 if (CHECK_PID(chip, 0x5208)) {
345 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
346 XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
347 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
348 XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
349 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
350 XD_WP_PD | XD_CE_PU | XD_CLE_PD | XD_CD_PU);
351 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
352 XD_RDY_PU | XD_WE_PU | XD_RE_PU | XD_ALE_PD);
353 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
354 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
355 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
356 MS_D5_PD | MS_D4_PD);
357 } else if (CHECK_PID(chip, 0x5288)) {
358 if (CHECK_BARO_PKG(chip, QFN)) {
359 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1,
360 0xFF, 0x55);
361 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2,
362 0xFF, 0x55);
363 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3,
364 0xFF, 0x53);
365 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4,
366 0xFF, 0xA9);
367 }
368 }
369 }
370
xd_pull_ctl_disable(struct rtsx_chip * chip)371 static int xd_pull_ctl_disable(struct rtsx_chip *chip)
372 {
373 int retval;
374
375 if (CHECK_PID(chip, 0x5208)) {
376 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF,
377 XD_D3_PD |
378 XD_D2_PD |
379 XD_D1_PD |
380 XD_D0_PD);
381 if (retval)
382 return retval;
383 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF,
384 XD_D7_PD |
385 XD_D6_PD |
386 XD_D5_PD |
387 XD_D4_PD);
388 if (retval)
389 return retval;
390 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF,
391 XD_WP_PD |
392 XD_CE_PD |
393 XD_CLE_PD |
394 XD_CD_PU);
395 if (retval)
396 return retval;
397 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF,
398 XD_RDY_PD |
399 XD_WE_PD |
400 XD_RE_PD |
401 XD_ALE_PD);
402 if (retval)
403 return retval;
404 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF,
405 MS_INS_PU |
406 SD_WP_PD |
407 SD_CD_PU |
408 SD_CMD_PD);
409 if (retval)
410 return retval;
411 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF,
412 MS_D5_PD | MS_D4_PD);
413 if (retval)
414 return retval;
415 } else if (CHECK_PID(chip, 0x5288)) {
416 if (CHECK_BARO_PKG(chip, QFN)) {
417 retval = rtsx_write_register(chip, CARD_PULL_CTL1,
418 0xFF, 0x55);
419 if (retval)
420 return retval;
421 retval = rtsx_write_register(chip, CARD_PULL_CTL2,
422 0xFF, 0x55);
423 if (retval)
424 return retval;
425 retval = rtsx_write_register(chip, CARD_PULL_CTL3,
426 0xFF, 0x4B);
427 if (retval)
428 return retval;
429 retval = rtsx_write_register(chip, CARD_PULL_CTL4,
430 0xFF, 0x69);
431 if (retval)
432 return retval;
433 }
434 }
435
436 return STATUS_SUCCESS;
437 }
438
reset_xd(struct rtsx_chip * chip)439 static int reset_xd(struct rtsx_chip *chip)
440 {
441 struct xd_info *xd_card = &chip->xd_card;
442 int retval, i, j;
443 u8 *ptr, id_buf[4], redunt[11];
444
445 retval = select_card(chip, XD_CARD);
446 if (retval != STATUS_SUCCESS)
447 return STATUS_FAIL;
448
449 rtsx_init_cmd(chip);
450
451 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF,
452 XD_PGSTS_NOT_FF);
453 if (chip->asic_code) {
454 if (!CHECK_PID(chip, 0x5288))
455 xd_fill_pull_ctl_disable(chip);
456 else
457 xd_fill_pull_ctl_stage1_barossa(chip);
458 } else {
459 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
460 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) |
461 0x20);
462 }
463
464 if (!chip->ft2_fast_mode)
465 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT,
466 XD_NO_AUTO_PWR_OFF, 0);
467
468 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
469
470 retval = rtsx_send_cmd(chip, XD_CARD, 100);
471 if (retval < 0)
472 return STATUS_FAIL;
473
474 if (!chip->ft2_fast_mode) {
475 retval = card_power_off(chip, XD_CARD);
476 if (retval != STATUS_SUCCESS)
477 return STATUS_FAIL;
478
479 wait_timeout(250);
480
481 rtsx_init_cmd(chip);
482
483 if (chip->asic_code) {
484 xd_fill_pull_ctl_enable(chip);
485 } else {
486 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
487 (FPGA_XD_PULL_CTL_EN1 &
488 FPGA_XD_PULL_CTL_EN2) |
489 0x20);
490 }
491
492 retval = rtsx_send_cmd(chip, XD_CARD, 100);
493 if (retval < 0)
494 return STATUS_FAIL;
495
496 retval = card_power_on(chip, XD_CARD);
497 if (retval != STATUS_SUCCESS)
498 return STATUS_FAIL;
499
500 #ifdef SUPPORT_OCP
501 wait_timeout(50);
502 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
503 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
504 chip->ocp_stat);
505 return STATUS_FAIL;
506 }
507 #endif
508 }
509
510 rtsx_init_cmd(chip);
511
512 if (chip->ft2_fast_mode) {
513 if (chip->asic_code) {
514 xd_fill_pull_ctl_enable(chip);
515 } else {
516 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
517 (FPGA_XD_PULL_CTL_EN1 &
518 FPGA_XD_PULL_CTL_EN2) |
519 0x20);
520 }
521 }
522
523 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, XD_OUTPUT_EN);
524 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN);
525
526 retval = rtsx_send_cmd(chip, XD_CARD, 100);
527 if (retval < 0)
528 return STATUS_FAIL;
529
530 if (!chip->ft2_fast_mode)
531 wait_timeout(200);
532
533 retval = xd_set_init_para(chip);
534 if (retval != STATUS_SUCCESS)
535 return STATUS_FAIL;
536
537 /* Read ID to check if the timing setting is right */
538 for (i = 0; i < 4; i++) {
539 rtsx_init_cmd(chip);
540
541 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF,
542 XD_TIME_SETUP_STEP * 3 +
543 XD_TIME_RW_STEP * (2 + i) + XD_TIME_RWN_STEP * i);
544 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF,
545 XD_TIME_SETUP_STEP * 3 +
546 XD_TIME_RW_STEP * (4 + i) +
547 XD_TIME_RWN_STEP * (3 + i));
548
549 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
550 XD_TRANSFER_START | XD_RESET);
551 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
552 XD_TRANSFER_END, XD_TRANSFER_END);
553
554 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
555 rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
556
557 retval = rtsx_send_cmd(chip, XD_CARD, 100);
558 if (retval < 0)
559 return STATUS_FAIL;
560
561 ptr = rtsx_get_cmd_data(chip) + 1;
562
563 dev_dbg(rtsx_dev(chip), "XD_DAT: 0x%x, XD_CTL: 0x%x\n",
564 ptr[0], ptr[1]);
565
566 if (((ptr[0] & READY_FLAG) != READY_STATE) ||
567 !(ptr[1] & XD_RDY))
568 continue;
569
570 retval = xd_read_id(chip, READ_ID, id_buf, 4);
571 if (retval != STATUS_SUCCESS)
572 return STATUS_FAIL;
573
574 dev_dbg(rtsx_dev(chip), "READ_ID: 0x%x 0x%x 0x%x 0x%x\n",
575 id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
576
577 xd_card->device_code = id_buf[1];
578
579 /* Check if the xD card is supported */
580 switch (xd_card->device_code) {
581 case XD_4M_X8_512_1:
582 case XD_4M_X8_512_2:
583 xd_card->block_shift = 4;
584 xd_card->page_off = 0x0F;
585 xd_card->addr_cycle = 3;
586 xd_card->zone_cnt = 1;
587 xd_card->capacity = 8000;
588 XD_SET_4MB(xd_card);
589 break;
590 case XD_8M_X8_512:
591 xd_card->block_shift = 4;
592 xd_card->page_off = 0x0F;
593 xd_card->addr_cycle = 3;
594 xd_card->zone_cnt = 1;
595 xd_card->capacity = 16000;
596 break;
597 case XD_16M_X8_512:
598 XD_PAGE_512(xd_card);
599 xd_card->addr_cycle = 3;
600 xd_card->zone_cnt = 1;
601 xd_card->capacity = 32000;
602 break;
603 case XD_32M_X8_512:
604 XD_PAGE_512(xd_card);
605 xd_card->addr_cycle = 3;
606 xd_card->zone_cnt = 2;
607 xd_card->capacity = 64000;
608 break;
609 case XD_64M_X8_512:
610 XD_PAGE_512(xd_card);
611 xd_card->addr_cycle = 4;
612 xd_card->zone_cnt = 4;
613 xd_card->capacity = 128000;
614 break;
615 case XD_128M_X8_512:
616 XD_PAGE_512(xd_card);
617 xd_card->addr_cycle = 4;
618 xd_card->zone_cnt = 8;
619 xd_card->capacity = 256000;
620 break;
621 case XD_256M_X8_512:
622 XD_PAGE_512(xd_card);
623 xd_card->addr_cycle = 4;
624 xd_card->zone_cnt = 16;
625 xd_card->capacity = 512000;
626 break;
627 case XD_512M_X8:
628 XD_PAGE_512(xd_card);
629 xd_card->addr_cycle = 4;
630 xd_card->zone_cnt = 32;
631 xd_card->capacity = 1024000;
632 break;
633 case xD_1G_X8_512:
634 XD_PAGE_512(xd_card);
635 xd_card->addr_cycle = 4;
636 xd_card->zone_cnt = 64;
637 xd_card->capacity = 2048000;
638 break;
639 case xD_2G_X8_512:
640 XD_PAGE_512(xd_card);
641 xd_card->addr_cycle = 4;
642 xd_card->zone_cnt = 128;
643 xd_card->capacity = 4096000;
644 break;
645 default:
646 continue;
647 }
648
649 /* Confirm timing setting */
650 for (j = 0; j < 10; j++) {
651 retval = xd_read_id(chip, READ_ID, id_buf, 4);
652 if (retval != STATUS_SUCCESS)
653 return STATUS_FAIL;
654
655 if (id_buf[1] != xd_card->device_code)
656 break;
657 }
658
659 if (j == 10)
660 break;
661 }
662
663 if (i == 4) {
664 xd_card->block_shift = 0;
665 xd_card->page_off = 0;
666 xd_card->addr_cycle = 0;
667 xd_card->capacity = 0;
668
669 return STATUS_FAIL;
670 }
671
672 retval = xd_read_id(chip, READ_xD_ID, id_buf, 4);
673 if (retval != STATUS_SUCCESS)
674 return STATUS_FAIL;
675 dev_dbg(rtsx_dev(chip), "READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n",
676 id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
677 if (id_buf[2] != XD_ID_CODE)
678 return STATUS_FAIL;
679
680 /* Search CIS block */
681 for (i = 0; i < 24; i++) {
682 u32 page_addr;
683
684 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS)
685 return STATUS_FAIL;
686
687 page_addr = (u32)i << xd_card->block_shift;
688
689 for (j = 0; j < 3; j++) {
690 retval = xd_read_redundant(chip, page_addr, redunt, 11);
691 if (retval == STATUS_SUCCESS)
692 break;
693 }
694 if (j == 3)
695 continue;
696
697 if (redunt[BLOCK_STATUS] != XD_GBLK)
698 continue;
699
700 j = 0;
701 if (redunt[PAGE_STATUS] != XD_GPG) {
702 for (j = 1; j <= 8; j++) {
703 retval = xd_read_redundant(chip, page_addr + j,
704 redunt, 11);
705 if (retval == STATUS_SUCCESS) {
706 if (redunt[PAGE_STATUS] == XD_GPG)
707 break;
708 }
709 }
710
711 if (j == 9)
712 break;
713 }
714
715 /* Check CIS data */
716 if ((redunt[BLOCK_STATUS] == XD_GBLK) &&
717 (redunt[PARITY] & XD_BA1_ALL0)) {
718 u8 buf[10];
719
720 page_addr += j;
721
722 retval = xd_read_cis(chip, page_addr, buf, 10);
723 if (retval != STATUS_SUCCESS)
724 return STATUS_FAIL;
725
726 if ((buf[0] == 0x01) && (buf[1] == 0x03) &&
727 (buf[2] == 0xD9) &&
728 (buf[3] == 0x01) && (buf[4] == 0xFF) &&
729 (buf[5] == 0x18) && (buf[6] == 0x02) &&
730 (buf[7] == 0xDF) && (buf[8] == 0x01) &&
731 (buf[9] == 0x20)) {
732 xd_card->cis_block = (u16)i;
733 }
734 }
735
736 break;
737 }
738
739 dev_dbg(rtsx_dev(chip), "CIS block: 0x%x\n", xd_card->cis_block);
740 if (xd_card->cis_block == 0xFFFF)
741 return STATUS_FAIL;
742
743 chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity;
744
745 return STATUS_SUCCESS;
746 }
747
xd_check_data_blank(u8 * redunt)748 static int xd_check_data_blank(u8 *redunt)
749 {
750 int i;
751
752 for (i = 0; i < 6; i++) {
753 if (redunt[PAGE_STATUS + i] != 0xFF)
754 return 0;
755 }
756
757 if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1))
758 != (XD_ECC1_ALL1 | XD_ECC2_ALL1))
759 return 0;
760
761 for (i = 0; i < 4; i++) {
762 if (redunt[RESERVED0 + i] != 0xFF)
763 return 0;
764 }
765
766 return 1;
767 }
768
xd_load_log_block_addr(u8 * redunt)769 static u16 xd_load_log_block_addr(u8 *redunt)
770 {
771 u16 addr = 0xFFFF;
772
773 if (redunt[PARITY] & XD_BA1_BA2_EQL)
774 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) |
775 redunt[BLOCK_ADDR1_L];
776 else if (redunt[PARITY] & XD_BA1_VALID)
777 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) |
778 redunt[BLOCK_ADDR1_L];
779 else if (redunt[PARITY] & XD_BA2_VALID)
780 addr = ((u16)redunt[BLOCK_ADDR2_H] << 8) |
781 redunt[BLOCK_ADDR2_L];
782
783 return addr;
784 }
785
xd_init_l2p_tbl(struct rtsx_chip * chip)786 static int xd_init_l2p_tbl(struct rtsx_chip *chip)
787 {
788 struct xd_info *xd_card = &chip->xd_card;
789 int size, i;
790
791 dev_dbg(rtsx_dev(chip), "%s: zone_cnt = %d\n", __func__,
792 xd_card->zone_cnt);
793
794 if (xd_card->zone_cnt < 1)
795 return STATUS_FAIL;
796
797 size = xd_card->zone_cnt * sizeof(struct zone_entry);
798 dev_dbg(rtsx_dev(chip), "Buffer size for l2p table is %d\n", size);
799
800 xd_card->zone = vmalloc(size);
801 if (!xd_card->zone)
802 return STATUS_ERROR;
803
804 for (i = 0; i < xd_card->zone_cnt; i++) {
805 xd_card->zone[i].build_flag = 0;
806 xd_card->zone[i].l2p_table = NULL;
807 xd_card->zone[i].free_table = NULL;
808 xd_card->zone[i].get_index = 0;
809 xd_card->zone[i].set_index = 0;
810 xd_card->zone[i].unused_blk_cnt = 0;
811 }
812
813 return STATUS_SUCCESS;
814 }
815
free_zone(struct zone_entry * zone)816 static inline void free_zone(struct zone_entry *zone)
817 {
818 if (!zone)
819 return;
820
821 zone->build_flag = 0;
822 zone->set_index = 0;
823 zone->get_index = 0;
824 zone->unused_blk_cnt = 0;
825 vfree(zone->l2p_table);
826 zone->l2p_table = NULL;
827 vfree(zone->free_table);
828 zone->free_table = NULL;
829 }
830
xd_set_unused_block(struct rtsx_chip * chip,u32 phy_blk)831 static void xd_set_unused_block(struct rtsx_chip *chip, u32 phy_blk)
832 {
833 struct xd_info *xd_card = &chip->xd_card;
834 struct zone_entry *zone;
835 int zone_no;
836
837 zone_no = (int)phy_blk >> 10;
838 if (zone_no >= xd_card->zone_cnt) {
839 dev_dbg(rtsx_dev(chip), "Set unused block to invalid zone (zone_no = %d, zone_cnt = %d)\n",
840 zone_no, xd_card->zone_cnt);
841 return;
842 }
843 zone = &xd_card->zone[zone_no];
844
845 if (!zone->free_table) {
846 if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS)
847 return;
848 }
849
850 if ((zone->set_index >= XD_FREE_TABLE_CNT) ||
851 (zone->set_index < 0)) {
852 free_zone(zone);
853 dev_dbg(rtsx_dev(chip), "Set unused block fail, invalid set_index\n");
854 return;
855 }
856
857 dev_dbg(rtsx_dev(chip), "Set unused block to index %d\n",
858 zone->set_index);
859
860 zone->free_table[zone->set_index++] = (u16)(phy_blk & 0x3ff);
861 if (zone->set_index >= XD_FREE_TABLE_CNT)
862 zone->set_index = 0;
863 zone->unused_blk_cnt++;
864 }
865
xd_get_unused_block(struct rtsx_chip * chip,int zone_no)866 static u32 xd_get_unused_block(struct rtsx_chip *chip, int zone_no)
867 {
868 struct xd_info *xd_card = &chip->xd_card;
869 struct zone_entry *zone;
870 u32 phy_blk;
871
872 if (zone_no >= xd_card->zone_cnt) {
873 dev_dbg(rtsx_dev(chip), "Get unused block from invalid zone (zone_no = %d, zone_cnt = %d)\n",
874 zone_no, xd_card->zone_cnt);
875 return BLK_NOT_FOUND;
876 }
877 zone = &xd_card->zone[zone_no];
878
879 if ((zone->unused_blk_cnt == 0) ||
880 (zone->set_index == zone->get_index)) {
881 free_zone(zone);
882 dev_dbg(rtsx_dev(chip), "Get unused block fail, no unused block available\n");
883 return BLK_NOT_FOUND;
884 }
885 if ((zone->get_index >= XD_FREE_TABLE_CNT) || (zone->get_index < 0)) {
886 free_zone(zone);
887 dev_dbg(rtsx_dev(chip), "Get unused block fail, invalid get_index\n");
888 return BLK_NOT_FOUND;
889 }
890
891 dev_dbg(rtsx_dev(chip), "Get unused block from index %d\n",
892 zone->get_index);
893
894 phy_blk = zone->free_table[zone->get_index];
895 zone->free_table[zone->get_index++] = 0xFFFF;
896 if (zone->get_index >= XD_FREE_TABLE_CNT)
897 zone->get_index = 0;
898 zone->unused_blk_cnt--;
899
900 phy_blk += ((u32)(zone_no) << 10);
901 return phy_blk;
902 }
903
xd_set_l2p_tbl(struct rtsx_chip * chip,int zone_no,u16 log_off,u16 phy_off)904 static void xd_set_l2p_tbl(struct rtsx_chip *chip,
905 int zone_no, u16 log_off, u16 phy_off)
906 {
907 struct xd_info *xd_card = &chip->xd_card;
908 struct zone_entry *zone;
909
910 zone = &xd_card->zone[zone_no];
911 zone->l2p_table[log_off] = phy_off;
912 }
913
xd_get_l2p_tbl(struct rtsx_chip * chip,int zone_no,u16 log_off)914 static u32 xd_get_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off)
915 {
916 struct xd_info *xd_card = &chip->xd_card;
917 struct zone_entry *zone;
918 int retval;
919
920 zone = &xd_card->zone[zone_no];
921 if (zone->l2p_table[log_off] == 0xFFFF) {
922 u32 phy_blk = 0;
923 int i;
924
925 #ifdef XD_DELAY_WRITE
926 retval = xd_delay_write(chip);
927 if (retval != STATUS_SUCCESS) {
928 dev_dbg(rtsx_dev(chip), "In %s, delay write fail!\n",
929 __func__);
930 return BLK_NOT_FOUND;
931 }
932 #endif
933
934 if (zone->unused_blk_cnt <= 0) {
935 dev_dbg(rtsx_dev(chip), "No unused block!\n");
936 return BLK_NOT_FOUND;
937 }
938
939 for (i = 0; i < zone->unused_blk_cnt; i++) {
940 phy_blk = xd_get_unused_block(chip, zone_no);
941 if (phy_blk == BLK_NOT_FOUND) {
942 dev_dbg(rtsx_dev(chip), "No unused block available!\n");
943 return BLK_NOT_FOUND;
944 }
945
946 retval = xd_init_page(chip, phy_blk, log_off,
947 0, xd_card->page_off + 1);
948 if (retval == STATUS_SUCCESS)
949 break;
950 }
951 if (i >= zone->unused_blk_cnt) {
952 dev_dbg(rtsx_dev(chip), "No good unused block available!\n");
953 return BLK_NOT_FOUND;
954 }
955
956 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(phy_blk & 0x3FF));
957 return phy_blk;
958 }
959
960 return (u32)zone->l2p_table[log_off] + ((u32)(zone_no) << 10);
961 }
962
reset_xd_card(struct rtsx_chip * chip)963 int reset_xd_card(struct rtsx_chip *chip)
964 {
965 struct xd_info *xd_card = &chip->xd_card;
966 int retval;
967
968 memset(xd_card, 0, sizeof(struct xd_info));
969
970 xd_card->block_shift = 0;
971 xd_card->page_off = 0;
972 xd_card->addr_cycle = 0;
973 xd_card->capacity = 0;
974 xd_card->zone_cnt = 0;
975 xd_card->cis_block = 0xFFFF;
976 xd_card->delay_write.delay_write_flag = 0;
977
978 retval = enable_card_clock(chip, XD_CARD);
979 if (retval != STATUS_SUCCESS)
980 return STATUS_FAIL;
981
982 retval = reset_xd(chip);
983 if (retval != STATUS_SUCCESS)
984 return STATUS_FAIL;
985
986 retval = xd_init_l2p_tbl(chip);
987 if (retval != STATUS_SUCCESS)
988 return STATUS_FAIL;
989
990 return STATUS_SUCCESS;
991 }
992
xd_mark_bad_block(struct rtsx_chip * chip,u32 phy_blk)993 static int xd_mark_bad_block(struct rtsx_chip *chip, u32 phy_blk)
994 {
995 struct xd_info *xd_card = &chip->xd_card;
996 int retval;
997 u32 page_addr;
998 u8 reg = 0;
999
1000 dev_dbg(rtsx_dev(chip), "mark block 0x%x as bad block\n", phy_blk);
1001
1002 if (phy_blk == BLK_NOT_FOUND)
1003 return STATUS_FAIL;
1004
1005 rtsx_init_cmd(chip);
1006
1007 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1008 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_LATER_BBLK);
1009 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF);
1010 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF);
1011 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF);
1012 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF);
1013 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF);
1014 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF);
1015 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF);
1016 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF);
1017
1018 page_addr = phy_blk << xd_card->block_shift;
1019
1020 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1021
1022 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF,
1023 xd_card->page_off + 1);
1024
1025 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1026 XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1027 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1028 XD_TRANSFER_END, XD_TRANSFER_END);
1029
1030 retval = rtsx_send_cmd(chip, XD_CARD, 500);
1031 if (retval < 0) {
1032 rtsx_clear_xd_error(chip);
1033 rtsx_read_register(chip, XD_DAT, ®);
1034 if (reg & PROGRAM_ERROR)
1035 xd_set_err_code(chip, XD_PRG_ERROR);
1036 else
1037 xd_set_err_code(chip, XD_TO_ERROR);
1038 return STATUS_FAIL;
1039 }
1040
1041 return STATUS_SUCCESS;
1042 }
1043
xd_init_page(struct rtsx_chip * chip,u32 phy_blk,u16 logoff,u8 start_page,u8 end_page)1044 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk,
1045 u16 logoff, u8 start_page, u8 end_page)
1046 {
1047 struct xd_info *xd_card = &chip->xd_card;
1048 int retval;
1049 u32 page_addr;
1050 u8 reg = 0;
1051
1052 dev_dbg(rtsx_dev(chip), "Init block 0x%x\n", phy_blk);
1053
1054 if (start_page > end_page)
1055 return STATUS_FAIL;
1056 if (phy_blk == BLK_NOT_FOUND)
1057 return STATUS_FAIL;
1058
1059 rtsx_init_cmd(chip);
1060
1061 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF);
1062 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF);
1063 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H,
1064 0xFF, (u8)(logoff >> 8));
1065 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)logoff);
1066
1067 page_addr = (phy_blk << xd_card->block_shift) + start_page;
1068
1069 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1070
1071 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG,
1072 XD_BA_TRANSFORM, XD_BA_TRANSFORM);
1073
1074 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT,
1075 0xFF, (end_page - start_page));
1076
1077 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1078 0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1079 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1080 XD_TRANSFER_END, XD_TRANSFER_END);
1081
1082 retval = rtsx_send_cmd(chip, XD_CARD, 500);
1083 if (retval < 0) {
1084 rtsx_clear_xd_error(chip);
1085 rtsx_read_register(chip, XD_DAT, ®);
1086 if (reg & PROGRAM_ERROR) {
1087 xd_mark_bad_block(chip, phy_blk);
1088 xd_set_err_code(chip, XD_PRG_ERROR);
1089 } else {
1090 xd_set_err_code(chip, XD_TO_ERROR);
1091 }
1092 return STATUS_FAIL;
1093 }
1094
1095 return STATUS_SUCCESS;
1096 }
1097
xd_copy_page(struct rtsx_chip * chip,u32 old_blk,u32 new_blk,u8 start_page,u8 end_page)1098 static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk,
1099 u8 start_page, u8 end_page)
1100 {
1101 struct xd_info *xd_card = &chip->xd_card;
1102 u32 old_page, new_page;
1103 u8 i, reg = 0;
1104 int retval;
1105
1106 dev_dbg(rtsx_dev(chip), "Copy page from block 0x%x to block 0x%x\n",
1107 old_blk, new_blk);
1108
1109 if (start_page > end_page)
1110 return STATUS_FAIL;
1111
1112 if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND))
1113 return STATUS_FAIL;
1114
1115 old_page = (old_blk << xd_card->block_shift) + start_page;
1116 new_page = (new_blk << xd_card->block_shift) + start_page;
1117
1118 XD_CLR_BAD_NEWBLK(xd_card);
1119
1120 retval = rtsx_write_register(chip, CARD_DATA_SOURCE, 0x01,
1121 PINGPONG_BUFFER);
1122 if (retval)
1123 return retval;
1124
1125 for (i = start_page; i < end_page; i++) {
1126 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1127 rtsx_clear_xd_error(chip);
1128 xd_set_err_code(chip, XD_NO_CARD);
1129 return STATUS_FAIL;
1130 }
1131
1132 rtsx_init_cmd(chip);
1133
1134 xd_assign_phy_addr(chip, old_page, XD_RW_ADDR);
1135
1136 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1137 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1138 XD_AUTO_CHK_DATA_STATUS, 0);
1139 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1140 XD_TRANSFER_START | XD_READ_PAGES);
1141 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1142 XD_TRANSFER_END, XD_TRANSFER_END);
1143
1144 retval = rtsx_send_cmd(chip, XD_CARD, 500);
1145 if (retval < 0) {
1146 rtsx_clear_xd_error(chip);
1147 reg = 0;
1148 rtsx_read_register(chip, XD_CTL, ®);
1149 if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) {
1150 mdelay(100);
1151
1152 if (detect_card_cd(chip,
1153 XD_CARD) != STATUS_SUCCESS) {
1154 xd_set_err_code(chip, XD_NO_CARD);
1155 return STATUS_FAIL;
1156 }
1157
1158 if (((reg & XD_ECC1_ERROR) &&
1159 (reg & XD_ECC1_UNCORRECTABLE)) ||
1160 ((reg & XD_ECC2_ERROR) &&
1161 (reg & XD_ECC2_UNCORRECTABLE))) {
1162 rtsx_write_register(chip,
1163 XD_PAGE_STATUS,
1164 0xFF,
1165 XD_BPG);
1166 rtsx_write_register(chip,
1167 XD_BLOCK_STATUS,
1168 0xFF,
1169 XD_GBLK);
1170 XD_SET_BAD_OLDBLK(xd_card);
1171 dev_dbg(rtsx_dev(chip), "old block 0x%x ecc error\n",
1172 old_blk);
1173 }
1174 } else {
1175 xd_set_err_code(chip, XD_TO_ERROR);
1176 return STATUS_FAIL;
1177 }
1178 }
1179
1180 if (XD_CHK_BAD_OLDBLK(xd_card))
1181 rtsx_clear_xd_error(chip);
1182
1183 rtsx_init_cmd(chip);
1184
1185 xd_assign_phy_addr(chip, new_page, XD_RW_ADDR);
1186 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1187 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1188 XD_TRANSFER_START | XD_WRITE_PAGES);
1189 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1190 XD_TRANSFER_END, XD_TRANSFER_END);
1191
1192 retval = rtsx_send_cmd(chip, XD_CARD, 300);
1193 if (retval < 0) {
1194 rtsx_clear_xd_error(chip);
1195 reg = 0;
1196 rtsx_read_register(chip, XD_DAT, ®);
1197 if (reg & PROGRAM_ERROR) {
1198 xd_mark_bad_block(chip, new_blk);
1199 xd_set_err_code(chip, XD_PRG_ERROR);
1200 XD_SET_BAD_NEWBLK(xd_card);
1201 } else {
1202 xd_set_err_code(chip, XD_TO_ERROR);
1203 }
1204 return STATUS_FAIL;
1205 }
1206
1207 old_page++;
1208 new_page++;
1209 }
1210
1211 return STATUS_SUCCESS;
1212 }
1213
xd_reset_cmd(struct rtsx_chip * chip)1214 static int xd_reset_cmd(struct rtsx_chip *chip)
1215 {
1216 int retval;
1217 u8 *ptr;
1218
1219 rtsx_init_cmd(chip);
1220
1221 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1222 0xFF, XD_TRANSFER_START | XD_RESET);
1223 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1224 XD_TRANSFER_END, XD_TRANSFER_END);
1225 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1226 rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
1227
1228 retval = rtsx_send_cmd(chip, XD_CARD, 100);
1229 if (retval < 0)
1230 return STATUS_FAIL;
1231
1232 ptr = rtsx_get_cmd_data(chip) + 1;
1233 if (((ptr[0] & READY_FLAG) == READY_STATE) && (ptr[1] & XD_RDY))
1234 return STATUS_SUCCESS;
1235
1236 return STATUS_FAIL;
1237 }
1238
xd_erase_block(struct rtsx_chip * chip,u32 phy_blk)1239 static int xd_erase_block(struct rtsx_chip *chip, u32 phy_blk)
1240 {
1241 struct xd_info *xd_card = &chip->xd_card;
1242 u32 page_addr;
1243 u8 reg = 0, *ptr;
1244 int i, retval;
1245
1246 if (phy_blk == BLK_NOT_FOUND)
1247 return STATUS_FAIL;
1248
1249 page_addr = phy_blk << xd_card->block_shift;
1250
1251 for (i = 0; i < 3; i++) {
1252 rtsx_init_cmd(chip);
1253
1254 xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR);
1255
1256 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1257 XD_TRANSFER_START | XD_ERASE);
1258 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1259 XD_TRANSFER_END, XD_TRANSFER_END);
1260 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1261
1262 retval = rtsx_send_cmd(chip, XD_CARD, 250);
1263 if (retval < 0) {
1264 rtsx_clear_xd_error(chip);
1265 rtsx_read_register(chip, XD_DAT, ®);
1266 if (reg & PROGRAM_ERROR) {
1267 xd_mark_bad_block(chip, phy_blk);
1268 xd_set_err_code(chip, XD_PRG_ERROR);
1269 return STATUS_FAIL;
1270 }
1271 xd_set_err_code(chip, XD_ERASE_FAIL);
1272 retval = xd_reset_cmd(chip);
1273 if (retval != STATUS_SUCCESS)
1274 return STATUS_FAIL;
1275 continue;
1276 }
1277
1278 ptr = rtsx_get_cmd_data(chip) + 1;
1279 if (*ptr & PROGRAM_ERROR) {
1280 xd_mark_bad_block(chip, phy_blk);
1281 xd_set_err_code(chip, XD_PRG_ERROR);
1282 return STATUS_FAIL;
1283 }
1284
1285 return STATUS_SUCCESS;
1286 }
1287
1288 xd_mark_bad_block(chip, phy_blk);
1289 xd_set_err_code(chip, XD_ERASE_FAIL);
1290 return STATUS_FAIL;
1291 }
1292
xd_build_l2p_tbl(struct rtsx_chip * chip,int zone_no)1293 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no)
1294 {
1295 struct xd_info *xd_card = &chip->xd_card;
1296 struct zone_entry *zone;
1297 int retval;
1298 u32 start, end, i;
1299 u16 max_logoff, cur_fst_page_logoff;
1300 u16 cur_lst_page_logoff, ent_lst_page_logoff;
1301 u8 redunt[11];
1302
1303 dev_dbg(rtsx_dev(chip), "%s: %d\n", __func__, zone_no);
1304
1305 if (!xd_card->zone) {
1306 retval = xd_init_l2p_tbl(chip);
1307 if (retval != STATUS_SUCCESS)
1308 return retval;
1309 }
1310
1311 if (xd_card->zone[zone_no].build_flag) {
1312 dev_dbg(rtsx_dev(chip), "l2p table of zone %d has been built\n",
1313 zone_no);
1314 return STATUS_SUCCESS;
1315 }
1316
1317 zone = &xd_card->zone[zone_no];
1318
1319 if (!zone->l2p_table) {
1320 zone->l2p_table = vmalloc(2000);
1321 if (!zone->l2p_table)
1322 goto build_fail;
1323 }
1324 memset((u8 *)(zone->l2p_table), 0xff, 2000);
1325
1326 if (!zone->free_table) {
1327 zone->free_table = vmalloc(XD_FREE_TABLE_CNT * 2);
1328 if (!zone->free_table)
1329 goto build_fail;
1330 }
1331 memset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2);
1332
1333 if (zone_no == 0) {
1334 if (xd_card->cis_block == 0xFFFF)
1335 start = 0;
1336 else
1337 start = xd_card->cis_block + 1;
1338 if (XD_CHK_4MB(xd_card)) {
1339 end = 0x200;
1340 max_logoff = 499;
1341 } else {
1342 end = 0x400;
1343 max_logoff = 999;
1344 }
1345 } else {
1346 start = (u32)(zone_no) << 10;
1347 end = (u32)(zone_no + 1) << 10;
1348 max_logoff = 999;
1349 }
1350
1351 dev_dbg(rtsx_dev(chip), "start block 0x%x, end block 0x%x\n",
1352 start, end);
1353
1354 zone->set_index = 0;
1355 zone->get_index = 0;
1356 zone->unused_blk_cnt = 0;
1357
1358 for (i = start; i < end; i++) {
1359 u32 page_addr = i << xd_card->block_shift;
1360 u32 phy_block;
1361
1362 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1363 if (retval != STATUS_SUCCESS)
1364 continue;
1365
1366 if (redunt[BLOCK_STATUS] != 0xFF) {
1367 dev_dbg(rtsx_dev(chip), "bad block\n");
1368 continue;
1369 }
1370
1371 if (xd_check_data_blank(redunt)) {
1372 dev_dbg(rtsx_dev(chip), "blank block\n");
1373 xd_set_unused_block(chip, i);
1374 continue;
1375 }
1376
1377 cur_fst_page_logoff = xd_load_log_block_addr(redunt);
1378 if ((cur_fst_page_logoff == 0xFFFF) ||
1379 (cur_fst_page_logoff > max_logoff)) {
1380 retval = xd_erase_block(chip, i);
1381 if (retval == STATUS_SUCCESS)
1382 xd_set_unused_block(chip, i);
1383 continue;
1384 }
1385
1386 if ((zone_no == 0) && (cur_fst_page_logoff == 0) &&
1387 (redunt[PAGE_STATUS] != XD_GPG))
1388 XD_SET_MBR_FAIL(xd_card);
1389
1390 if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) {
1391 zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF);
1392 continue;
1393 }
1394
1395 phy_block = zone->l2p_table[cur_fst_page_logoff] +
1396 ((u32)((zone_no) << 10));
1397
1398 page_addr = ((i + 1) << xd_card->block_shift) - 1;
1399
1400 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1401 if (retval != STATUS_SUCCESS)
1402 continue;
1403
1404 cur_lst_page_logoff = xd_load_log_block_addr(redunt);
1405 if (cur_lst_page_logoff == cur_fst_page_logoff) {
1406 int m;
1407
1408 page_addr = ((phy_block + 1) <<
1409 xd_card->block_shift) - 1;
1410
1411 for (m = 0; m < 3; m++) {
1412 retval = xd_read_redundant(chip, page_addr,
1413 redunt, 11);
1414 if (retval == STATUS_SUCCESS)
1415 break;
1416 }
1417
1418 if (m == 3) {
1419 zone->l2p_table[cur_fst_page_logoff] =
1420 (u16)(i & 0x3FF);
1421 retval = xd_erase_block(chip, phy_block);
1422 if (retval == STATUS_SUCCESS)
1423 xd_set_unused_block(chip, phy_block);
1424 continue;
1425 }
1426
1427 ent_lst_page_logoff = xd_load_log_block_addr(redunt);
1428 if (ent_lst_page_logoff != cur_fst_page_logoff) {
1429 zone->l2p_table[cur_fst_page_logoff] =
1430 (u16)(i & 0x3FF);
1431 retval = xd_erase_block(chip, phy_block);
1432 if (retval == STATUS_SUCCESS)
1433 xd_set_unused_block(chip, phy_block);
1434 continue;
1435 } else {
1436 retval = xd_erase_block(chip, i);
1437 if (retval == STATUS_SUCCESS)
1438 xd_set_unused_block(chip, i);
1439 }
1440 } else {
1441 retval = xd_erase_block(chip, i);
1442 if (retval == STATUS_SUCCESS)
1443 xd_set_unused_block(chip, i);
1444 }
1445 }
1446
1447 if (XD_CHK_4MB(xd_card))
1448 end = 500;
1449 else
1450 end = 1000;
1451
1452 i = 0;
1453 for (start = 0; start < end; start++) {
1454 if (zone->l2p_table[start] == 0xFFFF)
1455 i++;
1456 }
1457
1458 dev_dbg(rtsx_dev(chip), "Block count %d, invalid L2P entry %d\n",
1459 end, i);
1460 dev_dbg(rtsx_dev(chip), "Total unused block: %d\n",
1461 zone->unused_blk_cnt);
1462
1463 if ((zone->unused_blk_cnt - i) < 1)
1464 chip->card_wp |= XD_CARD;
1465
1466 zone->build_flag = 1;
1467
1468 return STATUS_SUCCESS;
1469
1470 build_fail:
1471 vfree(zone->l2p_table);
1472 zone->l2p_table = NULL;
1473 vfree(zone->free_table);
1474 zone->free_table = NULL;
1475
1476 return STATUS_FAIL;
1477 }
1478
xd_send_cmd(struct rtsx_chip * chip,u8 cmd)1479 static int xd_send_cmd(struct rtsx_chip *chip, u8 cmd)
1480 {
1481 int retval;
1482
1483 rtsx_init_cmd(chip);
1484
1485 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd);
1486 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1487 XD_TRANSFER_START | XD_SET_CMD);
1488 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1489 XD_TRANSFER_END, XD_TRANSFER_END);
1490
1491 retval = rtsx_send_cmd(chip, XD_CARD, 200);
1492 if (retval < 0)
1493 return STATUS_FAIL;
1494
1495 return STATUS_SUCCESS;
1496 }
1497
xd_read_multiple_pages(struct rtsx_chip * chip,u32 phy_blk,u32 log_blk,u8 start_page,u8 end_page,u8 * buf,unsigned int * index,unsigned int * offset)1498 static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk,
1499 u32 log_blk, u8 start_page, u8 end_page,
1500 u8 *buf, unsigned int *index,
1501 unsigned int *offset)
1502 {
1503 struct xd_info *xd_card = &chip->xd_card;
1504 u32 page_addr, new_blk;
1505 u16 log_off;
1506 u8 reg_val, page_cnt;
1507 int zone_no, retval, i;
1508
1509 if (start_page > end_page)
1510 goto status_fail;
1511
1512 page_cnt = end_page - start_page;
1513 zone_no = (int)(log_blk / 1000);
1514 log_off = (u16)(log_blk % 1000);
1515
1516 if ((phy_blk & 0x3FF) == 0x3FF) {
1517 for (i = 0; i < 256; i++) {
1518 page_addr = ((u32)i) << xd_card->block_shift;
1519
1520 retval = xd_read_redundant(chip, page_addr, NULL, 0);
1521 if (retval == STATUS_SUCCESS)
1522 break;
1523
1524 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1525 xd_set_err_code(chip, XD_NO_CARD);
1526 goto status_fail;
1527 }
1528 }
1529 }
1530
1531 page_addr = (phy_blk << xd_card->block_shift) + start_page;
1532
1533 rtsx_init_cmd(chip);
1534
1535 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1536 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE, XD_PPB_TO_SIE);
1537 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1538 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1539 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1540 XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
1541
1542 trans_dma_enable(chip->srb->sc_data_direction, chip,
1543 page_cnt * 512, DMA_512);
1544
1545 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1546 XD_TRANSFER_START | XD_READ_PAGES);
1547 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1548 XD_TRANSFER_END | XD_PPB_EMPTY,
1549 XD_TRANSFER_END | XD_PPB_EMPTY);
1550
1551 rtsx_send_cmd_no_wait(chip);
1552
1553 retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512,
1554 scsi_sg_count(chip->srb),
1555 index, offset, DMA_FROM_DEVICE,
1556 chip->xd_timeout);
1557 if (retval < 0) {
1558 rtsx_clear_xd_error(chip);
1559
1560 if (retval == -ETIMEDOUT) {
1561 xd_set_err_code(chip, XD_TO_ERROR);
1562 goto status_fail;
1563 } else {
1564 goto fail;
1565 }
1566 }
1567
1568 return STATUS_SUCCESS;
1569
1570 fail:
1571 retval = rtsx_read_register(chip, XD_PAGE_STATUS, ®_val);
1572 if (retval)
1573 return retval;
1574
1575 if (reg_val != XD_GPG)
1576 xd_set_err_code(chip, XD_PRG_ERROR);
1577
1578 retval = rtsx_read_register(chip, XD_CTL, ®_val);
1579 if (retval)
1580 return retval;
1581
1582 if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ==
1583 (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ||
1584 ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) ==
1585 (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1586 wait_timeout(100);
1587
1588 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1589 xd_set_err_code(chip, XD_NO_CARD);
1590 goto status_fail;
1591 }
1592
1593 xd_set_err_code(chip, XD_ECC_ERROR);
1594
1595 new_blk = xd_get_unused_block(chip, zone_no);
1596 if (new_blk == NO_NEW_BLK) {
1597 XD_CLR_BAD_OLDBLK(xd_card);
1598 goto status_fail;
1599 }
1600
1601 retval = xd_copy_page(chip, phy_blk, new_blk, 0,
1602 xd_card->page_off + 1);
1603 if (retval != STATUS_SUCCESS) {
1604 if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1605 retval = xd_erase_block(chip, new_blk);
1606 if (retval == STATUS_SUCCESS)
1607 xd_set_unused_block(chip, new_blk);
1608 } else {
1609 XD_CLR_BAD_NEWBLK(xd_card);
1610 }
1611 XD_CLR_BAD_OLDBLK(xd_card);
1612 goto status_fail;
1613 }
1614 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1615 xd_erase_block(chip, phy_blk);
1616 xd_mark_bad_block(chip, phy_blk);
1617 XD_CLR_BAD_OLDBLK(xd_card);
1618 }
1619
1620 status_fail:
1621 return STATUS_FAIL;
1622 }
1623
xd_finish_write(struct rtsx_chip * chip,u32 old_blk,u32 new_blk,u32 log_blk,u8 page_off)1624 static int xd_finish_write(struct rtsx_chip *chip,
1625 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1626 {
1627 struct xd_info *xd_card = &chip->xd_card;
1628 int retval, zone_no;
1629 u16 log_off;
1630
1631 dev_dbg(rtsx_dev(chip), "%s ", __func__);
1632 dev_dbg(rtsx_dev(chip), "old_blk = 0x%x, ", old_blk);
1633 dev_dbg(rtsx_dev(chip), "new_blk = 0x%x, ", new_blk);
1634 dev_dbg(rtsx_dev(chip), "log_blk = 0x%x\n", log_blk);
1635
1636 if (page_off > xd_card->page_off)
1637 return STATUS_FAIL;
1638
1639 zone_no = (int)(log_blk / 1000);
1640 log_off = (u16)(log_blk % 1000);
1641
1642 if (old_blk == BLK_NOT_FOUND) {
1643 retval = xd_init_page(chip, new_blk, log_off,
1644 page_off, xd_card->page_off + 1);
1645 if (retval != STATUS_SUCCESS) {
1646 retval = xd_erase_block(chip, new_blk);
1647 if (retval == STATUS_SUCCESS)
1648 xd_set_unused_block(chip, new_blk);
1649 return STATUS_FAIL;
1650 }
1651 } else {
1652 retval = xd_copy_page(chip, old_blk, new_blk,
1653 page_off, xd_card->page_off + 1);
1654 if (retval != STATUS_SUCCESS) {
1655 if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1656 retval = xd_erase_block(chip, new_blk);
1657 if (retval == STATUS_SUCCESS)
1658 xd_set_unused_block(chip, new_blk);
1659 }
1660 XD_CLR_BAD_NEWBLK(xd_card);
1661 return STATUS_FAIL;
1662 }
1663
1664 retval = xd_erase_block(chip, old_blk);
1665 if (retval == STATUS_SUCCESS) {
1666 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1667 xd_mark_bad_block(chip, old_blk);
1668 XD_CLR_BAD_OLDBLK(xd_card);
1669 } else {
1670 xd_set_unused_block(chip, old_blk);
1671 }
1672 } else {
1673 xd_set_err_code(chip, XD_NO_ERROR);
1674 XD_CLR_BAD_OLDBLK(xd_card);
1675 }
1676 }
1677
1678 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1679
1680 return STATUS_SUCCESS;
1681 }
1682
xd_prepare_write(struct rtsx_chip * chip,u32 old_blk,u32 new_blk,u32 log_blk,u8 page_off)1683 static int xd_prepare_write(struct rtsx_chip *chip,
1684 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1685 {
1686 int retval;
1687
1688 dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x, page_off = %d\n",
1689 __func__, old_blk, new_blk, log_blk, (int)page_off);
1690
1691 if (page_off) {
1692 retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off);
1693 if (retval != STATUS_SUCCESS)
1694 return STATUS_FAIL;
1695 }
1696
1697 return STATUS_SUCCESS;
1698 }
1699
xd_write_multiple_pages(struct rtsx_chip * chip,u32 old_blk,u32 new_blk,u32 log_blk,u8 start_page,u8 end_page,u8 * buf,unsigned int * index,unsigned int * offset)1700 static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk,
1701 u32 new_blk, u32 log_blk, u8 start_page,
1702 u8 end_page, u8 *buf, unsigned int *index,
1703 unsigned int *offset)
1704 {
1705 struct xd_info *xd_card = &chip->xd_card;
1706 u32 page_addr;
1707 int zone_no, retval;
1708 u16 log_off;
1709 u8 page_cnt, reg_val;
1710
1711 dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n",
1712 __func__, old_blk, new_blk, log_blk);
1713
1714 if (start_page > end_page)
1715 goto status_fail;
1716
1717 page_cnt = end_page - start_page;
1718 zone_no = (int)(log_blk / 1000);
1719 log_off = (u16)(log_blk % 1000);
1720
1721 page_addr = (new_blk << xd_card->block_shift) + start_page;
1722
1723 retval = xd_send_cmd(chip, READ1_1);
1724 if (retval != STATUS_SUCCESS)
1725 goto status_fail;
1726
1727 rtsx_init_cmd(chip);
1728
1729 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H,
1730 0xFF, (u8)(log_off >> 8));
1731 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)log_off);
1732 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1733 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1734
1735 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1736
1737 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM,
1738 XD_BA_TRANSFORM);
1739 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1740 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1741
1742 trans_dma_enable(chip->srb->sc_data_direction, chip,
1743 page_cnt * 512, DMA_512);
1744
1745 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1746 0xFF, XD_TRANSFER_START | XD_WRITE_PAGES);
1747 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1748 XD_TRANSFER_END, XD_TRANSFER_END);
1749
1750 rtsx_send_cmd_no_wait(chip);
1751
1752 retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512,
1753 scsi_sg_count(chip->srb),
1754 index, offset, DMA_TO_DEVICE, chip->xd_timeout);
1755 if (retval < 0) {
1756 rtsx_clear_xd_error(chip);
1757
1758 if (retval == -ETIMEDOUT) {
1759 xd_set_err_code(chip, XD_TO_ERROR);
1760 goto status_fail;
1761 } else {
1762 goto fail;
1763 }
1764 }
1765
1766 if (end_page == (xd_card->page_off + 1)) {
1767 xd_card->delay_write.delay_write_flag = 0;
1768
1769 if (old_blk != BLK_NOT_FOUND) {
1770 retval = xd_erase_block(chip, old_blk);
1771 if (retval == STATUS_SUCCESS) {
1772 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1773 xd_mark_bad_block(chip, old_blk);
1774 XD_CLR_BAD_OLDBLK(xd_card);
1775 } else {
1776 xd_set_unused_block(chip, old_blk);
1777 }
1778 } else {
1779 xd_set_err_code(chip, XD_NO_ERROR);
1780 XD_CLR_BAD_OLDBLK(xd_card);
1781 }
1782 }
1783 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1784 }
1785
1786 return STATUS_SUCCESS;
1787
1788 fail:
1789 retval = rtsx_read_register(chip, XD_DAT, ®_val);
1790 if (retval)
1791 return retval;
1792 if (reg_val & PROGRAM_ERROR) {
1793 xd_set_err_code(chip, XD_PRG_ERROR);
1794 xd_mark_bad_block(chip, new_blk);
1795 }
1796
1797 status_fail:
1798 return STATUS_FAIL;
1799 }
1800
1801 #ifdef XD_DELAY_WRITE
xd_delay_write(struct rtsx_chip * chip)1802 int xd_delay_write(struct rtsx_chip *chip)
1803 {
1804 struct xd_info *xd_card = &chip->xd_card;
1805 struct xd_delay_write_tag *delay_write = &xd_card->delay_write;
1806 int retval;
1807
1808 if (delay_write->delay_write_flag) {
1809 dev_dbg(rtsx_dev(chip), "%s\n", __func__);
1810 retval = xd_switch_clock(chip);
1811 if (retval != STATUS_SUCCESS)
1812 return STATUS_FAIL;
1813
1814 delay_write->delay_write_flag = 0;
1815 retval = xd_finish_write(chip,
1816 delay_write->old_phyblock,
1817 delay_write->new_phyblock,
1818 delay_write->logblock,
1819 delay_write->pageoff);
1820 if (retval != STATUS_SUCCESS)
1821 return STATUS_FAIL;
1822 }
1823
1824 return STATUS_SUCCESS;
1825 }
1826 #endif
1827
xd_rw(struct scsi_cmnd * srb,struct rtsx_chip * chip,u32 start_sector,u16 sector_cnt)1828 int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
1829 u32 start_sector, u16 sector_cnt)
1830 {
1831 struct xd_info *xd_card = &chip->xd_card;
1832 unsigned int lun = SCSI_LUN(srb);
1833 #ifdef XD_DELAY_WRITE
1834 struct xd_delay_write_tag *delay_write = &xd_card->delay_write;
1835 #endif
1836 int retval, zone_no;
1837 unsigned int index = 0, offset = 0;
1838 u32 log_blk, old_blk = 0, new_blk = 0;
1839 u16 log_off, total_sec_cnt = sector_cnt;
1840 u8 start_page, end_page = 0, page_cnt;
1841 u8 *ptr;
1842
1843 xd_set_err_code(chip, XD_NO_ERROR);
1844
1845 xd_card->cleanup_counter = 0;
1846
1847 dev_dbg(rtsx_dev(chip), "%s: scsi_sg_count = %d\n", __func__,
1848 scsi_sg_count(srb));
1849
1850 ptr = (u8 *)scsi_sglist(srb);
1851
1852 retval = xd_switch_clock(chip);
1853 if (retval != STATUS_SUCCESS)
1854 return STATUS_FAIL;
1855
1856 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1857 chip->card_fail |= XD_CARD;
1858 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1859 return STATUS_FAIL;
1860 }
1861
1862 log_blk = start_sector >> xd_card->block_shift;
1863 start_page = (u8)start_sector & xd_card->page_off;
1864 zone_no = (int)(log_blk / 1000);
1865 log_off = (u16)(log_blk % 1000);
1866
1867 if (xd_card->zone[zone_no].build_flag == 0) {
1868 retval = xd_build_l2p_tbl(chip, zone_no);
1869 if (retval != STATUS_SUCCESS) {
1870 chip->card_fail |= XD_CARD;
1871 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1872 return STATUS_FAIL;
1873 }
1874 }
1875
1876 if (srb->sc_data_direction == DMA_TO_DEVICE) {
1877 #ifdef XD_DELAY_WRITE
1878 if (delay_write->delay_write_flag &&
1879 (delay_write->logblock == log_blk) &&
1880 (start_page > delay_write->pageoff)) {
1881 delay_write->delay_write_flag = 0;
1882 if (delay_write->old_phyblock != BLK_NOT_FOUND) {
1883 retval = xd_copy_page(chip,
1884 delay_write->old_phyblock,
1885 delay_write->new_phyblock,
1886 delay_write->pageoff,
1887 start_page);
1888 if (retval != STATUS_SUCCESS) {
1889 set_sense_type(chip, lun,
1890 SENSE_TYPE_MEDIA_WRITE_ERR);
1891 return STATUS_FAIL;
1892 }
1893 }
1894 old_blk = delay_write->old_phyblock;
1895 new_blk = delay_write->new_phyblock;
1896 } else if (delay_write->delay_write_flag &&
1897 (delay_write->logblock == log_blk) &&
1898 (start_page == delay_write->pageoff)) {
1899 delay_write->delay_write_flag = 0;
1900 old_blk = delay_write->old_phyblock;
1901 new_blk = delay_write->new_phyblock;
1902 } else {
1903 retval = xd_delay_write(chip);
1904 if (retval != STATUS_SUCCESS) {
1905 set_sense_type(chip, lun,
1906 SENSE_TYPE_MEDIA_WRITE_ERR);
1907 return STATUS_FAIL;
1908 }
1909 #endif
1910 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1911 new_blk = xd_get_unused_block(chip, zone_no);
1912 if ((old_blk == BLK_NOT_FOUND) ||
1913 (new_blk == BLK_NOT_FOUND)) {
1914 set_sense_type(chip, lun,
1915 SENSE_TYPE_MEDIA_WRITE_ERR);
1916 return STATUS_FAIL;
1917 }
1918
1919 retval = xd_prepare_write(chip, old_blk, new_blk,
1920 log_blk, start_page);
1921 if (retval != STATUS_SUCCESS) {
1922 if (detect_card_cd(chip, XD_CARD) !=
1923 STATUS_SUCCESS) {
1924 set_sense_type(chip, lun,
1925 SENSE_TYPE_MEDIA_NOT_PRESENT);
1926 return STATUS_FAIL;
1927 }
1928 set_sense_type(chip, lun,
1929 SENSE_TYPE_MEDIA_WRITE_ERR);
1930 return STATUS_FAIL;
1931 }
1932 #ifdef XD_DELAY_WRITE
1933 }
1934 #endif
1935 } else {
1936 #ifdef XD_DELAY_WRITE
1937 retval = xd_delay_write(chip);
1938 if (retval != STATUS_SUCCESS) {
1939 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1940 set_sense_type(chip, lun,
1941 SENSE_TYPE_MEDIA_NOT_PRESENT);
1942 return STATUS_FAIL;
1943 }
1944 set_sense_type(chip, lun,
1945 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1946 return STATUS_FAIL;
1947 }
1948 #endif
1949
1950 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1951 if (old_blk == BLK_NOT_FOUND) {
1952 set_sense_type(chip, lun,
1953 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1954 return STATUS_FAIL;
1955 }
1956 }
1957
1958 dev_dbg(rtsx_dev(chip), "old_blk = 0x%x\n", old_blk);
1959
1960 while (total_sec_cnt) {
1961 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1962 chip->card_fail |= XD_CARD;
1963 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1964 return STATUS_FAIL;
1965 }
1966
1967 if ((start_page + total_sec_cnt) > (xd_card->page_off + 1))
1968 end_page = xd_card->page_off + 1;
1969 else
1970 end_page = start_page + (u8)total_sec_cnt;
1971
1972 page_cnt = end_page - start_page;
1973 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
1974 retval = xd_read_multiple_pages(chip, old_blk, log_blk,
1975 start_page, end_page,
1976 ptr, &index, &offset);
1977 if (retval != STATUS_SUCCESS) {
1978 set_sense_type(chip, lun,
1979 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1980 return STATUS_FAIL;
1981 }
1982 } else {
1983 retval = xd_write_multiple_pages(chip, old_blk,
1984 new_blk, log_blk,
1985 start_page, end_page,
1986 ptr, &index, &offset);
1987 if (retval != STATUS_SUCCESS) {
1988 set_sense_type(chip, lun,
1989 SENSE_TYPE_MEDIA_WRITE_ERR);
1990 return STATUS_FAIL;
1991 }
1992 }
1993
1994 total_sec_cnt -= page_cnt;
1995 if (scsi_sg_count(srb) == 0)
1996 ptr += page_cnt * 512;
1997
1998 if (total_sec_cnt == 0)
1999 break;
2000
2001 log_blk++;
2002 zone_no = (int)(log_blk / 1000);
2003 log_off = (u16)(log_blk % 1000);
2004
2005 if (xd_card->zone[zone_no].build_flag == 0) {
2006 retval = xd_build_l2p_tbl(chip, zone_no);
2007 if (retval != STATUS_SUCCESS) {
2008 chip->card_fail |= XD_CARD;
2009 set_sense_type(chip, lun,
2010 SENSE_TYPE_MEDIA_NOT_PRESENT);
2011 return STATUS_FAIL;
2012 }
2013 }
2014
2015 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2016 if (old_blk == BLK_NOT_FOUND) {
2017 if (srb->sc_data_direction == DMA_FROM_DEVICE)
2018 set_sense_type(chip, lun,
2019 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2020 else
2021 set_sense_type(chip, lun,
2022 SENSE_TYPE_MEDIA_WRITE_ERR);
2023
2024 return STATUS_FAIL;
2025 }
2026
2027 if (srb->sc_data_direction == DMA_TO_DEVICE) {
2028 new_blk = xd_get_unused_block(chip, zone_no);
2029 if (new_blk == BLK_NOT_FOUND) {
2030 set_sense_type(chip, lun,
2031 SENSE_TYPE_MEDIA_WRITE_ERR);
2032 return STATUS_FAIL;
2033 }
2034 }
2035
2036 start_page = 0;
2037 }
2038
2039 if ((srb->sc_data_direction == DMA_TO_DEVICE) &&
2040 (end_page != (xd_card->page_off + 1))) {
2041 #ifdef XD_DELAY_WRITE
2042 delay_write->delay_write_flag = 1;
2043 delay_write->old_phyblock = old_blk;
2044 delay_write->new_phyblock = new_blk;
2045 delay_write->logblock = log_blk;
2046 delay_write->pageoff = end_page;
2047 #else
2048 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2049 chip->card_fail |= XD_CARD;
2050 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
2051 return STATUS_FAIL;
2052 }
2053
2054 retval = xd_finish_write(chip, old_blk, new_blk,
2055 log_blk, end_page);
2056 if (retval != STATUS_SUCCESS) {
2057 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2058 set_sense_type(chip, lun,
2059 SENSE_TYPE_MEDIA_NOT_PRESENT);
2060 return STATUS_FAIL;
2061 }
2062 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
2063 return STATUS_FAIL;
2064 }
2065 #endif
2066 }
2067
2068 scsi_set_resid(srb, 0);
2069
2070 return STATUS_SUCCESS;
2071 }
2072
xd_free_l2p_tbl(struct rtsx_chip * chip)2073 void xd_free_l2p_tbl(struct rtsx_chip *chip)
2074 {
2075 struct xd_info *xd_card = &chip->xd_card;
2076 int i = 0;
2077
2078 if (xd_card->zone) {
2079 for (i = 0; i < xd_card->zone_cnt; i++) {
2080 vfree(xd_card->zone[i].l2p_table);
2081 xd_card->zone[i].l2p_table = NULL;
2082 vfree(xd_card->zone[i].free_table);
2083 xd_card->zone[i].free_table = NULL;
2084 }
2085 vfree(xd_card->zone);
2086 xd_card->zone = NULL;
2087 }
2088 }
2089
xd_cleanup_work(struct rtsx_chip * chip)2090 void xd_cleanup_work(struct rtsx_chip *chip)
2091 {
2092 #ifdef XD_DELAY_WRITE
2093 struct xd_info *xd_card = &chip->xd_card;
2094
2095 if (xd_card->delay_write.delay_write_flag) {
2096 dev_dbg(rtsx_dev(chip), "xD: delay write\n");
2097 xd_delay_write(chip);
2098 xd_card->cleanup_counter = 0;
2099 }
2100 #endif
2101 }
2102
xd_power_off_card3v3(struct rtsx_chip * chip)2103 int xd_power_off_card3v3(struct rtsx_chip *chip)
2104 {
2105 int retval;
2106
2107 retval = disable_card_clock(chip, XD_CARD);
2108 if (retval != STATUS_SUCCESS)
2109 return STATUS_FAIL;
2110
2111 retval = rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
2112 if (retval)
2113 return retval;
2114
2115 if (!chip->ft2_fast_mode) {
2116 retval = card_power_off(chip, XD_CARD);
2117 if (retval != STATUS_SUCCESS)
2118 return STATUS_FAIL;
2119
2120 wait_timeout(50);
2121 }
2122
2123 if (chip->asic_code) {
2124 retval = xd_pull_ctl_disable(chip);
2125 if (retval != STATUS_SUCCESS)
2126 return STATUS_FAIL;
2127 } else {
2128 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 0xFF, 0xDF);
2129 if (retval)
2130 return retval;
2131 }
2132
2133 return STATUS_SUCCESS;
2134 }
2135
release_xd_card(struct rtsx_chip * chip)2136 int release_xd_card(struct rtsx_chip *chip)
2137 {
2138 struct xd_info *xd_card = &chip->xd_card;
2139 int retval;
2140
2141 chip->card_ready &= ~XD_CARD;
2142 chip->card_fail &= ~XD_CARD;
2143 chip->card_wp &= ~XD_CARD;
2144
2145 xd_card->delay_write.delay_write_flag = 0;
2146
2147 xd_free_l2p_tbl(chip);
2148
2149 retval = xd_power_off_card3v3(chip);
2150 if (retval != STATUS_SUCCESS)
2151 return STATUS_FAIL;
2152
2153 return STATUS_SUCCESS;
2154 }
2155
