1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PROCESSOR_H
3 #define _ASM_X86_PROCESSOR_H
4
5 #include <asm/processor-flags.h>
6
7 /* Forward declaration, a strange C thing */
8 struct task_struct;
9 struct mm_struct;
10 struct io_bitmap;
11 struct vm86;
12
13 #include <asm/math_emu.h>
14 #include <asm/segment.h>
15 #include <asm/types.h>
16 #include <uapi/asm/sigcontext.h>
17 #include <asm/current.h>
18 #include <asm/cpufeatures.h>
19 #include <asm/page.h>
20 #include <asm/pgtable_types.h>
21 #include <asm/percpu.h>
22 #include <asm/msr.h>
23 #include <asm/desc_defs.h>
24 #include <asm/nops.h>
25 #include <asm/special_insns.h>
26 #include <asm/fpu/types.h>
27 #include <asm/unwind_hints.h>
28 #include <asm/vmxfeatures.h>
29 #include <asm/vdso/processor.h>
30
31 #include <linux/personality.h>
32 #include <linux/cache.h>
33 #include <linux/threads.h>
34 #include <linux/math64.h>
35 #include <linux/err.h>
36 #include <linux/irqflags.h>
37 #include <linux/mem_encrypt.h>
38
39 /*
40 * We handle most unaligned accesses in hardware. On the other hand
41 * unaligned DMA can be quite expensive on some Nehalem processors.
42 *
43 * Based on this we disable the IP header alignment in network drivers.
44 */
45 #define NET_IP_ALIGN 0
46
47 #define HBP_NUM 4
48
49 /*
50 * These alignment constraints are for performance in the vSMP case,
51 * but in the task_struct case we must also meet hardware imposed
52 * alignment requirements of the FPU state:
53 */
54 #ifdef CONFIG_X86_VSMP
55 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
56 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
57 #else
58 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
59 # define ARCH_MIN_MMSTRUCT_ALIGN 0
60 #endif
61
62 enum tlb_infos {
63 ENTRIES,
64 NR_INFO
65 };
66
67 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
68 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
69 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
70 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
71 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
72 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
73 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
74
75 /*
76 * CPU type and hardware bug flags. Kept separately for each CPU.
77 * Members of this structure are referenced in head_32.S, so think twice
78 * before touching them. [mj]
79 */
80
81 struct cpuinfo_x86 {
82 __u8 x86; /* CPU family */
83 __u8 x86_vendor; /* CPU vendor */
84 __u8 x86_model;
85 __u8 x86_stepping;
86 #ifdef CONFIG_X86_64
87 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
88 int x86_tlbsize;
89 #endif
90 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
91 __u32 vmx_capability[NVMXINTS];
92 #endif
93 __u8 x86_virt_bits;
94 __u8 x86_phys_bits;
95 /* CPUID returned core id bits: */
96 __u8 x86_coreid_bits;
97 __u8 cu_id;
98 /* Max extended CPUID function supported: */
99 __u32 extended_cpuid_level;
100 /* Maximum supported CPUID level, -1=no CPUID: */
101 int cpuid_level;
102 /*
103 * Align to size of unsigned long because the x86_capability array
104 * is passed to bitops which require the alignment. Use unnamed
105 * union to enforce the array is aligned to size of unsigned long.
106 */
107 union {
108 __u32 x86_capability[NCAPINTS + NBUGINTS];
109 unsigned long x86_capability_alignment;
110 };
111 char x86_vendor_id[16];
112 char x86_model_id[64];
113 /* in KB - valid for CPUS which support this call: */
114 unsigned int x86_cache_size;
115 int x86_cache_alignment; /* In bytes */
116 /* Cache QoS architectural values, valid only on the BSP: */
117 int x86_cache_max_rmid; /* max index */
118 int x86_cache_occ_scale; /* scale to bytes */
119 int x86_cache_mbm_width_offset;
120 int x86_power;
121 unsigned long loops_per_jiffy;
122 /* cpuid returned max cores value: */
123 u16 x86_max_cores;
124 u16 apicid;
125 u16 initial_apicid;
126 u16 x86_clflush_size;
127 /* number of cores as seen by the OS: */
128 u16 booted_cores;
129 /* Physical processor id: */
130 u16 phys_proc_id;
131 /* Logical processor id: */
132 u16 logical_proc_id;
133 /* Core id: */
134 u16 cpu_core_id;
135 u16 cpu_die_id;
136 u16 logical_die_id;
137 /* Index into per_cpu list: */
138 u16 cpu_index;
139 u32 microcode;
140 /* Address space bits used by the cache internally */
141 u8 x86_cache_bits;
142 unsigned initialized : 1;
143 } __randomize_layout;
144
145 struct cpuid_regs {
146 u32 eax, ebx, ecx, edx;
147 };
148
149 enum cpuid_regs_idx {
150 CPUID_EAX = 0,
151 CPUID_EBX,
152 CPUID_ECX,
153 CPUID_EDX,
154 };
155
156 #define X86_VENDOR_INTEL 0
157 #define X86_VENDOR_CYRIX 1
158 #define X86_VENDOR_AMD 2
159 #define X86_VENDOR_UMC 3
160 #define X86_VENDOR_CENTAUR 5
161 #define X86_VENDOR_TRANSMETA 7
162 #define X86_VENDOR_NSC 8
163 #define X86_VENDOR_HYGON 9
164 #define X86_VENDOR_ZHAOXIN 10
165 #define X86_VENDOR_NUM 11
166
167 #define X86_VENDOR_UNKNOWN 0xff
168
169 /*
170 * capabilities of CPUs
171 */
172 extern struct cpuinfo_x86 boot_cpu_data;
173 extern struct cpuinfo_x86 new_cpu_data;
174
175 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
176 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
177
178 #ifdef CONFIG_SMP
179 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
180 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
181 #else
182 #define cpu_info boot_cpu_data
183 #define cpu_data(cpu) boot_cpu_data
184 #endif
185
186 extern const struct seq_operations cpuinfo_op;
187
188 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
189
190 extern void cpu_detect(struct cpuinfo_x86 *c);
191
l1tf_pfn_limit(void)192 static inline unsigned long long l1tf_pfn_limit(void)
193 {
194 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
195 }
196
197 extern void early_cpu_init(void);
198 extern void identify_boot_cpu(void);
199 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
200 extern void print_cpu_info(struct cpuinfo_x86 *);
201 void print_cpu_msr(struct cpuinfo_x86 *);
202
203 #ifdef CONFIG_X86_32
204 extern int have_cpuid_p(void);
205 #else
have_cpuid_p(void)206 static inline int have_cpuid_p(void)
207 {
208 return 1;
209 }
210 #endif
native_cpuid(unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)211 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
212 unsigned int *ecx, unsigned int *edx)
213 {
214 /* ecx is often an input as well as an output. */
215 asm volatile("cpuid"
216 : "=a" (*eax),
217 "=b" (*ebx),
218 "=c" (*ecx),
219 "=d" (*edx)
220 : "0" (*eax), "2" (*ecx)
221 : "memory");
222 }
223
224 #define native_cpuid_reg(reg) \
225 static inline unsigned int native_cpuid_##reg(unsigned int op) \
226 { \
227 unsigned int eax = op, ebx, ecx = 0, edx; \
228 \
229 native_cpuid(&eax, &ebx, &ecx, &edx); \
230 \
231 return reg; \
232 }
233
234 /*
235 * Native CPUID functions returning a single datum.
236 */
237 native_cpuid_reg(eax)
native_cpuid_reg(ebx)238 native_cpuid_reg(ebx)
239 native_cpuid_reg(ecx)
240 native_cpuid_reg(edx)
241
242 /*
243 * Friendlier CR3 helpers.
244 */
245 static inline unsigned long read_cr3_pa(void)
246 {
247 return __read_cr3() & CR3_ADDR_MASK;
248 }
249
native_read_cr3_pa(void)250 static inline unsigned long native_read_cr3_pa(void)
251 {
252 return __native_read_cr3() & CR3_ADDR_MASK;
253 }
254
load_cr3(pgd_t * pgdir)255 static inline void load_cr3(pgd_t *pgdir)
256 {
257 write_cr3(__sme_pa(pgdir));
258 }
259
260 /*
261 * Note that while the legacy 'TSS' name comes from 'Task State Segment',
262 * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
263 * unrelated to the task-switch mechanism:
264 */
265 #ifdef CONFIG_X86_32
266 /* This is the TSS defined by the hardware. */
267 struct x86_hw_tss {
268 unsigned short back_link, __blh;
269 unsigned long sp0;
270 unsigned short ss0, __ss0h;
271 unsigned long sp1;
272
273 /*
274 * We don't use ring 1, so ss1 is a convenient scratch space in
275 * the same cacheline as sp0. We use ss1 to cache the value in
276 * MSR_IA32_SYSENTER_CS. When we context switch
277 * MSR_IA32_SYSENTER_CS, we first check if the new value being
278 * written matches ss1, and, if it's not, then we wrmsr the new
279 * value and update ss1.
280 *
281 * The only reason we context switch MSR_IA32_SYSENTER_CS is
282 * that we set it to zero in vm86 tasks to avoid corrupting the
283 * stack if we were to go through the sysenter path from vm86
284 * mode.
285 */
286 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
287
288 unsigned short __ss1h;
289 unsigned long sp2;
290 unsigned short ss2, __ss2h;
291 unsigned long __cr3;
292 unsigned long ip;
293 unsigned long flags;
294 unsigned long ax;
295 unsigned long cx;
296 unsigned long dx;
297 unsigned long bx;
298 unsigned long sp;
299 unsigned long bp;
300 unsigned long si;
301 unsigned long di;
302 unsigned short es, __esh;
303 unsigned short cs, __csh;
304 unsigned short ss, __ssh;
305 unsigned short ds, __dsh;
306 unsigned short fs, __fsh;
307 unsigned short gs, __gsh;
308 unsigned short ldt, __ldth;
309 unsigned short trace;
310 unsigned short io_bitmap_base;
311
312 } __attribute__((packed));
313 #else
314 struct x86_hw_tss {
315 u32 reserved1;
316 u64 sp0;
317
318 /*
319 * We store cpu_current_top_of_stack in sp1 so it's always accessible.
320 * Linux does not use ring 1, so sp1 is not otherwise needed.
321 */
322 u64 sp1;
323
324 /*
325 * Since Linux does not use ring 2, the 'sp2' slot is unused by
326 * hardware. entry_SYSCALL_64 uses it as scratch space to stash
327 * the user RSP value.
328 */
329 u64 sp2;
330
331 u64 reserved2;
332 u64 ist[7];
333 u32 reserved3;
334 u32 reserved4;
335 u16 reserved5;
336 u16 io_bitmap_base;
337
338 } __attribute__((packed));
339 #endif
340
341 /*
342 * IO-bitmap sizes:
343 */
344 #define IO_BITMAP_BITS 65536
345 #define IO_BITMAP_BYTES (IO_BITMAP_BITS / BITS_PER_BYTE)
346 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES / sizeof(long))
347
348 #define IO_BITMAP_OFFSET_VALID_MAP \
349 (offsetof(struct tss_struct, io_bitmap.bitmap) - \
350 offsetof(struct tss_struct, x86_tss))
351
352 #define IO_BITMAP_OFFSET_VALID_ALL \
353 (offsetof(struct tss_struct, io_bitmap.mapall) - \
354 offsetof(struct tss_struct, x86_tss))
355
356 #ifdef CONFIG_X86_IOPL_IOPERM
357 /*
358 * sizeof(unsigned long) coming from an extra "long" at the end of the
359 * iobitmap. The limit is inclusive, i.e. the last valid byte.
360 */
361 # define __KERNEL_TSS_LIMIT \
362 (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \
363 sizeof(unsigned long) - 1)
364 #else
365 # define __KERNEL_TSS_LIMIT \
366 (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1)
367 #endif
368
369 /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */
370 #define IO_BITMAP_OFFSET_INVALID (__KERNEL_TSS_LIMIT + 1)
371
372 struct entry_stack {
373 char stack[PAGE_SIZE];
374 };
375
376 struct entry_stack_page {
377 struct entry_stack stack;
378 } __aligned(PAGE_SIZE);
379
380 /*
381 * All IO bitmap related data stored in the TSS:
382 */
383 struct x86_io_bitmap {
384 /* The sequence number of the last active bitmap. */
385 u64 prev_sequence;
386
387 /*
388 * Store the dirty size of the last io bitmap offender. The next
389 * one will have to do the cleanup as the switch out to a non io
390 * bitmap user will just set x86_tss.io_bitmap_base to a value
391 * outside of the TSS limit. So for sane tasks there is no need to
392 * actually touch the io_bitmap at all.
393 */
394 unsigned int prev_max;
395
396 /*
397 * The extra 1 is there because the CPU will access an
398 * additional byte beyond the end of the IO permission
399 * bitmap. The extra byte must be all 1 bits, and must
400 * be within the limit.
401 */
402 unsigned long bitmap[IO_BITMAP_LONGS + 1];
403
404 /*
405 * Special I/O bitmap to emulate IOPL(3). All bytes zero,
406 * except the additional byte at the end.
407 */
408 unsigned long mapall[IO_BITMAP_LONGS + 1];
409 };
410
411 struct tss_struct {
412 /*
413 * The fixed hardware portion. This must not cross a page boundary
414 * at risk of violating the SDM's advice and potentially triggering
415 * errata.
416 */
417 struct x86_hw_tss x86_tss;
418
419 struct x86_io_bitmap io_bitmap;
420 } __aligned(PAGE_SIZE);
421
422 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
423
424 /* Per CPU interrupt stacks */
425 struct irq_stack {
426 char stack[IRQ_STACK_SIZE];
427 } __aligned(IRQ_STACK_SIZE);
428
429 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
430
431 #ifdef CONFIG_X86_32
432 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
433 #else
434 /* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */
435 #define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1
436 #endif
437
438 #ifdef CONFIG_X86_64
439 struct fixed_percpu_data {
440 /*
441 * GCC hardcodes the stack canary as %gs:40. Since the
442 * irq_stack is the object at %gs:0, we reserve the bottom
443 * 48 bytes of the irq stack for the canary.
444 */
445 char gs_base[40];
446 unsigned long stack_canary;
447 };
448
449 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible;
450 DECLARE_INIT_PER_CPU(fixed_percpu_data);
451
cpu_kernelmode_gs_base(int cpu)452 static inline unsigned long cpu_kernelmode_gs_base(int cpu)
453 {
454 return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu);
455 }
456
457 DECLARE_PER_CPU(unsigned int, irq_count);
458 extern asmlinkage void ignore_sysret(void);
459
460 /* Save actual FS/GS selectors and bases to current->thread */
461 void current_save_fsgs(void);
462 #else /* X86_64 */
463 #ifdef CONFIG_STACKPROTECTOR
464 /*
465 * Make sure stack canary segment base is cached-aligned:
466 * "For Intel Atom processors, avoid non zero segment base address
467 * that is not aligned to cache line boundary at all cost."
468 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
469 */
470 struct stack_canary {
471 char __pad[20]; /* canary at %gs:20 */
472 unsigned long canary;
473 };
474 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
475 #endif
476 /* Per CPU softirq stack pointer */
477 DECLARE_PER_CPU(struct irq_stack *, softirq_stack_ptr);
478 #endif /* X86_64 */
479
480 extern unsigned int fpu_kernel_xstate_size;
481 extern unsigned int fpu_user_xstate_size;
482
483 struct perf_event;
484
485 struct thread_struct {
486 /* Cached TLS descriptors: */
487 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
488 #ifdef CONFIG_X86_32
489 unsigned long sp0;
490 #endif
491 unsigned long sp;
492 #ifdef CONFIG_X86_32
493 unsigned long sysenter_cs;
494 #else
495 unsigned short es;
496 unsigned short ds;
497 unsigned short fsindex;
498 unsigned short gsindex;
499 #endif
500
501 #ifdef CONFIG_X86_64
502 unsigned long fsbase;
503 unsigned long gsbase;
504 #else
505 /*
506 * XXX: this could presumably be unsigned short. Alternatively,
507 * 32-bit kernels could be taught to use fsindex instead.
508 */
509 unsigned long fs;
510 unsigned long gs;
511 #endif
512
513 /* Save middle states of ptrace breakpoints */
514 struct perf_event *ptrace_bps[HBP_NUM];
515 /* Debug status used for traps, single steps, etc... */
516 unsigned long virtual_dr6;
517 /* Keep track of the exact dr7 value set by the user */
518 unsigned long ptrace_dr7;
519 /* Fault info: */
520 unsigned long cr2;
521 unsigned long trap_nr;
522 unsigned long error_code;
523 #ifdef CONFIG_VM86
524 /* Virtual 86 mode info */
525 struct vm86 *vm86;
526 #endif
527 /* IO permissions: */
528 struct io_bitmap *io_bitmap;
529
530 /*
531 * IOPL. Priviledge level dependent I/O permission which is
532 * emulated via the I/O bitmap to prevent user space from disabling
533 * interrupts.
534 */
535 unsigned long iopl_emul;
536
537 unsigned int sig_on_uaccess_err:1;
538
539 /* Floating point and extended processor state */
540 struct fpu fpu;
541 /*
542 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
543 * the end.
544 */
545 };
546
547 /* Whitelist the FPU state from the task_struct for hardened usercopy. */
arch_thread_struct_whitelist(unsigned long * offset,unsigned long * size)548 static inline void arch_thread_struct_whitelist(unsigned long *offset,
549 unsigned long *size)
550 {
551 *offset = offsetof(struct thread_struct, fpu.state);
552 *size = fpu_kernel_xstate_size;
553 }
554
555 /*
556 * Thread-synchronous status.
557 *
558 * This is different from the flags in that nobody else
559 * ever touches our thread-synchronous status, so we don't
560 * have to worry about atomic accesses.
561 */
562 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
563
564 static inline void
native_load_sp0(unsigned long sp0)565 native_load_sp0(unsigned long sp0)
566 {
567 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
568 }
569
native_swapgs(void)570 static __always_inline void native_swapgs(void)
571 {
572 #ifdef CONFIG_X86_64
573 asm volatile("swapgs" ::: "memory");
574 #endif
575 }
576
current_top_of_stack(void)577 static inline unsigned long current_top_of_stack(void)
578 {
579 /*
580 * We can't read directly from tss.sp0: sp0 on x86_32 is special in
581 * and around vm86 mode and sp0 on x86_64 is special because of the
582 * entry trampoline.
583 */
584 return this_cpu_read_stable(cpu_current_top_of_stack);
585 }
586
on_thread_stack(void)587 static inline bool on_thread_stack(void)
588 {
589 return (unsigned long)(current_top_of_stack() -
590 current_stack_pointer) < THREAD_SIZE;
591 }
592
593 #ifdef CONFIG_PARAVIRT_XXL
594 #include <asm/paravirt.h>
595 #else
596 #define __cpuid native_cpuid
597
load_sp0(unsigned long sp0)598 static inline void load_sp0(unsigned long sp0)
599 {
600 native_load_sp0(sp0);
601 }
602
603 #endif /* CONFIG_PARAVIRT_XXL */
604
605 /* Free all resources held by a thread. */
606 extern void release_thread(struct task_struct *);
607
608 unsigned long get_wchan(struct task_struct *p);
609
610 /*
611 * Generic CPUID function
612 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
613 * resulting in stale register contents being returned.
614 */
cpuid(unsigned int op,unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)615 static inline void cpuid(unsigned int op,
616 unsigned int *eax, unsigned int *ebx,
617 unsigned int *ecx, unsigned int *edx)
618 {
619 *eax = op;
620 *ecx = 0;
621 __cpuid(eax, ebx, ecx, edx);
622 }
623
624 /* Some CPUID calls want 'count' to be placed in ecx */
cpuid_count(unsigned int op,int count,unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)625 static inline void cpuid_count(unsigned int op, int count,
626 unsigned int *eax, unsigned int *ebx,
627 unsigned int *ecx, unsigned int *edx)
628 {
629 *eax = op;
630 *ecx = count;
631 __cpuid(eax, ebx, ecx, edx);
632 }
633
634 /*
635 * CPUID functions returning a single datum
636 */
cpuid_eax(unsigned int op)637 static inline unsigned int cpuid_eax(unsigned int op)
638 {
639 unsigned int eax, ebx, ecx, edx;
640
641 cpuid(op, &eax, &ebx, &ecx, &edx);
642
643 return eax;
644 }
645
cpuid_ebx(unsigned int op)646 static inline unsigned int cpuid_ebx(unsigned int op)
647 {
648 unsigned int eax, ebx, ecx, edx;
649
650 cpuid(op, &eax, &ebx, &ecx, &edx);
651
652 return ebx;
653 }
654
cpuid_ecx(unsigned int op)655 static inline unsigned int cpuid_ecx(unsigned int op)
656 {
657 unsigned int eax, ebx, ecx, edx;
658
659 cpuid(op, &eax, &ebx, &ecx, &edx);
660
661 return ecx;
662 }
663
cpuid_edx(unsigned int op)664 static inline unsigned int cpuid_edx(unsigned int op)
665 {
666 unsigned int eax, ebx, ecx, edx;
667
668 cpuid(op, &eax, &ebx, &ecx, &edx);
669
670 return edx;
671 }
672
673 extern void select_idle_routine(const struct cpuinfo_x86 *c);
674 extern void amd_e400_c1e_apic_setup(void);
675
676 extern unsigned long boot_option_idle_override;
677
678 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
679 IDLE_POLL};
680
681 extern void enable_sep_cpu(void);
682 extern int sysenter_setup(void);
683
684
685 /* Defined in head.S */
686 extern struct desc_ptr early_gdt_descr;
687
688 extern void switch_to_new_gdt(int);
689 extern void load_direct_gdt(int);
690 extern void load_fixmap_gdt(int);
691 extern void load_percpu_segment(int);
692 extern void cpu_init(void);
693 extern void cpu_init_exception_handling(void);
694 extern void cr4_init(void);
695
get_debugctlmsr(void)696 static inline unsigned long get_debugctlmsr(void)
697 {
698 unsigned long debugctlmsr = 0;
699
700 #ifndef CONFIG_X86_DEBUGCTLMSR
701 if (boot_cpu_data.x86 < 6)
702 return 0;
703 #endif
704 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
705
706 return debugctlmsr;
707 }
708
update_debugctlmsr(unsigned long debugctlmsr)709 static inline void update_debugctlmsr(unsigned long debugctlmsr)
710 {
711 #ifndef CONFIG_X86_DEBUGCTLMSR
712 if (boot_cpu_data.x86 < 6)
713 return;
714 #endif
715 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
716 }
717
718 extern void set_task_blockstep(struct task_struct *task, bool on);
719
720 /* Boot loader type from the setup header: */
721 extern int bootloader_type;
722 extern int bootloader_version;
723
724 extern char ignore_fpu_irq;
725
726 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
727 #define ARCH_HAS_PREFETCHW
728 #define ARCH_HAS_SPINLOCK_PREFETCH
729
730 #ifdef CONFIG_X86_32
731 # define BASE_PREFETCH ""
732 # define ARCH_HAS_PREFETCH
733 #else
734 # define BASE_PREFETCH "prefetcht0 %P1"
735 #endif
736
737 /*
738 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
739 *
740 * It's not worth to care about 3dnow prefetches for the K6
741 * because they are microcoded there and very slow.
742 */
prefetch(const void * x)743 static inline void prefetch(const void *x)
744 {
745 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
746 X86_FEATURE_XMM,
747 "m" (*(const char *)x));
748 }
749
750 /*
751 * 3dnow prefetch to get an exclusive cache line.
752 * Useful for spinlocks to avoid one state transition in the
753 * cache coherency protocol:
754 */
prefetchw(const void * x)755 static __always_inline void prefetchw(const void *x)
756 {
757 alternative_input(BASE_PREFETCH, "prefetchw %P1",
758 X86_FEATURE_3DNOWPREFETCH,
759 "m" (*(const char *)x));
760 }
761
spin_lock_prefetch(const void * x)762 static inline void spin_lock_prefetch(const void *x)
763 {
764 prefetchw(x);
765 }
766
767 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
768 TOP_OF_KERNEL_STACK_PADDING)
769
770 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
771
772 #define task_pt_regs(task) \
773 ({ \
774 unsigned long __ptr = (unsigned long)task_stack_page(task); \
775 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
776 ((struct pt_regs *)__ptr) - 1; \
777 })
778
779 #ifdef CONFIG_X86_32
780 #define INIT_THREAD { \
781 .sp0 = TOP_OF_INIT_STACK, \
782 .sysenter_cs = __KERNEL_CS, \
783 }
784
785 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
786
787 #else
788 #define INIT_THREAD { }
789
790 extern unsigned long KSTK_ESP(struct task_struct *task);
791
792 #endif /* CONFIG_X86_64 */
793
794 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
795 unsigned long new_sp);
796
797 /*
798 * This decides where the kernel will search for a free chunk of vm
799 * space during mmap's.
800 */
801 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
802 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
803
804 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
805
806 /* Get/set a process' ability to use the timestamp counter instruction */
807 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
808 #define SET_TSC_CTL(val) set_tsc_mode((val))
809
810 extern int get_tsc_mode(unsigned long adr);
811 extern int set_tsc_mode(unsigned int val);
812
813 DECLARE_PER_CPU(u64, msr_misc_features_shadow);
814
815 #ifdef CONFIG_CPU_SUP_AMD
816 extern u16 amd_get_nb_id(int cpu);
817 extern u32 amd_get_nodes_per_socket(void);
818 #else
amd_get_nb_id(int cpu)819 static inline u16 amd_get_nb_id(int cpu) { return 0; }
amd_get_nodes_per_socket(void)820 static inline u32 amd_get_nodes_per_socket(void) { return 0; }
821 #endif
822
hypervisor_cpuid_base(const char * sig,uint32_t leaves)823 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
824 {
825 uint32_t base, eax, signature[3];
826
827 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
828 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
829
830 if (!memcmp(sig, signature, 12) &&
831 (leaves == 0 || ((eax - base) >= leaves)))
832 return base;
833 }
834
835 return 0;
836 }
837
838 extern unsigned long arch_align_stack(unsigned long sp);
839 void free_init_pages(const char *what, unsigned long begin, unsigned long end);
840 extern void free_kernel_image_pages(const char *what, void *begin, void *end);
841
842 void default_idle(void);
843 #ifdef CONFIG_XEN
844 bool xen_set_default_idle(void);
845 #else
846 #define xen_set_default_idle 0
847 #endif
848
849 void stop_this_cpu(void *dummy);
850 void microcode_check(void);
851
852 enum l1tf_mitigations {
853 L1TF_MITIGATION_OFF,
854 L1TF_MITIGATION_FLUSH_NOWARN,
855 L1TF_MITIGATION_FLUSH,
856 L1TF_MITIGATION_FLUSH_NOSMT,
857 L1TF_MITIGATION_FULL,
858 L1TF_MITIGATION_FULL_FORCE
859 };
860
861 extern enum l1tf_mitigations l1tf_mitigation;
862
863 enum mds_mitigations {
864 MDS_MITIGATION_OFF,
865 MDS_MITIGATION_FULL,
866 MDS_MITIGATION_VMWERV,
867 };
868
869 #endif /* _ASM_X86_PROCESSOR_H */
870
