1 /*
2 * Copyright (C) 2009 Thomas Gleixner <tglx@linutronix.de>
3 *
4 * For licencing details see kernel-base/COPYING
5 */
6 #include <linux/init.h>
7 #include <linux/ioport.h>
8 #include <linux/export.h>
9 #include <linux/pci.h>
10
11 #include <asm/acpi.h>
12 #include <asm/bios_ebda.h>
13 #include <asm/paravirt.h>
14 #include <asm/pci_x86.h>
15 #include <asm/mpspec.h>
16 #include <asm/setup.h>
17 #include <asm/apic.h>
18 #include <asm/e820/api.h>
19 #include <asm/time.h>
20 #include <asm/irq.h>
21 #include <asm/io_apic.h>
22 #include <asm/hpet.h>
23 #include <asm/pat.h>
24 #include <asm/tsc.h>
25 #include <asm/iommu.h>
26 #include <asm/mach_traps.h>
27
x86_init_noop(void)28 void x86_init_noop(void) { }
x86_init_uint_noop(unsigned int unused)29 void __init x86_init_uint_noop(unsigned int unused) { }
iommu_init_noop(void)30 static int __init iommu_init_noop(void) { return 0; }
iommu_shutdown_noop(void)31 static void iommu_shutdown_noop(void) { }
bool_x86_init_noop(void)32 bool __init bool_x86_init_noop(void) { return false; }
x86_op_int_noop(int cpu)33 void x86_op_int_noop(int cpu) { }
34
35 /*
36 * The platform setup functions are preset with the default functions
37 * for standard PC hardware.
38 */
39 struct x86_init_ops x86_init __initdata = {
40
41 .resources = {
42 .probe_roms = probe_roms,
43 .reserve_resources = reserve_standard_io_resources,
44 .memory_setup = e820__memory_setup_default,
45 },
46
47 .mpparse = {
48 .mpc_record = x86_init_uint_noop,
49 .setup_ioapic_ids = x86_init_noop,
50 .mpc_apic_id = default_mpc_apic_id,
51 .smp_read_mpc_oem = default_smp_read_mpc_oem,
52 .mpc_oem_bus_info = default_mpc_oem_bus_info,
53 .find_smp_config = default_find_smp_config,
54 .get_smp_config = default_get_smp_config,
55 },
56
57 .irqs = {
58 .pre_vector_init = init_ISA_irqs,
59 .intr_init = native_init_IRQ,
60 .trap_init = x86_init_noop,
61 .intr_mode_init = apic_intr_mode_init
62 },
63
64 .oem = {
65 .arch_setup = x86_init_noop,
66 .banner = default_banner,
67 },
68
69 .paging = {
70 .pagetable_init = native_pagetable_init,
71 },
72
73 .timers = {
74 .setup_percpu_clockev = setup_boot_APIC_clock,
75 .timer_init = hpet_time_init,
76 .wallclock_init = x86_init_noop,
77 },
78
79 .iommu = {
80 .iommu_init = iommu_init_noop,
81 },
82
83 .pci = {
84 .init = x86_default_pci_init,
85 .init_irq = x86_default_pci_init_irq,
86 .fixup_irqs = x86_default_pci_fixup_irqs,
87 },
88
89 .hyper = {
90 .init_platform = x86_init_noop,
91 .guest_late_init = x86_init_noop,
92 .x2apic_available = bool_x86_init_noop,
93 .init_mem_mapping = x86_init_noop,
94 .init_after_bootmem = x86_init_noop,
95 },
96
97 .acpi = {
98 .set_root_pointer = x86_default_set_root_pointer,
99 .get_root_pointer = x86_default_get_root_pointer,
100 .reduced_hw_early_init = acpi_generic_reduced_hw_init,
101 },
102 };
103
104 struct x86_cpuinit_ops x86_cpuinit = {
105 .early_percpu_clock_init = x86_init_noop,
106 .setup_percpu_clockev = setup_secondary_APIC_clock,
107 };
108
default_nmi_init(void)109 static void default_nmi_init(void) { };
110
111 struct x86_platform_ops x86_platform __ro_after_init = {
112 .calibrate_cpu = native_calibrate_cpu_early,
113 .calibrate_tsc = native_calibrate_tsc,
114 .get_wallclock = mach_get_cmos_time,
115 .set_wallclock = mach_set_rtc_mmss,
116 .iommu_shutdown = iommu_shutdown_noop,
117 .is_untracked_pat_range = is_ISA_range,
118 .nmi_init = default_nmi_init,
119 .get_nmi_reason = default_get_nmi_reason,
120 .save_sched_clock_state = tsc_save_sched_clock_state,
121 .restore_sched_clock_state = tsc_restore_sched_clock_state,
122 .hyper.pin_vcpu = x86_op_int_noop,
123 };
124
125 EXPORT_SYMBOL_GPL(x86_platform);
126
127 #if defined(CONFIG_PCI_MSI)
128 struct x86_msi_ops x86_msi __ro_after_init = {
129 .setup_msi_irqs = native_setup_msi_irqs,
130 .teardown_msi_irq = native_teardown_msi_irq,
131 .teardown_msi_irqs = default_teardown_msi_irqs,
132 .restore_msi_irqs = default_restore_msi_irqs,
133 };
134
135 /* MSI arch specific hooks */
arch_setup_msi_irqs(struct pci_dev * dev,int nvec,int type)136 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
137 {
138 return x86_msi.setup_msi_irqs(dev, nvec, type);
139 }
140
arch_teardown_msi_irqs(struct pci_dev * dev)141 void arch_teardown_msi_irqs(struct pci_dev *dev)
142 {
143 x86_msi.teardown_msi_irqs(dev);
144 }
145
arch_teardown_msi_irq(unsigned int irq)146 void arch_teardown_msi_irq(unsigned int irq)
147 {
148 x86_msi.teardown_msi_irq(irq);
149 }
150
arch_restore_msi_irqs(struct pci_dev * dev)151 void arch_restore_msi_irqs(struct pci_dev *dev)
152 {
153 x86_msi.restore_msi_irqs(dev);
154 }
155 #endif
156
157 struct x86_apic_ops x86_apic_ops __ro_after_init = {
158 .io_apic_read = native_io_apic_read,
159 .restore = native_restore_boot_irq_mode,
160 };
161
