1 // SPDX-License-Identifier: GPL-2.0
2 #ifndef __SAMSUNG_H
3 #define __SAMSUNG_H
4 
5 /*
6  * Driver for Samsung SoC onboard UARTs.
7  *
8  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
9  *	http://armlinux.simtec.co.uk/
10 */
11 
12 #include <linux/dmaengine.h>
13 
14 struct s3c24xx_uart_info {
15 	char			*name;
16 	unsigned int		type;
17 	unsigned int		fifosize;
18 	unsigned long		rx_fifomask;
19 	unsigned long		rx_fifoshift;
20 	unsigned long		rx_fifofull;
21 	unsigned long		tx_fifomask;
22 	unsigned long		tx_fifoshift;
23 	unsigned long		tx_fifofull;
24 	unsigned int		def_clk_sel;
25 	unsigned long		num_clks;
26 	unsigned long		clksel_mask;
27 	unsigned long		clksel_shift;
28 
29 	/* uart port features */
30 
31 	unsigned int		has_divslot:1;
32 
33 	/* uart controls */
34 	int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
35 };
36 
37 struct s3c24xx_serial_drv_data {
38 	struct s3c24xx_uart_info	*info;
39 	struct s3c2410_uartcfg		*def_cfg;
40 	unsigned int			fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
41 };
42 
43 struct s3c24xx_uart_dma {
44 	unsigned int			rx_chan_id;
45 	unsigned int			tx_chan_id;
46 
47 	struct dma_slave_config		rx_conf;
48 	struct dma_slave_config		tx_conf;
49 
50 	struct dma_chan			*rx_chan;
51 	struct dma_chan			*tx_chan;
52 
53 	dma_addr_t			rx_addr;
54 	dma_addr_t			tx_addr;
55 
56 	dma_cookie_t			rx_cookie;
57 	dma_cookie_t			tx_cookie;
58 
59 	char				*rx_buf;
60 
61 	dma_addr_t			tx_transfer_addr;
62 
63 	size_t				rx_size;
64 	size_t				tx_size;
65 
66 	struct dma_async_tx_descriptor	*tx_desc;
67 	struct dma_async_tx_descriptor	*rx_desc;
68 
69 	int				tx_bytes_requested;
70 	int				rx_bytes_requested;
71 };
72 
73 struct s3c24xx_uart_port {
74 	unsigned char			rx_claimed;
75 	unsigned char			tx_claimed;
76 	unsigned int			pm_level;
77 	unsigned long			baudclk_rate;
78 	unsigned int			min_dma_size;
79 
80 	unsigned int			rx_irq;
81 	unsigned int			tx_irq;
82 
83 	unsigned int			tx_in_progress;
84 	unsigned int			tx_mode;
85 	unsigned int			rx_mode;
86 
87 	struct s3c24xx_uart_info	*info;
88 	struct clk			*clk;
89 	struct clk			*baudclk;
90 	struct uart_port		port;
91 	struct s3c24xx_serial_drv_data	*drv_data;
92 
93 	/* reference to platform data */
94 	struct s3c2410_uartcfg		*cfg;
95 
96 	struct s3c24xx_uart_dma		*dma;
97 
98 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
99 	struct notifier_block		freq_transition;
100 #endif
101 };
102 
103 /* conversion functions */
104 
105 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
106 
107 /* register access controls */
108 
109 #define portaddr(port, reg) ((port)->membase + (reg))
110 #define portaddrl(port, reg) \
111 	((unsigned long *)(unsigned long)((port)->membase + (reg)))
112 
113 #define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg)))
114 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
115 
116 #define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg))
117 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
118 
119 /* Byte-order aware bit setting/clearing functions. */
120 
s3c24xx_set_bit(struct uart_port * port,int idx,unsigned int reg)121 static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
122 				   unsigned int reg)
123 {
124 	unsigned long flags;
125 	u32 val;
126 
127 	local_irq_save(flags);
128 	val = rd_regl(port, reg);
129 	val |= (1 << idx);
130 	wr_regl(port, reg, val);
131 	local_irq_restore(flags);
132 }
133 
s3c24xx_clear_bit(struct uart_port * port,int idx,unsigned int reg)134 static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
135 				     unsigned int reg)
136 {
137 	unsigned long flags;
138 	u32 val;
139 
140 	local_irq_save(flags);
141 	val = rd_regl(port, reg);
142 	val &= ~(1 << idx);
143 	wr_regl(port, reg, val);
144 	local_irq_restore(flags);
145 }
146 
147 #endif
148