1 /*
2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc.
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <linux/interrupt.h>
19
20 #include "wil6210.h"
21 #include "trace.h"
22
23 /**
24 * Theory of operation:
25 *
26 * There is ISR pseudo-cause register,
27 * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
28 * Its bits represents OR'ed bits from 3 real ISR registers:
29 * TX, RX, and MISC.
30 *
31 * Registers may be configured to either "write 1 to clear" or
32 * "clear on read" mode
33 *
34 * When handling interrupt, one have to mask/unmask interrupts for the
35 * real ISR registers, or hardware may malfunction.
36 *
37 */
38
39 #define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
40 #define WIL6210_IRQ_DISABLE_NO_HALP (0xF7FFFFFFUL)
41 #define WIL6210_IMC_RX (BIT_DMA_EP_RX_ICR_RX_DONE | \
42 BIT_DMA_EP_RX_ICR_RX_HTRSH)
43 #define WIL6210_IMC_RX_NO_RX_HTRSH (WIL6210_IMC_RX & \
44 (~(BIT_DMA_EP_RX_ICR_RX_HTRSH)))
45 #define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \
46 BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
47 #define WIL6210_IMC_TX_EDMA BIT_TX_STATUS_IRQ
48 #define WIL6210_IMC_RX_EDMA BIT_RX_STATUS_IRQ
49 #define WIL6210_IMC_MISC_NO_HALP (ISR_MISC_FW_READY | \
50 ISR_MISC_MBOX_EVT | \
51 ISR_MISC_FW_ERROR)
52 #define WIL6210_IMC_MISC (WIL6210_IMC_MISC_NO_HALP | \
53 BIT_DMA_EP_MISC_ICR_HALP)
54 #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
55 BIT_DMA_PSEUDO_CAUSE_TX | \
56 BIT_DMA_PSEUDO_CAUSE_MISC))
57
58 #if defined(CONFIG_WIL6210_ISR_COR)
59 /* configure to Clear-On-Read mode */
60 #define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL)
61 #define WIL_ICR_ICC_MISC_VALUE (0xF7FFFFFFUL)
62
wil_icr_clear(u32 x,void __iomem * addr)63 static inline void wil_icr_clear(u32 x, void __iomem *addr)
64 {
65 }
66 #else /* defined(CONFIG_WIL6210_ISR_COR) */
67 /* configure to Write-1-to-Clear mode */
68 #define WIL_ICR_ICC_VALUE (0UL)
69 #define WIL_ICR_ICC_MISC_VALUE (0UL)
70
wil_icr_clear(u32 x,void __iomem * addr)71 static inline void wil_icr_clear(u32 x, void __iomem *addr)
72 {
73 writel(x, addr);
74 }
75 #endif /* defined(CONFIG_WIL6210_ISR_COR) */
76
wil_ioread32_and_clear(void __iomem * addr)77 static inline u32 wil_ioread32_and_clear(void __iomem *addr)
78 {
79 u32 x = readl(addr);
80
81 wil_icr_clear(x, addr);
82
83 return x;
84 }
85
wil6210_mask_irq_tx(struct wil6210_priv * wil)86 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
87 {
88 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMS),
89 WIL6210_IRQ_DISABLE);
90 }
91
wil6210_mask_irq_tx_edma(struct wil6210_priv * wil)92 static void wil6210_mask_irq_tx_edma(struct wil6210_priv *wil)
93 {
94 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMS),
95 WIL6210_IRQ_DISABLE);
96 }
97
wil6210_mask_irq_rx(struct wil6210_priv * wil)98 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
99 {
100 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMS),
101 WIL6210_IRQ_DISABLE);
102 }
103
wil6210_mask_irq_rx_edma(struct wil6210_priv * wil)104 static void wil6210_mask_irq_rx_edma(struct wil6210_priv *wil)
105 {
106 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMS),
107 WIL6210_IRQ_DISABLE);
108 }
109
wil6210_mask_irq_misc(struct wil6210_priv * wil,bool mask_halp)110 static void wil6210_mask_irq_misc(struct wil6210_priv *wil, bool mask_halp)
111 {
112 wil_dbg_irq(wil, "mask_irq_misc: mask_halp(%s)\n",
113 mask_halp ? "true" : "false");
114
115 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
116 mask_halp ? WIL6210_IRQ_DISABLE : WIL6210_IRQ_DISABLE_NO_HALP);
117 }
118
wil6210_mask_halp(struct wil6210_priv * wil)119 void wil6210_mask_halp(struct wil6210_priv *wil)
120 {
121 wil_dbg_irq(wil, "mask_halp\n");
122
123 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
124 BIT_DMA_EP_MISC_ICR_HALP);
125 }
126
wil6210_mask_irq_pseudo(struct wil6210_priv * wil)127 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
128 {
129 wil_dbg_irq(wil, "mask_irq_pseudo\n");
130
131 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_DISABLE);
132
133 clear_bit(wil_status_irqen, wil->status);
134 }
135
wil6210_unmask_irq_tx(struct wil6210_priv * wil)136 void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
137 {
138 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMC),
139 WIL6210_IMC_TX);
140 }
141
wil6210_unmask_irq_tx_edma(struct wil6210_priv * wil)142 void wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil)
143 {
144 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMC),
145 WIL6210_IMC_TX_EDMA);
146 }
147
wil6210_unmask_irq_rx(struct wil6210_priv * wil)148 void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
149 {
150 bool unmask_rx_htrsh = atomic_read(&wil->connected_vifs) > 0;
151
152 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMC),
153 unmask_rx_htrsh ? WIL6210_IMC_RX : WIL6210_IMC_RX_NO_RX_HTRSH);
154 }
155
wil6210_unmask_irq_rx_edma(struct wil6210_priv * wil)156 void wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil)
157 {
158 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMC),
159 WIL6210_IMC_RX_EDMA);
160 }
161
wil6210_unmask_irq_misc(struct wil6210_priv * wil,bool unmask_halp)162 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil, bool unmask_halp)
163 {
164 wil_dbg_irq(wil, "unmask_irq_misc: unmask_halp(%s)\n",
165 unmask_halp ? "true" : "false");
166
167 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
168 unmask_halp ? WIL6210_IMC_MISC : WIL6210_IMC_MISC_NO_HALP);
169 }
170
wil6210_unmask_halp(struct wil6210_priv * wil)171 static void wil6210_unmask_halp(struct wil6210_priv *wil)
172 {
173 wil_dbg_irq(wil, "unmask_halp\n");
174
175 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
176 BIT_DMA_EP_MISC_ICR_HALP);
177 }
178
wil6210_unmask_irq_pseudo(struct wil6210_priv * wil)179 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
180 {
181 wil_dbg_irq(wil, "unmask_irq_pseudo\n");
182
183 set_bit(wil_status_irqen, wil->status);
184
185 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_PSEUDO_MASK);
186 }
187
wil_mask_irq(struct wil6210_priv * wil)188 void wil_mask_irq(struct wil6210_priv *wil)
189 {
190 wil_dbg_irq(wil, "mask_irq\n");
191
192 wil6210_mask_irq_tx(wil);
193 wil6210_mask_irq_tx_edma(wil);
194 wil6210_mask_irq_rx(wil);
195 wil6210_mask_irq_rx_edma(wil);
196 wil6210_mask_irq_misc(wil, true);
197 wil6210_mask_irq_pseudo(wil);
198 }
199
wil_unmask_irq(struct wil6210_priv * wil)200 void wil_unmask_irq(struct wil6210_priv *wil)
201 {
202 wil_dbg_irq(wil, "unmask_irq\n");
203
204 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC),
205 WIL_ICR_ICC_VALUE);
206 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC),
207 WIL_ICR_ICC_VALUE);
208 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC),
209 WIL_ICR_ICC_MISC_VALUE);
210 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, ICC),
211 WIL_ICR_ICC_VALUE);
212 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, ICC),
213 WIL_ICR_ICC_VALUE);
214
215 wil6210_unmask_irq_pseudo(wil);
216 if (wil->use_enhanced_dma_hw) {
217 wil6210_unmask_irq_tx_edma(wil);
218 wil6210_unmask_irq_rx_edma(wil);
219 } else {
220 wil6210_unmask_irq_tx(wil);
221 wil6210_unmask_irq_rx(wil);
222 }
223 wil6210_unmask_irq_misc(wil, true);
224 }
225
wil_configure_interrupt_moderation_edma(struct wil6210_priv * wil)226 void wil_configure_interrupt_moderation_edma(struct wil6210_priv *wil)
227 {
228 u32 moderation;
229
230 wil_s(wil, RGF_INT_GEN_IDLE_TIME_LIMIT, WIL_EDMA_IDLE_TIME_LIMIT_USEC);
231
232 wil_s(wil, RGF_INT_GEN_TIME_UNIT_LIMIT, WIL_EDMA_TIME_UNIT_CLK_CYCLES);
233
234 /* Update RX and TX moderation */
235 moderation = wil->rx_max_burst_duration |
236 (WIL_EDMA_AGG_WATERMARK << WIL_EDMA_AGG_WATERMARK_POS);
237 wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_0, moderation);
238 wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_1, moderation);
239
240 /* Treat special events as regular
241 * (set bit 0 to 0x1 and clear bits 1-8)
242 */
243 wil_c(wil, RGF_INT_COUNT_ON_SPECIAL_EVT, 0x1FE);
244 wil_s(wil, RGF_INT_COUNT_ON_SPECIAL_EVT, 0x1);
245 }
246
wil_configure_interrupt_moderation(struct wil6210_priv * wil)247 void wil_configure_interrupt_moderation(struct wil6210_priv *wil)
248 {
249 struct wireless_dev *wdev = wil->main_ndev->ieee80211_ptr;
250
251 wil_dbg_irq(wil, "configure_interrupt_moderation\n");
252
253 /* disable interrupt moderation for monitor
254 * to get better timestamp precision
255 */
256 if (wdev->iftype == NL80211_IFTYPE_MONITOR)
257 return;
258
259 /* Disable and clear tx counter before (re)configuration */
260 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR);
261 wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration);
262 wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n",
263 wil->tx_max_burst_duration);
264 /* Configure TX max burst duration timer to use usec units */
265 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL,
266 BIT_DMA_ITR_TX_CNT_CTL_EN | BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL);
267
268 /* Disable and clear tx idle counter before (re)configuration */
269 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR);
270 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout);
271 wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n",
272 wil->tx_interframe_timeout);
273 /* Configure TX max burst duration timer to use usec units */
274 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN |
275 BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL);
276
277 /* Disable and clear rx counter before (re)configuration */
278 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR);
279 wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration);
280 wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n",
281 wil->rx_max_burst_duration);
282 /* Configure TX max burst duration timer to use usec units */
283 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL,
284 BIT_DMA_ITR_RX_CNT_CTL_EN | BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL);
285
286 /* Disable and clear rx idle counter before (re)configuration */
287 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR);
288 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout);
289 wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n",
290 wil->rx_interframe_timeout);
291 /* Configure TX max burst duration timer to use usec units */
292 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN |
293 BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL);
294 }
295
wil6210_irq_rx(int irq,void * cookie)296 static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
297 {
298 struct wil6210_priv *wil = cookie;
299 u32 isr = wil_ioread32_and_clear(wil->csr +
300 HOSTADDR(RGF_DMA_EP_RX_ICR) +
301 offsetof(struct RGF_ICR, ICR));
302 bool need_unmask = true;
303
304 trace_wil6210_irq_rx(isr);
305 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
306
307 if (unlikely(!isr)) {
308 wil_err_ratelimited(wil, "spurious IRQ: RX\n");
309 return IRQ_NONE;
310 }
311
312 wil6210_mask_irq_rx(wil);
313
314 /* RX_DONE and RX_HTRSH interrupts are the same if interrupt
315 * moderation is not used. Interrupt moderation may cause RX
316 * buffer overflow while RX_DONE is delayed. The required
317 * action is always the same - should empty the accumulated
318 * packets from the RX ring.
319 */
320 if (likely(isr & (BIT_DMA_EP_RX_ICR_RX_DONE |
321 BIT_DMA_EP_RX_ICR_RX_HTRSH))) {
322 wil_dbg_irq(wil, "RX done / RX_HTRSH received, ISR (0x%x)\n",
323 isr);
324
325 isr &= ~(BIT_DMA_EP_RX_ICR_RX_DONE |
326 BIT_DMA_EP_RX_ICR_RX_HTRSH);
327 if (likely(test_bit(wil_status_fwready, wil->status))) {
328 if (likely(test_bit(wil_status_napi_en, wil->status))) {
329 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
330 need_unmask = false;
331 napi_schedule(&wil->napi_rx);
332 } else {
333 wil_err_ratelimited(
334 wil,
335 "Got Rx interrupt while stopping interface\n");
336 }
337 } else {
338 wil_err_ratelimited(wil, "Got Rx interrupt while in reset\n");
339 }
340 }
341
342 if (unlikely(isr))
343 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
344
345 /* Rx IRQ will be enabled when NAPI processing finished */
346
347 atomic_inc(&wil->isr_count_rx);
348
349 if (unlikely(need_unmask))
350 wil6210_unmask_irq_rx(wil);
351
352 return IRQ_HANDLED;
353 }
354
wil6210_irq_rx_edma(int irq,void * cookie)355 static irqreturn_t wil6210_irq_rx_edma(int irq, void *cookie)
356 {
357 struct wil6210_priv *wil = cookie;
358 u32 isr = wil_ioread32_and_clear(wil->csr +
359 HOSTADDR(RGF_INT_GEN_RX_ICR) +
360 offsetof(struct RGF_ICR, ICR));
361 bool need_unmask = true;
362
363 trace_wil6210_irq_rx(isr);
364 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
365
366 if (unlikely(!isr)) {
367 wil_err(wil, "spurious IRQ: RX\n");
368 return IRQ_NONE;
369 }
370
371 wil6210_mask_irq_rx_edma(wil);
372
373 if (likely(isr & BIT_RX_STATUS_IRQ)) {
374 wil_dbg_irq(wil, "RX status ring\n");
375 isr &= ~BIT_RX_STATUS_IRQ;
376 if (likely(test_bit(wil_status_fwready, wil->status))) {
377 if (likely(test_bit(wil_status_napi_en, wil->status))) {
378 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
379 need_unmask = false;
380 napi_schedule(&wil->napi_rx);
381 } else {
382 wil_err(wil,
383 "Got Rx interrupt while stopping interface\n");
384 }
385 } else {
386 wil_err(wil, "Got Rx interrupt while in reset\n");
387 }
388 }
389
390 if (unlikely(isr))
391 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
392
393 /* Rx IRQ will be enabled when NAPI processing finished */
394
395 atomic_inc(&wil->isr_count_rx);
396
397 if (unlikely(need_unmask))
398 wil6210_unmask_irq_rx_edma(wil);
399
400 return IRQ_HANDLED;
401 }
402
wil6210_irq_tx_edma(int irq,void * cookie)403 static irqreturn_t wil6210_irq_tx_edma(int irq, void *cookie)
404 {
405 struct wil6210_priv *wil = cookie;
406 u32 isr = wil_ioread32_and_clear(wil->csr +
407 HOSTADDR(RGF_INT_GEN_TX_ICR) +
408 offsetof(struct RGF_ICR, ICR));
409 bool need_unmask = true;
410
411 trace_wil6210_irq_tx(isr);
412 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
413
414 if (unlikely(!isr)) {
415 wil_err(wil, "spurious IRQ: TX\n");
416 return IRQ_NONE;
417 }
418
419 wil6210_mask_irq_tx_edma(wil);
420
421 if (likely(isr & BIT_TX_STATUS_IRQ)) {
422 wil_dbg_irq(wil, "TX status ring\n");
423 isr &= ~BIT_TX_STATUS_IRQ;
424 if (likely(test_bit(wil_status_fwready, wil->status))) {
425 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
426 need_unmask = false;
427 napi_schedule(&wil->napi_tx);
428 } else {
429 wil_err(wil, "Got Tx status ring IRQ while in reset\n");
430 }
431 }
432
433 if (unlikely(isr))
434 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
435
436 /* Tx IRQ will be enabled when NAPI processing finished */
437
438 atomic_inc(&wil->isr_count_tx);
439
440 if (unlikely(need_unmask))
441 wil6210_unmask_irq_tx_edma(wil);
442
443 return IRQ_HANDLED;
444 }
445
wil6210_irq_tx(int irq,void * cookie)446 static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
447 {
448 struct wil6210_priv *wil = cookie;
449 u32 isr = wil_ioread32_and_clear(wil->csr +
450 HOSTADDR(RGF_DMA_EP_TX_ICR) +
451 offsetof(struct RGF_ICR, ICR));
452 bool need_unmask = true;
453
454 trace_wil6210_irq_tx(isr);
455 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
456
457 if (unlikely(!isr)) {
458 wil_err_ratelimited(wil, "spurious IRQ: TX\n");
459 return IRQ_NONE;
460 }
461
462 wil6210_mask_irq_tx(wil);
463
464 if (likely(isr & BIT_DMA_EP_TX_ICR_TX_DONE)) {
465 wil_dbg_irq(wil, "TX done\n");
466 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
467 /* clear also all VRING interrupts */
468 isr &= ~(BIT(25) - 1UL);
469 if (likely(test_bit(wil_status_fwready, wil->status))) {
470 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
471 need_unmask = false;
472 napi_schedule(&wil->napi_tx);
473 } else {
474 wil_err_ratelimited(wil, "Got Tx interrupt while in reset\n");
475 }
476 }
477
478 if (unlikely(isr))
479 wil_err_ratelimited(wil, "un-handled TX ISR bits 0x%08x\n",
480 isr);
481
482 /* Tx IRQ will be enabled when NAPI processing finished */
483
484 atomic_inc(&wil->isr_count_tx);
485
486 if (unlikely(need_unmask))
487 wil6210_unmask_irq_tx(wil);
488
489 return IRQ_HANDLED;
490 }
491
wil_notify_fw_error(struct wil6210_priv * wil)492 static void wil_notify_fw_error(struct wil6210_priv *wil)
493 {
494 struct device *dev = &wil->main_ndev->dev;
495 char *envp[3] = {
496 [0] = "SOURCE=wil6210",
497 [1] = "EVENT=FW_ERROR",
498 [2] = NULL,
499 };
500 wil_err(wil, "Notify about firmware error\n");
501 kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
502 }
503
wil_cache_mbox_regs(struct wil6210_priv * wil)504 static void wil_cache_mbox_regs(struct wil6210_priv *wil)
505 {
506 /* make shadow copy of registers that should not change on run time */
507 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
508 sizeof(struct wil6210_mbox_ctl));
509 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
510 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
511 }
512
wil_validate_mbox_regs(struct wil6210_priv * wil)513 static bool wil_validate_mbox_regs(struct wil6210_priv *wil)
514 {
515 size_t min_size = sizeof(struct wil6210_mbox_hdr) +
516 sizeof(struct wmi_cmd_hdr);
517
518 if (wil->mbox_ctl.rx.entry_size < min_size) {
519 wil_err(wil, "rx mbox entry too small (%d)\n",
520 wil->mbox_ctl.rx.entry_size);
521 return false;
522 }
523 if (wil->mbox_ctl.tx.entry_size < min_size) {
524 wil_err(wil, "tx mbox entry too small (%d)\n",
525 wil->mbox_ctl.tx.entry_size);
526 return false;
527 }
528
529 return true;
530 }
531
wil6210_irq_misc(int irq,void * cookie)532 static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
533 {
534 struct wil6210_priv *wil = cookie;
535 u32 isr = wil_ioread32_and_clear(wil->csr +
536 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
537 offsetof(struct RGF_ICR, ICR));
538
539 trace_wil6210_irq_misc(isr);
540 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
541
542 if (!isr) {
543 wil_err(wil, "spurious IRQ: MISC\n");
544 return IRQ_NONE;
545 }
546
547 wil6210_mask_irq_misc(wil, false);
548
549 if (isr & ISR_MISC_FW_ERROR) {
550 u32 fw_assert_code = wil_r(wil, wil->rgf_fw_assert_code_addr);
551 u32 ucode_assert_code =
552 wil_r(wil, wil->rgf_ucode_assert_code_addr);
553
554 wil_err(wil,
555 "Firmware error detected, assert codes FW 0x%08x, UCODE 0x%08x\n",
556 fw_assert_code, ucode_assert_code);
557 clear_bit(wil_status_fwready, wil->status);
558 /*
559 * do not clear @isr here - we do 2-nd part in thread
560 * there, user space get notified, and it should be done
561 * in non-atomic context
562 */
563 }
564
565 if (isr & ISR_MISC_FW_READY) {
566 wil_dbg_irq(wil, "IRQ: FW ready\n");
567 wil_cache_mbox_regs(wil);
568 if (wil_validate_mbox_regs(wil))
569 set_bit(wil_status_mbox_ready, wil->status);
570 /**
571 * Actual FW ready indicated by the
572 * WMI_FW_READY_EVENTID
573 */
574 isr &= ~ISR_MISC_FW_READY;
575 }
576
577 if (isr & BIT_DMA_EP_MISC_ICR_HALP) {
578 wil_dbg_irq(wil, "irq_misc: HALP IRQ invoked\n");
579 wil6210_mask_halp(wil);
580 isr &= ~BIT_DMA_EP_MISC_ICR_HALP;
581 complete(&wil->halp.comp);
582 }
583
584 wil->isr_misc = isr;
585
586 if (isr) {
587 return IRQ_WAKE_THREAD;
588 } else {
589 wil6210_unmask_irq_misc(wil, false);
590 return IRQ_HANDLED;
591 }
592 }
593
wil6210_irq_misc_thread(int irq,void * cookie)594 static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
595 {
596 struct wil6210_priv *wil = cookie;
597 u32 isr = wil->isr_misc;
598
599 trace_wil6210_irq_misc_thread(isr);
600 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
601
602 if (isr & ISR_MISC_FW_ERROR) {
603 wil->recovery_state = fw_recovery_pending;
604 wil_fw_core_dump(wil);
605 wil_notify_fw_error(wil);
606 isr &= ~ISR_MISC_FW_ERROR;
607 if (wil->platform_ops.notify) {
608 wil_err(wil, "notify platform driver about FW crash");
609 wil->platform_ops.notify(wil->platform_handle,
610 WIL_PLATFORM_EVT_FW_CRASH);
611 } else {
612 wil_fw_error_recovery(wil);
613 }
614 }
615 if (isr & ISR_MISC_MBOX_EVT) {
616 wil_dbg_irq(wil, "MBOX event\n");
617 wmi_recv_cmd(wil);
618 isr &= ~ISR_MISC_MBOX_EVT;
619 }
620
621 if (isr)
622 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
623
624 wil->isr_misc = 0;
625
626 wil6210_unmask_irq_misc(wil, false);
627
628 /* in non-triple MSI case, this is done inside wil6210_thread_irq
629 * because it has to be done after unmasking the pseudo.
630 */
631 if (wil->n_msi == 3 && wil->suspend_resp_rcvd) {
632 wil_dbg_irq(wil, "set suspend_resp_comp to true\n");
633 wil->suspend_resp_comp = true;
634 wake_up_interruptible(&wil->wq);
635 }
636
637 return IRQ_HANDLED;
638 }
639
640 /**
641 * thread IRQ handler
642 */
wil6210_thread_irq(int irq,void * cookie)643 static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
644 {
645 struct wil6210_priv *wil = cookie;
646
647 wil_dbg_irq(wil, "Thread IRQ\n");
648 /* Discover real IRQ cause */
649 if (wil->isr_misc)
650 wil6210_irq_misc_thread(irq, cookie);
651
652 wil6210_unmask_irq_pseudo(wil);
653
654 if (wil->suspend_resp_rcvd) {
655 wil_dbg_irq(wil, "set suspend_resp_comp to true\n");
656 wil->suspend_resp_comp = true;
657 wake_up_interruptible(&wil->wq);
658 }
659
660 return IRQ_HANDLED;
661 }
662
663 /* DEBUG
664 * There is subtle bug in hardware that causes IRQ to raise when it should be
665 * masked. It is quite rare and hard to debug.
666 *
667 * Catch irq issue if it happens and print all I can.
668 */
wil6210_debug_irq_mask(struct wil6210_priv * wil,u32 pseudo_cause)669 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
670 {
671 u32 icm_rx, icr_rx, imv_rx;
672 u32 icm_tx, icr_tx, imv_tx;
673 u32 icm_misc, icr_misc, imv_misc;
674
675 if (!test_bit(wil_status_irqen, wil->status)) {
676 if (wil->use_enhanced_dma_hw) {
677 icm_rx = wil_ioread32_and_clear(wil->csr +
678 HOSTADDR(RGF_INT_GEN_RX_ICR) +
679 offsetof(struct RGF_ICR, ICM));
680 icr_rx = wil_ioread32_and_clear(wil->csr +
681 HOSTADDR(RGF_INT_GEN_RX_ICR) +
682 offsetof(struct RGF_ICR, ICR));
683 imv_rx = wil_r(wil, RGF_INT_GEN_RX_ICR +
684 offsetof(struct RGF_ICR, IMV));
685 icm_tx = wil_ioread32_and_clear(wil->csr +
686 HOSTADDR(RGF_INT_GEN_TX_ICR) +
687 offsetof(struct RGF_ICR, ICM));
688 icr_tx = wil_ioread32_and_clear(wil->csr +
689 HOSTADDR(RGF_INT_GEN_TX_ICR) +
690 offsetof(struct RGF_ICR, ICR));
691 imv_tx = wil_r(wil, RGF_INT_GEN_TX_ICR +
692 offsetof(struct RGF_ICR, IMV));
693 } else {
694 icm_rx = wil_ioread32_and_clear(wil->csr +
695 HOSTADDR(RGF_DMA_EP_RX_ICR) +
696 offsetof(struct RGF_ICR, ICM));
697 icr_rx = wil_ioread32_and_clear(wil->csr +
698 HOSTADDR(RGF_DMA_EP_RX_ICR) +
699 offsetof(struct RGF_ICR, ICR));
700 imv_rx = wil_r(wil, RGF_DMA_EP_RX_ICR +
701 offsetof(struct RGF_ICR, IMV));
702 icm_tx = wil_ioread32_and_clear(wil->csr +
703 HOSTADDR(RGF_DMA_EP_TX_ICR) +
704 offsetof(struct RGF_ICR, ICM));
705 icr_tx = wil_ioread32_and_clear(wil->csr +
706 HOSTADDR(RGF_DMA_EP_TX_ICR) +
707 offsetof(struct RGF_ICR, ICR));
708 imv_tx = wil_r(wil, RGF_DMA_EP_TX_ICR +
709 offsetof(struct RGF_ICR, IMV));
710 }
711 icm_misc = wil_ioread32_and_clear(wil->csr +
712 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
713 offsetof(struct RGF_ICR, ICM));
714 icr_misc = wil_ioread32_and_clear(wil->csr +
715 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
716 offsetof(struct RGF_ICR, ICR));
717 imv_misc = wil_r(wil, RGF_DMA_EP_MISC_ICR +
718 offsetof(struct RGF_ICR, IMV));
719
720 /* HALP interrupt can be unmasked when misc interrupts are
721 * masked
722 */
723 if (icr_misc & BIT_DMA_EP_MISC_ICR_HALP)
724 return 0;
725
726 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
727 "Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
728 "Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
729 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
730 pseudo_cause,
731 icm_rx, icr_rx, imv_rx,
732 icm_tx, icr_tx, imv_tx,
733 icm_misc, icr_misc, imv_misc);
734
735 return -EINVAL;
736 }
737
738 return 0;
739 }
740
wil6210_hardirq(int irq,void * cookie)741 static irqreturn_t wil6210_hardirq(int irq, void *cookie)
742 {
743 irqreturn_t rc = IRQ_HANDLED;
744 struct wil6210_priv *wil = cookie;
745 u32 pseudo_cause = wil_r(wil, RGF_DMA_PSEUDO_CAUSE);
746
747 /**
748 * pseudo_cause is Clear-On-Read, no need to ACK
749 */
750 if (unlikely((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff)))
751 return IRQ_NONE;
752
753 /* IRQ mask debug */
754 if (unlikely(wil6210_debug_irq_mask(wil, pseudo_cause)))
755 return IRQ_NONE;
756
757 trace_wil6210_irq_pseudo(pseudo_cause);
758 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
759
760 wil6210_mask_irq_pseudo(wil);
761
762 /* Discover real IRQ cause
763 * There are 2 possible phases for every IRQ:
764 * - hard IRQ handler called right here
765 * - threaded handler called later
766 *
767 * Hard IRQ handler reads and clears ISR.
768 *
769 * If threaded handler requested, hard IRQ handler
770 * returns IRQ_WAKE_THREAD and saves ISR register value
771 * for the threaded handler use.
772 *
773 * voting for wake thread - need at least 1 vote
774 */
775 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
776 (wil->txrx_ops.irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
777 rc = IRQ_WAKE_THREAD;
778
779 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
780 (wil->txrx_ops.irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
781 rc = IRQ_WAKE_THREAD;
782
783 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
784 (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
785 rc = IRQ_WAKE_THREAD;
786
787 /* if thread is requested, it will unmask IRQ */
788 if (rc != IRQ_WAKE_THREAD)
789 wil6210_unmask_irq_pseudo(wil);
790
791 return rc;
792 }
793
wil6210_request_3msi(struct wil6210_priv * wil,int irq)794 static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
795 {
796 int rc;
797
798 /* IRQ's are in the following order:
799 * - Tx
800 * - Rx
801 * - Misc
802 */
803 rc = request_irq(irq, wil->txrx_ops.irq_tx, IRQF_SHARED,
804 WIL_NAME "_tx", wil);
805 if (rc)
806 return rc;
807
808 rc = request_irq(irq + 1, wil->txrx_ops.irq_rx, IRQF_SHARED,
809 WIL_NAME "_rx", wil);
810 if (rc)
811 goto free0;
812
813 rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
814 wil6210_irq_misc_thread,
815 IRQF_SHARED, WIL_NAME "_misc", wil);
816 if (rc)
817 goto free1;
818
819 return 0;
820 free1:
821 free_irq(irq + 1, wil);
822 free0:
823 free_irq(irq, wil);
824
825 return rc;
826 }
827
828 /* can't use wil_ioread32_and_clear because ICC value is not set yet */
wil_clear32(void __iomem * addr)829 static inline void wil_clear32(void __iomem *addr)
830 {
831 u32 x = readl(addr);
832
833 writel(x, addr);
834 }
835
wil6210_clear_irq(struct wil6210_priv * wil)836 void wil6210_clear_irq(struct wil6210_priv *wil)
837 {
838 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
839 offsetof(struct RGF_ICR, ICR));
840 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
841 offsetof(struct RGF_ICR, ICR));
842 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_RX_ICR) +
843 offsetof(struct RGF_ICR, ICR));
844 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_TX_ICR) +
845 offsetof(struct RGF_ICR, ICR));
846 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
847 offsetof(struct RGF_ICR, ICR));
848 wmb(); /* make sure write completed */
849 }
850
wil6210_set_halp(struct wil6210_priv * wil)851 void wil6210_set_halp(struct wil6210_priv *wil)
852 {
853 wil_dbg_irq(wil, "set_halp\n");
854
855 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICS),
856 BIT_DMA_EP_MISC_ICR_HALP);
857 }
858
wil6210_clear_halp(struct wil6210_priv * wil)859 void wil6210_clear_halp(struct wil6210_priv *wil)
860 {
861 wil_dbg_irq(wil, "clear_halp\n");
862
863 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICR),
864 BIT_DMA_EP_MISC_ICR_HALP);
865 wil6210_unmask_halp(wil);
866 }
867
wil6210_init_irq(struct wil6210_priv * wil,int irq)868 int wil6210_init_irq(struct wil6210_priv *wil, int irq)
869 {
870 int rc;
871
872 wil_dbg_misc(wil, "init_irq: %s, n_msi=%d\n",
873 wil->n_msi ? "MSI" : "INTx", wil->n_msi);
874
875 if (wil->use_enhanced_dma_hw) {
876 wil->txrx_ops.irq_tx = wil6210_irq_tx_edma;
877 wil->txrx_ops.irq_rx = wil6210_irq_rx_edma;
878 } else {
879 wil->txrx_ops.irq_tx = wil6210_irq_tx;
880 wil->txrx_ops.irq_rx = wil6210_irq_rx;
881 }
882
883 if (wil->n_msi == 3)
884 rc = wil6210_request_3msi(wil, irq);
885 else
886 rc = request_threaded_irq(irq, wil6210_hardirq,
887 wil6210_thread_irq,
888 wil->n_msi ? 0 : IRQF_SHARED,
889 WIL_NAME, wil);
890 return rc;
891 }
892
wil6210_fini_irq(struct wil6210_priv * wil,int irq)893 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
894 {
895 wil_dbg_misc(wil, "fini_irq:\n");
896
897 wil_mask_irq(wil);
898 free_irq(irq, wil);
899 if (wil->n_msi == 3) {
900 free_irq(irq + 1, wil);
901 free_irq(irq + 2, wil);
902 }
903 }
904
