1 /******************************************************************************
2 * This software may be used and distributed according to the terms of
3 * the GNU General Public License (GPL), incorporated herein by reference.
4 * Drivers based on or derived from this code fall under the GPL and must
5 * retain the authorship, copyright and license notice. This file is not
6 * a complete program and may only be used when the entire operating
7 * system is licensed under the GPL.
8 * See the file COPYING in this distribution for more information.
9 *
10 * vxge-config.c: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O
11 * Virtualized Server Adapter.
12 * Copyright(c) 2002-2010 Exar Corp.
13 ******************************************************************************/
14 #include <linux/vmalloc.h>
15 #include <linux/etherdevice.h>
16 #include <linux/pci.h>
17 #include <linux/slab.h>
18
19 #include "vxge-traffic.h"
20 #include "vxge-config.h"
21 #include "vxge-main.h"
22
23 #define VXGE_HW_VPATH_STATS_PIO_READ(offset) { \
24 status = __vxge_hw_vpath_stats_access(vpath, \
25 VXGE_HW_STATS_OP_READ, \
26 offset, \
27 &val64); \
28 if (status != VXGE_HW_OK) \
29 return status; \
30 }
31
32 static void
vxge_hw_vpath_set_zero_rx_frm_len(struct vxge_hw_vpath_reg __iomem * vp_reg)33 vxge_hw_vpath_set_zero_rx_frm_len(struct vxge_hw_vpath_reg __iomem *vp_reg)
34 {
35 u64 val64;
36
37 val64 = readq(&vp_reg->rxmac_vcfg0);
38 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
39 writeq(val64, &vp_reg->rxmac_vcfg0);
40 val64 = readq(&vp_reg->rxmac_vcfg0);
41 }
42
43 /*
44 * vxge_hw_vpath_wait_receive_idle - Wait for Rx to become idle
45 */
vxge_hw_vpath_wait_receive_idle(struct __vxge_hw_device * hldev,u32 vp_id)46 int vxge_hw_vpath_wait_receive_idle(struct __vxge_hw_device *hldev, u32 vp_id)
47 {
48 struct vxge_hw_vpath_reg __iomem *vp_reg;
49 struct __vxge_hw_virtualpath *vpath;
50 u64 val64, rxd_count, rxd_spat;
51 int count = 0, total_count = 0;
52
53 vpath = &hldev->virtual_paths[vp_id];
54 vp_reg = vpath->vp_reg;
55
56 vxge_hw_vpath_set_zero_rx_frm_len(vp_reg);
57
58 /* Check that the ring controller for this vpath has enough free RxDs
59 * to send frames to the host. This is done by reading the
60 * PRC_RXD_DOORBELL_VPn register and comparing the read value to the
61 * RXD_SPAT value for the vpath.
62 */
63 val64 = readq(&vp_reg->prc_cfg6);
64 rxd_spat = VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val64) + 1;
65 /* Use a factor of 2 when comparing rxd_count against rxd_spat for some
66 * leg room.
67 */
68 rxd_spat *= 2;
69
70 do {
71 mdelay(1);
72
73 rxd_count = readq(&vp_reg->prc_rxd_doorbell);
74
75 /* Check that the ring controller for this vpath does
76 * not have any frame in its pipeline.
77 */
78 val64 = readq(&vp_reg->frm_in_progress_cnt);
79 if ((rxd_count <= rxd_spat) || (val64 > 0))
80 count = 0;
81 else
82 count++;
83 total_count++;
84 } while ((count < VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT) &&
85 (total_count < VXGE_HW_MAX_POLLING_COUNT));
86
87 if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
88 printk(KERN_ALERT "%s: Still Receiving traffic. Abort wait\n",
89 __func__);
90
91 return total_count;
92 }
93
94 /* vxge_hw_device_wait_receive_idle - This function waits until all frames
95 * stored in the frame buffer for each vpath assigned to the given
96 * function (hldev) have been sent to the host.
97 */
vxge_hw_device_wait_receive_idle(struct __vxge_hw_device * hldev)98 void vxge_hw_device_wait_receive_idle(struct __vxge_hw_device *hldev)
99 {
100 int i, total_count = 0;
101
102 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
103 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
104 continue;
105
106 total_count += vxge_hw_vpath_wait_receive_idle(hldev, i);
107 if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
108 break;
109 }
110 }
111
112 /*
113 * __vxge_hw_device_register_poll
114 * Will poll certain register for specified amount of time.
115 * Will poll until masked bit is not cleared.
116 */
117 static enum vxge_hw_status
__vxge_hw_device_register_poll(void __iomem * reg,u64 mask,u32 max_millis)118 __vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis)
119 {
120 u64 val64;
121 u32 i = 0;
122
123 udelay(10);
124
125 do {
126 val64 = readq(reg);
127 if (!(val64 & mask))
128 return VXGE_HW_OK;
129 udelay(100);
130 } while (++i <= 9);
131
132 i = 0;
133 do {
134 val64 = readq(reg);
135 if (!(val64 & mask))
136 return VXGE_HW_OK;
137 mdelay(1);
138 } while (++i <= max_millis);
139
140 return VXGE_HW_FAIL;
141 }
142
143 static inline enum vxge_hw_status
__vxge_hw_pio_mem_write64(u64 val64,void __iomem * addr,u64 mask,u32 max_millis)144 __vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr,
145 u64 mask, u32 max_millis)
146 {
147 __vxge_hw_pio_mem_write32_lower((u32)vxge_bVALn(val64, 32, 32), addr);
148 wmb();
149 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), addr);
150 wmb();
151
152 return __vxge_hw_device_register_poll(addr, mask, max_millis);
153 }
154
155 static enum vxge_hw_status
vxge_hw_vpath_fw_api(struct __vxge_hw_virtualpath * vpath,u32 action,u32 fw_memo,u32 offset,u64 * data0,u64 * data1,u64 * steer_ctrl)156 vxge_hw_vpath_fw_api(struct __vxge_hw_virtualpath *vpath, u32 action,
157 u32 fw_memo, u32 offset, u64 *data0, u64 *data1,
158 u64 *steer_ctrl)
159 {
160 struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
161 enum vxge_hw_status status;
162 u64 val64;
163 u32 retry = 0, max_retry = 3;
164
165 spin_lock(&vpath->lock);
166 if (!vpath->vp_open) {
167 spin_unlock(&vpath->lock);
168 max_retry = 100;
169 }
170
171 writeq(*data0, &vp_reg->rts_access_steer_data0);
172 writeq(*data1, &vp_reg->rts_access_steer_data1);
173 wmb();
174
175 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
176 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(fw_memo) |
177 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset) |
178 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
179 *steer_ctrl;
180
181 status = __vxge_hw_pio_mem_write64(val64,
182 &vp_reg->rts_access_steer_ctrl,
183 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
184 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
185
186 /* The __vxge_hw_device_register_poll can udelay for a significant
187 * amount of time, blocking other process from the CPU. If it delays
188 * for ~5secs, a NMI error can occur. A way around this is to give up
189 * the processor via msleep, but this is not allowed is under lock.
190 * So, only allow it to sleep for ~4secs if open. Otherwise, delay for
191 * 1sec and sleep for 10ms until the firmware operation has completed
192 * or timed-out.
193 */
194 while ((status != VXGE_HW_OK) && retry++ < max_retry) {
195 if (!vpath->vp_open)
196 msleep(20);
197 status = __vxge_hw_device_register_poll(
198 &vp_reg->rts_access_steer_ctrl,
199 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
200 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
201 }
202
203 if (status != VXGE_HW_OK)
204 goto out;
205
206 val64 = readq(&vp_reg->rts_access_steer_ctrl);
207 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
208 *data0 = readq(&vp_reg->rts_access_steer_data0);
209 *data1 = readq(&vp_reg->rts_access_steer_data1);
210 *steer_ctrl = val64;
211 } else
212 status = VXGE_HW_FAIL;
213
214 out:
215 if (vpath->vp_open)
216 spin_unlock(&vpath->lock);
217 return status;
218 }
219
220 enum vxge_hw_status
vxge_hw_upgrade_read_version(struct __vxge_hw_device * hldev,u32 * major,u32 * minor,u32 * build)221 vxge_hw_upgrade_read_version(struct __vxge_hw_device *hldev, u32 *major,
222 u32 *minor, u32 *build)
223 {
224 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
225 struct __vxge_hw_virtualpath *vpath;
226 enum vxge_hw_status status;
227
228 vpath = &hldev->virtual_paths[hldev->first_vp_id];
229
230 status = vxge_hw_vpath_fw_api(vpath,
231 VXGE_HW_FW_UPGRADE_ACTION,
232 VXGE_HW_FW_UPGRADE_MEMO,
233 VXGE_HW_FW_UPGRADE_OFFSET_READ,
234 &data0, &data1, &steer_ctrl);
235 if (status != VXGE_HW_OK)
236 return status;
237
238 *major = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
239 *minor = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
240 *build = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
241
242 return status;
243 }
244
vxge_hw_flash_fw(struct __vxge_hw_device * hldev)245 enum vxge_hw_status vxge_hw_flash_fw(struct __vxge_hw_device *hldev)
246 {
247 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
248 struct __vxge_hw_virtualpath *vpath;
249 enum vxge_hw_status status;
250 u32 ret;
251
252 vpath = &hldev->virtual_paths[hldev->first_vp_id];
253
254 status = vxge_hw_vpath_fw_api(vpath,
255 VXGE_HW_FW_UPGRADE_ACTION,
256 VXGE_HW_FW_UPGRADE_MEMO,
257 VXGE_HW_FW_UPGRADE_OFFSET_COMMIT,
258 &data0, &data1, &steer_ctrl);
259 if (status != VXGE_HW_OK) {
260 vxge_debug_init(VXGE_ERR, "%s: FW upgrade failed", __func__);
261 goto exit;
262 }
263
264 ret = VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(steer_ctrl) & 0x7F;
265 if (ret != 1) {
266 vxge_debug_init(VXGE_ERR, "%s: FW commit failed with error %d",
267 __func__, ret);
268 status = VXGE_HW_FAIL;
269 }
270
271 exit:
272 return status;
273 }
274
275 enum vxge_hw_status
vxge_update_fw_image(struct __vxge_hw_device * hldev,const u8 * fwdata,int size)276 vxge_update_fw_image(struct __vxge_hw_device *hldev, const u8 *fwdata, int size)
277 {
278 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
279 struct __vxge_hw_virtualpath *vpath;
280 enum vxge_hw_status status;
281 int ret_code, sec_code;
282
283 vpath = &hldev->virtual_paths[hldev->first_vp_id];
284
285 /* send upgrade start command */
286 status = vxge_hw_vpath_fw_api(vpath,
287 VXGE_HW_FW_UPGRADE_ACTION,
288 VXGE_HW_FW_UPGRADE_MEMO,
289 VXGE_HW_FW_UPGRADE_OFFSET_START,
290 &data0, &data1, &steer_ctrl);
291 if (status != VXGE_HW_OK) {
292 vxge_debug_init(VXGE_ERR, " %s: Upgrade start cmd failed",
293 __func__);
294 return status;
295 }
296
297 /* Transfer fw image to adapter 16 bytes at a time */
298 for (; size > 0; size -= VXGE_HW_FW_UPGRADE_BLK_SIZE) {
299 steer_ctrl = 0;
300
301 /* The next 128bits of fwdata to be loaded onto the adapter */
302 data0 = *((u64 *)fwdata);
303 data1 = *((u64 *)fwdata + 1);
304
305 status = vxge_hw_vpath_fw_api(vpath,
306 VXGE_HW_FW_UPGRADE_ACTION,
307 VXGE_HW_FW_UPGRADE_MEMO,
308 VXGE_HW_FW_UPGRADE_OFFSET_SEND,
309 &data0, &data1, &steer_ctrl);
310 if (status != VXGE_HW_OK) {
311 vxge_debug_init(VXGE_ERR, "%s: Upgrade send failed",
312 __func__);
313 goto out;
314 }
315
316 ret_code = VXGE_HW_UPGRADE_GET_RET_ERR_CODE(data0);
317 switch (ret_code) {
318 case VXGE_HW_FW_UPGRADE_OK:
319 /* All OK, send next 16 bytes. */
320 break;
321 case VXGE_FW_UPGRADE_BYTES2SKIP:
322 /* skip bytes in the stream */
323 fwdata += (data0 >> 8) & 0xFFFFFFFF;
324 break;
325 case VXGE_HW_FW_UPGRADE_DONE:
326 goto out;
327 case VXGE_HW_FW_UPGRADE_ERR:
328 sec_code = VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(data0);
329 switch (sec_code) {
330 case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_1:
331 case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_7:
332 printk(KERN_ERR
333 "corrupted data from .ncf file\n");
334 break;
335 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_3:
336 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_4:
337 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_5:
338 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_6:
339 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_8:
340 printk(KERN_ERR "invalid .ncf file\n");
341 break;
342 case VXGE_HW_FW_UPGRADE_ERR_BUFFER_OVERFLOW:
343 printk(KERN_ERR "buffer overflow\n");
344 break;
345 case VXGE_HW_FW_UPGRADE_ERR_FAILED_TO_FLASH:
346 printk(KERN_ERR "failed to flash the image\n");
347 break;
348 case VXGE_HW_FW_UPGRADE_ERR_GENERIC_ERROR_UNKNOWN:
349 printk(KERN_ERR
350 "generic error. Unknown error type\n");
351 break;
352 default:
353 printk(KERN_ERR "Unknown error of type %d\n",
354 sec_code);
355 break;
356 }
357 status = VXGE_HW_FAIL;
358 goto out;
359 default:
360 printk(KERN_ERR "Unknown FW error: %d\n", ret_code);
361 status = VXGE_HW_FAIL;
362 goto out;
363 }
364 /* point to next 16 bytes */
365 fwdata += VXGE_HW_FW_UPGRADE_BLK_SIZE;
366 }
367 out:
368 return status;
369 }
370
371 enum vxge_hw_status
vxge_hw_vpath_eprom_img_ver_get(struct __vxge_hw_device * hldev,struct eprom_image * img)372 vxge_hw_vpath_eprom_img_ver_get(struct __vxge_hw_device *hldev,
373 struct eprom_image *img)
374 {
375 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
376 struct __vxge_hw_virtualpath *vpath;
377 enum vxge_hw_status status;
378 int i;
379
380 vpath = &hldev->virtual_paths[hldev->first_vp_id];
381
382 for (i = 0; i < VXGE_HW_MAX_ROM_IMAGES; i++) {
383 data0 = VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(i);
384 data1 = steer_ctrl = 0;
385
386 status = vxge_hw_vpath_fw_api(vpath,
387 VXGE_HW_FW_API_GET_EPROM_REV,
388 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
389 0, &data0, &data1, &steer_ctrl);
390 if (status != VXGE_HW_OK)
391 break;
392
393 img[i].is_valid = VXGE_HW_GET_EPROM_IMAGE_VALID(data0);
394 img[i].index = VXGE_HW_GET_EPROM_IMAGE_INDEX(data0);
395 img[i].type = VXGE_HW_GET_EPROM_IMAGE_TYPE(data0);
396 img[i].version = VXGE_HW_GET_EPROM_IMAGE_REV(data0);
397 }
398
399 return status;
400 }
401
402 /*
403 * __vxge_hw_channel_free - Free memory allocated for channel
404 * This function deallocates memory from the channel and various arrays
405 * in the channel
406 */
__vxge_hw_channel_free(struct __vxge_hw_channel * channel)407 static void __vxge_hw_channel_free(struct __vxge_hw_channel *channel)
408 {
409 kfree(channel->work_arr);
410 kfree(channel->free_arr);
411 kfree(channel->reserve_arr);
412 kfree(channel->orig_arr);
413 kfree(channel);
414 }
415
416 /*
417 * __vxge_hw_channel_initialize - Initialize a channel
418 * This function initializes a channel by properly setting the
419 * various references
420 */
421 static enum vxge_hw_status
__vxge_hw_channel_initialize(struct __vxge_hw_channel * channel)422 __vxge_hw_channel_initialize(struct __vxge_hw_channel *channel)
423 {
424 u32 i;
425 struct __vxge_hw_virtualpath *vpath;
426
427 vpath = channel->vph->vpath;
428
429 if ((channel->reserve_arr != NULL) && (channel->orig_arr != NULL)) {
430 for (i = 0; i < channel->length; i++)
431 channel->orig_arr[i] = channel->reserve_arr[i];
432 }
433
434 switch (channel->type) {
435 case VXGE_HW_CHANNEL_TYPE_FIFO:
436 vpath->fifoh = (struct __vxge_hw_fifo *)channel;
437 channel->stats = &((struct __vxge_hw_fifo *)
438 channel)->stats->common_stats;
439 break;
440 case VXGE_HW_CHANNEL_TYPE_RING:
441 vpath->ringh = (struct __vxge_hw_ring *)channel;
442 channel->stats = &((struct __vxge_hw_ring *)
443 channel)->stats->common_stats;
444 break;
445 default:
446 break;
447 }
448
449 return VXGE_HW_OK;
450 }
451
452 /*
453 * __vxge_hw_channel_reset - Resets a channel
454 * This function resets a channel by properly setting the various references
455 */
456 static enum vxge_hw_status
__vxge_hw_channel_reset(struct __vxge_hw_channel * channel)457 __vxge_hw_channel_reset(struct __vxge_hw_channel *channel)
458 {
459 u32 i;
460
461 for (i = 0; i < channel->length; i++) {
462 if (channel->reserve_arr != NULL)
463 channel->reserve_arr[i] = channel->orig_arr[i];
464 if (channel->free_arr != NULL)
465 channel->free_arr[i] = NULL;
466 if (channel->work_arr != NULL)
467 channel->work_arr[i] = NULL;
468 }
469 channel->free_ptr = channel->length;
470 channel->reserve_ptr = channel->length;
471 channel->reserve_top = 0;
472 channel->post_index = 0;
473 channel->compl_index = 0;
474
475 return VXGE_HW_OK;
476 }
477
478 /*
479 * __vxge_hw_device_pci_e_init
480 * Initialize certain PCI/PCI-X configuration registers
481 * with recommended values. Save config space for future hw resets.
482 */
__vxge_hw_device_pci_e_init(struct __vxge_hw_device * hldev)483 static void __vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
484 {
485 u16 cmd = 0;
486
487 /* Set the PErr Repconse bit and SERR in PCI command register. */
488 pci_read_config_word(hldev->pdev, PCI_COMMAND, &cmd);
489 cmd |= 0x140;
490 pci_write_config_word(hldev->pdev, PCI_COMMAND, cmd);
491
492 pci_save_state(hldev->pdev);
493 }
494
495 /* __vxge_hw_device_vpath_reset_in_prog_check - Check if vpath reset
496 * in progress
497 * This routine checks the vpath reset in progress register is turned zero
498 */
499 static enum vxge_hw_status
__vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem * vpath_rst_in_prog)500 __vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog)
501 {
502 enum vxge_hw_status status;
503 status = __vxge_hw_device_register_poll(vpath_rst_in_prog,
504 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff),
505 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
506 return status;
507 }
508
509 /*
510 * _hw_legacy_swapper_set - Set the swapper bits for the legacy secion.
511 * Set the swapper bits appropriately for the lagacy section.
512 */
513 static enum vxge_hw_status
__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem * legacy_reg)514 __vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
515 {
516 u64 val64;
517 enum vxge_hw_status status = VXGE_HW_OK;
518
519 val64 = readq(&legacy_reg->toc_swapper_fb);
520
521 wmb();
522
523 switch (val64) {
524 case VXGE_HW_SWAPPER_INITIAL_VALUE:
525 return status;
526
527 case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED:
528 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
529 &legacy_reg->pifm_rd_swap_en);
530 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
531 &legacy_reg->pifm_rd_flip_en);
532 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
533 &legacy_reg->pifm_wr_swap_en);
534 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
535 &legacy_reg->pifm_wr_flip_en);
536 break;
537
538 case VXGE_HW_SWAPPER_BYTE_SWAPPED:
539 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
540 &legacy_reg->pifm_rd_swap_en);
541 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
542 &legacy_reg->pifm_wr_swap_en);
543 break;
544
545 case VXGE_HW_SWAPPER_BIT_FLIPPED:
546 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
547 &legacy_reg->pifm_rd_flip_en);
548 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
549 &legacy_reg->pifm_wr_flip_en);
550 break;
551 }
552
553 wmb();
554
555 val64 = readq(&legacy_reg->toc_swapper_fb);
556
557 if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE)
558 status = VXGE_HW_ERR_SWAPPER_CTRL;
559
560 return status;
561 }
562
563 /*
564 * __vxge_hw_device_toc_get
565 * This routine sets the swapper and reads the toc pointer and returns the
566 * memory mapped address of the toc
567 */
568 static struct vxge_hw_toc_reg __iomem *
__vxge_hw_device_toc_get(void __iomem * bar0)569 __vxge_hw_device_toc_get(void __iomem *bar0)
570 {
571 u64 val64;
572 struct vxge_hw_toc_reg __iomem *toc = NULL;
573 enum vxge_hw_status status;
574
575 struct vxge_hw_legacy_reg __iomem *legacy_reg =
576 (struct vxge_hw_legacy_reg __iomem *)bar0;
577
578 status = __vxge_hw_legacy_swapper_set(legacy_reg);
579 if (status != VXGE_HW_OK)
580 goto exit;
581
582 val64 = readq(&legacy_reg->toc_first_pointer);
583 toc = bar0 + val64;
584 exit:
585 return toc;
586 }
587
588 /*
589 * __vxge_hw_device_reg_addr_get
590 * This routine sets the swapper and reads the toc pointer and initializes the
591 * register location pointers in the device object. It waits until the ric is
592 * completed initializing registers.
593 */
594 static enum vxge_hw_status
__vxge_hw_device_reg_addr_get(struct __vxge_hw_device * hldev)595 __vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev)
596 {
597 u64 val64;
598 u32 i;
599 enum vxge_hw_status status = VXGE_HW_OK;
600
601 hldev->legacy_reg = hldev->bar0;
602
603 hldev->toc_reg = __vxge_hw_device_toc_get(hldev->bar0);
604 if (hldev->toc_reg == NULL) {
605 status = VXGE_HW_FAIL;
606 goto exit;
607 }
608
609 val64 = readq(&hldev->toc_reg->toc_common_pointer);
610 hldev->common_reg = hldev->bar0 + val64;
611
612 val64 = readq(&hldev->toc_reg->toc_mrpcim_pointer);
613 hldev->mrpcim_reg = hldev->bar0 + val64;
614
615 for (i = 0; i < VXGE_HW_TITAN_SRPCIM_REG_SPACES; i++) {
616 val64 = readq(&hldev->toc_reg->toc_srpcim_pointer[i]);
617 hldev->srpcim_reg[i] = hldev->bar0 + val64;
618 }
619
620 for (i = 0; i < VXGE_HW_TITAN_VPMGMT_REG_SPACES; i++) {
621 val64 = readq(&hldev->toc_reg->toc_vpmgmt_pointer[i]);
622 hldev->vpmgmt_reg[i] = hldev->bar0 + val64;
623 }
624
625 for (i = 0; i < VXGE_HW_TITAN_VPATH_REG_SPACES; i++) {
626 val64 = readq(&hldev->toc_reg->toc_vpath_pointer[i]);
627 hldev->vpath_reg[i] = hldev->bar0 + val64;
628 }
629
630 val64 = readq(&hldev->toc_reg->toc_kdfc);
631
632 switch (VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val64)) {
633 case 0:
634 hldev->kdfc = hldev->bar0 + VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val64) ;
635 break;
636 default:
637 break;
638 }
639
640 status = __vxge_hw_device_vpath_reset_in_prog_check(
641 (u64 __iomem *)&hldev->common_reg->vpath_rst_in_prog);
642 exit:
643 return status;
644 }
645
646 /*
647 * __vxge_hw_device_access_rights_get: Get Access Rights of the driver
648 * This routine returns the Access Rights of the driver
649 */
650 static u32
__vxge_hw_device_access_rights_get(u32 host_type,u32 func_id)651 __vxge_hw_device_access_rights_get(u32 host_type, u32 func_id)
652 {
653 u32 access_rights = VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH;
654
655 switch (host_type) {
656 case VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION:
657 if (func_id == 0) {
658 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
659 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
660 }
661 break;
662 case VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION:
663 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
664 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
665 break;
666 case VXGE_HW_NO_MR_SR_VH0_FUNCTION0:
667 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
668 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
669 break;
670 case VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION:
671 case VXGE_HW_SR_VH_VIRTUAL_FUNCTION:
672 case VXGE_HW_MR_SR_VH0_INVALID_CONFIG:
673 break;
674 case VXGE_HW_SR_VH_FUNCTION0:
675 case VXGE_HW_VH_NORMAL_FUNCTION:
676 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
677 break;
678 }
679
680 return access_rights;
681 }
682 /*
683 * __vxge_hw_device_is_privilaged
684 * This routine checks if the device function is privilaged or not
685 */
686
687 enum vxge_hw_status
__vxge_hw_device_is_privilaged(u32 host_type,u32 func_id)688 __vxge_hw_device_is_privilaged(u32 host_type, u32 func_id)
689 {
690 if (__vxge_hw_device_access_rights_get(host_type,
691 func_id) &
692 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)
693 return VXGE_HW_OK;
694 else
695 return VXGE_HW_ERR_PRIVILEGED_OPERATION;
696 }
697
698 /*
699 * __vxge_hw_vpath_func_id_get - Get the function id of the vpath.
700 * Returns the function number of the vpath.
701 */
702 static u32
__vxge_hw_vpath_func_id_get(struct vxge_hw_vpmgmt_reg __iomem * vpmgmt_reg)703 __vxge_hw_vpath_func_id_get(struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg)
704 {
705 u64 val64;
706
707 val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1);
708
709 return
710 (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64);
711 }
712
713 /*
714 * __vxge_hw_device_host_info_get
715 * This routine returns the host type assignments
716 */
__vxge_hw_device_host_info_get(struct __vxge_hw_device * hldev)717 static void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
718 {
719 u64 val64;
720 u32 i;
721
722 val64 = readq(&hldev->common_reg->host_type_assignments);
723
724 hldev->host_type =
725 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
726
727 hldev->vpath_assignments = readq(&hldev->common_reg->vpath_assignments);
728
729 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
730 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
731 continue;
732
733 hldev->func_id =
734 __vxge_hw_vpath_func_id_get(hldev->vpmgmt_reg[i]);
735
736 hldev->access_rights = __vxge_hw_device_access_rights_get(
737 hldev->host_type, hldev->func_id);
738
739 hldev->virtual_paths[i].vp_open = VXGE_HW_VP_NOT_OPEN;
740 hldev->virtual_paths[i].vp_reg = hldev->vpath_reg[i];
741
742 hldev->first_vp_id = i;
743 break;
744 }
745 }
746
747 /*
748 * __vxge_hw_verify_pci_e_info - Validate the pci-e link parameters such as
749 * link width and signalling rate.
750 */
751 static enum vxge_hw_status
__vxge_hw_verify_pci_e_info(struct __vxge_hw_device * hldev)752 __vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev)
753 {
754 struct pci_dev *dev = hldev->pdev;
755 u16 lnk;
756
757 /* Get the negotiated link width and speed from PCI config space */
758 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
759
760 if ((lnk & PCI_EXP_LNKSTA_CLS) != 1)
761 return VXGE_HW_ERR_INVALID_PCI_INFO;
762
763 switch ((lnk & PCI_EXP_LNKSTA_NLW) >> 4) {
764 case PCIE_LNK_WIDTH_RESRV:
765 case PCIE_LNK_X1:
766 case PCIE_LNK_X2:
767 case PCIE_LNK_X4:
768 case PCIE_LNK_X8:
769 break;
770 default:
771 return VXGE_HW_ERR_INVALID_PCI_INFO;
772 }
773
774 return VXGE_HW_OK;
775 }
776
777 /*
778 * __vxge_hw_device_initialize
779 * Initialize Titan-V hardware.
780 */
781 static enum vxge_hw_status
__vxge_hw_device_initialize(struct __vxge_hw_device * hldev)782 __vxge_hw_device_initialize(struct __vxge_hw_device *hldev)
783 {
784 enum vxge_hw_status status = VXGE_HW_OK;
785
786 if (VXGE_HW_OK == __vxge_hw_device_is_privilaged(hldev->host_type,
787 hldev->func_id)) {
788 /* Validate the pci-e link width and speed */
789 status = __vxge_hw_verify_pci_e_info(hldev);
790 if (status != VXGE_HW_OK)
791 goto exit;
792 }
793
794 exit:
795 return status;
796 }
797
798 /*
799 * __vxge_hw_vpath_fw_ver_get - Get the fw version
800 * Returns FW Version
801 */
802 static enum vxge_hw_status
__vxge_hw_vpath_fw_ver_get(struct __vxge_hw_virtualpath * vpath,struct vxge_hw_device_hw_info * hw_info)803 __vxge_hw_vpath_fw_ver_get(struct __vxge_hw_virtualpath *vpath,
804 struct vxge_hw_device_hw_info *hw_info)
805 {
806 struct vxge_hw_device_version *fw_version = &hw_info->fw_version;
807 struct vxge_hw_device_date *fw_date = &hw_info->fw_date;
808 struct vxge_hw_device_version *flash_version = &hw_info->flash_version;
809 struct vxge_hw_device_date *flash_date = &hw_info->flash_date;
810 u64 data0, data1 = 0, steer_ctrl = 0;
811 enum vxge_hw_status status;
812
813 status = vxge_hw_vpath_fw_api(vpath,
814 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
815 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
816 0, &data0, &data1, &steer_ctrl);
817 if (status != VXGE_HW_OK)
818 goto exit;
819
820 fw_date->day =
821 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(data0);
822 fw_date->month =
823 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(data0);
824 fw_date->year =
825 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(data0);
826
827 snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
828 fw_date->month, fw_date->day, fw_date->year);
829
830 fw_version->major =
831 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
832 fw_version->minor =
833 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
834 fw_version->build =
835 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
836
837 snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
838 fw_version->major, fw_version->minor, fw_version->build);
839
840 flash_date->day =
841 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data1);
842 flash_date->month =
843 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data1);
844 flash_date->year =
845 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data1);
846
847 snprintf(flash_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
848 flash_date->month, flash_date->day, flash_date->year);
849
850 flash_version->major =
851 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data1);
852 flash_version->minor =
853 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data1);
854 flash_version->build =
855 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data1);
856
857 snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
858 flash_version->major, flash_version->minor,
859 flash_version->build);
860
861 exit:
862 return status;
863 }
864
865 /*
866 * __vxge_hw_vpath_card_info_get - Get the serial numbers,
867 * part number and product description.
868 */
869 static enum vxge_hw_status
__vxge_hw_vpath_card_info_get(struct __vxge_hw_virtualpath * vpath,struct vxge_hw_device_hw_info * hw_info)870 __vxge_hw_vpath_card_info_get(struct __vxge_hw_virtualpath *vpath,
871 struct vxge_hw_device_hw_info *hw_info)
872 {
873 enum vxge_hw_status status;
874 u64 data0, data1 = 0, steer_ctrl = 0;
875 u8 *serial_number = hw_info->serial_number;
876 u8 *part_number = hw_info->part_number;
877 u8 *product_desc = hw_info->product_desc;
878 u32 i, j = 0;
879
880 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER;
881
882 status = vxge_hw_vpath_fw_api(vpath,
883 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
884 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
885 0, &data0, &data1, &steer_ctrl);
886 if (status != VXGE_HW_OK)
887 return status;
888
889 ((u64 *)serial_number)[0] = be64_to_cpu(data0);
890 ((u64 *)serial_number)[1] = be64_to_cpu(data1);
891
892 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER;
893 data1 = steer_ctrl = 0;
894
895 status = vxge_hw_vpath_fw_api(vpath,
896 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
897 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
898 0, &data0, &data1, &steer_ctrl);
899 if (status != VXGE_HW_OK)
900 return status;
901
902 ((u64 *)part_number)[0] = be64_to_cpu(data0);
903 ((u64 *)part_number)[1] = be64_to_cpu(data1);
904
905 for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0;
906 i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) {
907 data0 = i;
908 data1 = steer_ctrl = 0;
909
910 status = vxge_hw_vpath_fw_api(vpath,
911 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
912 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
913 0, &data0, &data1, &steer_ctrl);
914 if (status != VXGE_HW_OK)
915 return status;
916
917 ((u64 *)product_desc)[j++] = be64_to_cpu(data0);
918 ((u64 *)product_desc)[j++] = be64_to_cpu(data1);
919 }
920
921 return status;
922 }
923
924 /*
925 * __vxge_hw_vpath_pci_func_mode_get - Get the pci mode
926 * Returns pci function mode
927 */
928 static enum vxge_hw_status
__vxge_hw_vpath_pci_func_mode_get(struct __vxge_hw_virtualpath * vpath,struct vxge_hw_device_hw_info * hw_info)929 __vxge_hw_vpath_pci_func_mode_get(struct __vxge_hw_virtualpath *vpath,
930 struct vxge_hw_device_hw_info *hw_info)
931 {
932 u64 data0, data1 = 0, steer_ctrl = 0;
933 enum vxge_hw_status status;
934
935 data0 = 0;
936
937 status = vxge_hw_vpath_fw_api(vpath,
938 VXGE_HW_FW_API_GET_FUNC_MODE,
939 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
940 0, &data0, &data1, &steer_ctrl);
941 if (status != VXGE_HW_OK)
942 return status;
943
944 hw_info->function_mode = VXGE_HW_GET_FUNC_MODE_VAL(data0);
945 return status;
946 }
947
948 /*
949 * __vxge_hw_vpath_addr_get - Get the hw address entry for this vpath
950 * from MAC address table.
951 */
952 static enum vxge_hw_status
__vxge_hw_vpath_addr_get(struct __vxge_hw_virtualpath * vpath,u8 * macaddr,u8 * macaddr_mask)953 __vxge_hw_vpath_addr_get(struct __vxge_hw_virtualpath *vpath,
954 u8 *macaddr, u8 *macaddr_mask)
955 {
956 u64 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
957 data0 = 0, data1 = 0, steer_ctrl = 0;
958 enum vxge_hw_status status;
959 int i;
960
961 do {
962 status = vxge_hw_vpath_fw_api(vpath, action,
963 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
964 0, &data0, &data1, &steer_ctrl);
965 if (status != VXGE_HW_OK)
966 goto exit;
967
968 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data0);
969 data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(
970 data1);
971
972 for (i = ETH_ALEN; i > 0; i--) {
973 macaddr[i - 1] = (u8) (data0 & 0xFF);
974 data0 >>= 8;
975
976 macaddr_mask[i - 1] = (u8) (data1 & 0xFF);
977 data1 >>= 8;
978 }
979
980 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY;
981 data0 = 0, data1 = 0, steer_ctrl = 0;
982
983 } while (!is_valid_ether_addr(macaddr));
984 exit:
985 return status;
986 }
987
988 /**
989 * vxge_hw_device_hw_info_get - Get the hw information
990 * Returns the vpath mask that has the bits set for each vpath allocated
991 * for the driver, FW version information, and the first mac address for
992 * each vpath
993 */
994 enum vxge_hw_status
vxge_hw_device_hw_info_get(void __iomem * bar0,struct vxge_hw_device_hw_info * hw_info)995 vxge_hw_device_hw_info_get(void __iomem *bar0,
996 struct vxge_hw_device_hw_info *hw_info)
997 {
998 u32 i;
999 u64 val64;
1000 struct vxge_hw_toc_reg __iomem *toc;
1001 struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg;
1002 struct vxge_hw_common_reg __iomem *common_reg;
1003 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
1004 enum vxge_hw_status status;
1005 struct __vxge_hw_virtualpath vpath;
1006
1007 memset(hw_info, 0, sizeof(struct vxge_hw_device_hw_info));
1008
1009 toc = __vxge_hw_device_toc_get(bar0);
1010 if (toc == NULL) {
1011 status = VXGE_HW_ERR_CRITICAL;
1012 goto exit;
1013 }
1014
1015 val64 = readq(&toc->toc_common_pointer);
1016 common_reg = bar0 + val64;
1017
1018 status = __vxge_hw_device_vpath_reset_in_prog_check(
1019 (u64 __iomem *)&common_reg->vpath_rst_in_prog);
1020 if (status != VXGE_HW_OK)
1021 goto exit;
1022
1023 hw_info->vpath_mask = readq(&common_reg->vpath_assignments);
1024
1025 val64 = readq(&common_reg->host_type_assignments);
1026
1027 hw_info->host_type =
1028 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
1029
1030 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1031 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1032 continue;
1033
1034 val64 = readq(&toc->toc_vpmgmt_pointer[i]);
1035
1036 vpmgmt_reg = bar0 + val64;
1037
1038 hw_info->func_id = __vxge_hw_vpath_func_id_get(vpmgmt_reg);
1039 if (__vxge_hw_device_access_rights_get(hw_info->host_type,
1040 hw_info->func_id) &
1041 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) {
1042
1043 val64 = readq(&toc->toc_mrpcim_pointer);
1044
1045 mrpcim_reg = bar0 + val64;
1046
1047 writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask);
1048 wmb();
1049 }
1050
1051 val64 = readq(&toc->toc_vpath_pointer[i]);
1052
1053 spin_lock_init(&vpath.lock);
1054 vpath.vp_reg = bar0 + val64;
1055 vpath.vp_open = VXGE_HW_VP_NOT_OPEN;
1056
1057 status = __vxge_hw_vpath_pci_func_mode_get(&vpath, hw_info);
1058 if (status != VXGE_HW_OK)
1059 goto exit;
1060
1061 status = __vxge_hw_vpath_fw_ver_get(&vpath, hw_info);
1062 if (status != VXGE_HW_OK)
1063 goto exit;
1064
1065 status = __vxge_hw_vpath_card_info_get(&vpath, hw_info);
1066 if (status != VXGE_HW_OK)
1067 goto exit;
1068
1069 break;
1070 }
1071
1072 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1073 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1074 continue;
1075
1076 val64 = readq(&toc->toc_vpath_pointer[i]);
1077 vpath.vp_reg = bar0 + val64;
1078 vpath.vp_open = VXGE_HW_VP_NOT_OPEN;
1079
1080 status = __vxge_hw_vpath_addr_get(&vpath,
1081 hw_info->mac_addrs[i],
1082 hw_info->mac_addr_masks[i]);
1083 if (status != VXGE_HW_OK)
1084 goto exit;
1085 }
1086 exit:
1087 return status;
1088 }
1089
1090 /*
1091 * __vxge_hw_blockpool_destroy - Deallocates the block pool
1092 */
__vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool * blockpool)1093 static void __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool)
1094 {
1095 struct __vxge_hw_device *hldev;
1096 struct list_head *p, *n;
1097
1098 if (!blockpool)
1099 return;
1100
1101 hldev = blockpool->hldev;
1102
1103 list_for_each_safe(p, n, &blockpool->free_block_list) {
1104 pci_unmap_single(hldev->pdev,
1105 ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
1106 ((struct __vxge_hw_blockpool_entry *)p)->length,
1107 PCI_DMA_BIDIRECTIONAL);
1108
1109 vxge_os_dma_free(hldev->pdev,
1110 ((struct __vxge_hw_blockpool_entry *)p)->memblock,
1111 &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
1112
1113 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
1114 kfree(p);
1115 blockpool->pool_size--;
1116 }
1117
1118 list_for_each_safe(p, n, &blockpool->free_entry_list) {
1119 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
1120 kfree((void *)p);
1121 }
1122
1123 return;
1124 }
1125
1126 /*
1127 * __vxge_hw_blockpool_create - Create block pool
1128 */
1129 static enum vxge_hw_status
__vxge_hw_blockpool_create(struct __vxge_hw_device * hldev,struct __vxge_hw_blockpool * blockpool,u32 pool_size,u32 pool_max)1130 __vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
1131 struct __vxge_hw_blockpool *blockpool,
1132 u32 pool_size,
1133 u32 pool_max)
1134 {
1135 u32 i;
1136 struct __vxge_hw_blockpool_entry *entry = NULL;
1137 void *memblock;
1138 dma_addr_t dma_addr;
1139 struct pci_dev *dma_handle;
1140 struct pci_dev *acc_handle;
1141 enum vxge_hw_status status = VXGE_HW_OK;
1142
1143 if (blockpool == NULL) {
1144 status = VXGE_HW_FAIL;
1145 goto blockpool_create_exit;
1146 }
1147
1148 blockpool->hldev = hldev;
1149 blockpool->block_size = VXGE_HW_BLOCK_SIZE;
1150 blockpool->pool_size = 0;
1151 blockpool->pool_max = pool_max;
1152 blockpool->req_out = 0;
1153
1154 INIT_LIST_HEAD(&blockpool->free_block_list);
1155 INIT_LIST_HEAD(&blockpool->free_entry_list);
1156
1157 for (i = 0; i < pool_size + pool_max; i++) {
1158 entry = kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
1159 GFP_KERNEL);
1160 if (entry == NULL) {
1161 __vxge_hw_blockpool_destroy(blockpool);
1162 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1163 goto blockpool_create_exit;
1164 }
1165 list_add(&entry->item, &blockpool->free_entry_list);
1166 }
1167
1168 for (i = 0; i < pool_size; i++) {
1169 memblock = vxge_os_dma_malloc(
1170 hldev->pdev,
1171 VXGE_HW_BLOCK_SIZE,
1172 &dma_handle,
1173 &acc_handle);
1174 if (memblock == NULL) {
1175 __vxge_hw_blockpool_destroy(blockpool);
1176 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1177 goto blockpool_create_exit;
1178 }
1179
1180 dma_addr = pci_map_single(hldev->pdev, memblock,
1181 VXGE_HW_BLOCK_SIZE, PCI_DMA_BIDIRECTIONAL);
1182 if (unlikely(pci_dma_mapping_error(hldev->pdev,
1183 dma_addr))) {
1184 vxge_os_dma_free(hldev->pdev, memblock, &acc_handle);
1185 __vxge_hw_blockpool_destroy(blockpool);
1186 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1187 goto blockpool_create_exit;
1188 }
1189
1190 if (!list_empty(&blockpool->free_entry_list))
1191 entry = (struct __vxge_hw_blockpool_entry *)
1192 list_first_entry(&blockpool->free_entry_list,
1193 struct __vxge_hw_blockpool_entry,
1194 item);
1195
1196 if (entry == NULL)
1197 entry =
1198 kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
1199 GFP_KERNEL);
1200 if (entry != NULL) {
1201 list_del(&entry->item);
1202 entry->length = VXGE_HW_BLOCK_SIZE;
1203 entry->memblock = memblock;
1204 entry->dma_addr = dma_addr;
1205 entry->acc_handle = acc_handle;
1206 entry->dma_handle = dma_handle;
1207 list_add(&entry->item,
1208 &blockpool->free_block_list);
1209 blockpool->pool_size++;
1210 } else {
1211 __vxge_hw_blockpool_destroy(blockpool);
1212 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1213 goto blockpool_create_exit;
1214 }
1215 }
1216
1217 blockpool_create_exit:
1218 return status;
1219 }
1220
1221 /*
1222 * __vxge_hw_device_fifo_config_check - Check fifo configuration.
1223 * Check the fifo configuration
1224 */
1225 static enum vxge_hw_status
__vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config * fifo_config)1226 __vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config)
1227 {
1228 if ((fifo_config->fifo_blocks < VXGE_HW_MIN_FIFO_BLOCKS) ||
1229 (fifo_config->fifo_blocks > VXGE_HW_MAX_FIFO_BLOCKS))
1230 return VXGE_HW_BADCFG_FIFO_BLOCKS;
1231
1232 return VXGE_HW_OK;
1233 }
1234
1235 /*
1236 * __vxge_hw_device_vpath_config_check - Check vpath configuration.
1237 * Check the vpath configuration
1238 */
1239 static enum vxge_hw_status
__vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config * vp_config)1240 __vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config)
1241 {
1242 enum vxge_hw_status status;
1243
1244 if ((vp_config->min_bandwidth < VXGE_HW_VPATH_BANDWIDTH_MIN) ||
1245 (vp_config->min_bandwidth > VXGE_HW_VPATH_BANDWIDTH_MAX))
1246 return VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH;
1247
1248 status = __vxge_hw_device_fifo_config_check(&vp_config->fifo);
1249 if (status != VXGE_HW_OK)
1250 return status;
1251
1252 if ((vp_config->mtu != VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) &&
1253 ((vp_config->mtu < VXGE_HW_VPATH_MIN_INITIAL_MTU) ||
1254 (vp_config->mtu > VXGE_HW_VPATH_MAX_INITIAL_MTU)))
1255 return VXGE_HW_BADCFG_VPATH_MTU;
1256
1257 if ((vp_config->rpa_strip_vlan_tag !=
1258 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) &&
1259 (vp_config->rpa_strip_vlan_tag !=
1260 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) &&
1261 (vp_config->rpa_strip_vlan_tag !=
1262 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE))
1263 return VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG;
1264
1265 return VXGE_HW_OK;
1266 }
1267
1268 /*
1269 * __vxge_hw_device_config_check - Check device configuration.
1270 * Check the device configuration
1271 */
1272 static enum vxge_hw_status
__vxge_hw_device_config_check(struct vxge_hw_device_config * new_config)1273 __vxge_hw_device_config_check(struct vxge_hw_device_config *new_config)
1274 {
1275 u32 i;
1276 enum vxge_hw_status status;
1277
1278 if ((new_config->intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
1279 (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
1280 (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
1281 (new_config->intr_mode != VXGE_HW_INTR_MODE_DEF))
1282 return VXGE_HW_BADCFG_INTR_MODE;
1283
1284 if ((new_config->rts_mac_en != VXGE_HW_RTS_MAC_DISABLE) &&
1285 (new_config->rts_mac_en != VXGE_HW_RTS_MAC_ENABLE))
1286 return VXGE_HW_BADCFG_RTS_MAC_EN;
1287
1288 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1289 status = __vxge_hw_device_vpath_config_check(
1290 &new_config->vp_config[i]);
1291 if (status != VXGE_HW_OK)
1292 return status;
1293 }
1294
1295 return VXGE_HW_OK;
1296 }
1297
1298 /*
1299 * vxge_hw_device_initialize - Initialize Titan device.
1300 * Initialize Titan device. Note that all the arguments of this public API
1301 * are 'IN', including @hldev. Driver cooperates with
1302 * OS to find new Titan device, locate its PCI and memory spaces.
1303 *
1304 * When done, the driver allocates sizeof(struct __vxge_hw_device) bytes for HW
1305 * to enable the latter to perform Titan hardware initialization.
1306 */
1307 enum vxge_hw_status
vxge_hw_device_initialize(struct __vxge_hw_device ** devh,struct vxge_hw_device_attr * attr,struct vxge_hw_device_config * device_config)1308 vxge_hw_device_initialize(
1309 struct __vxge_hw_device **devh,
1310 struct vxge_hw_device_attr *attr,
1311 struct vxge_hw_device_config *device_config)
1312 {
1313 u32 i;
1314 u32 nblocks = 0;
1315 struct __vxge_hw_device *hldev = NULL;
1316 enum vxge_hw_status status = VXGE_HW_OK;
1317
1318 status = __vxge_hw_device_config_check(device_config);
1319 if (status != VXGE_HW_OK)
1320 goto exit;
1321
1322 hldev = vzalloc(sizeof(struct __vxge_hw_device));
1323 if (hldev == NULL) {
1324 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1325 goto exit;
1326 }
1327
1328 hldev->magic = VXGE_HW_DEVICE_MAGIC;
1329
1330 vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_ALL);
1331
1332 /* apply config */
1333 memcpy(&hldev->config, device_config,
1334 sizeof(struct vxge_hw_device_config));
1335
1336 hldev->bar0 = attr->bar0;
1337 hldev->pdev = attr->pdev;
1338
1339 hldev->uld_callbacks = attr->uld_callbacks;
1340
1341 __vxge_hw_device_pci_e_init(hldev);
1342
1343 status = __vxge_hw_device_reg_addr_get(hldev);
1344 if (status != VXGE_HW_OK) {
1345 vfree(hldev);
1346 goto exit;
1347 }
1348
1349 __vxge_hw_device_host_info_get(hldev);
1350
1351 /* Incrementing for stats blocks */
1352 nblocks++;
1353
1354 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1355 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
1356 continue;
1357
1358 if (device_config->vp_config[i].ring.enable ==
1359 VXGE_HW_RING_ENABLE)
1360 nblocks += device_config->vp_config[i].ring.ring_blocks;
1361
1362 if (device_config->vp_config[i].fifo.enable ==
1363 VXGE_HW_FIFO_ENABLE)
1364 nblocks += device_config->vp_config[i].fifo.fifo_blocks;
1365 nblocks++;
1366 }
1367
1368 if (__vxge_hw_blockpool_create(hldev,
1369 &hldev->block_pool,
1370 device_config->dma_blockpool_initial + nblocks,
1371 device_config->dma_blockpool_max + nblocks) != VXGE_HW_OK) {
1372
1373 vxge_hw_device_terminate(hldev);
1374 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1375 goto exit;
1376 }
1377
1378 status = __vxge_hw_device_initialize(hldev);
1379 if (status != VXGE_HW_OK) {
1380 vxge_hw_device_terminate(hldev);
1381 goto exit;
1382 }
1383
1384 *devh = hldev;
1385 exit:
1386 return status;
1387 }
1388
1389 /*
1390 * vxge_hw_device_terminate - Terminate Titan device.
1391 * Terminate HW device.
1392 */
1393 void
vxge_hw_device_terminate(struct __vxge_hw_device * hldev)1394 vxge_hw_device_terminate(struct __vxge_hw_device *hldev)
1395 {
1396 vxge_assert(hldev->magic == VXGE_HW_DEVICE_MAGIC);
1397
1398 hldev->magic = VXGE_HW_DEVICE_DEAD;
1399 __vxge_hw_blockpool_destroy(&hldev->block_pool);
1400 vfree(hldev);
1401 }
1402
1403 /*
1404 * __vxge_hw_vpath_stats_access - Get the statistics from the given location
1405 * and offset and perform an operation
1406 */
1407 static enum vxge_hw_status
__vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath * vpath,u32 operation,u32 offset,u64 * stat)1408 __vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath,
1409 u32 operation, u32 offset, u64 *stat)
1410 {
1411 u64 val64;
1412 enum vxge_hw_status status = VXGE_HW_OK;
1413 struct vxge_hw_vpath_reg __iomem *vp_reg;
1414
1415 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1416 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1417 goto vpath_stats_access_exit;
1418 }
1419
1420 vp_reg = vpath->vp_reg;
1421
1422 val64 = VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(operation) |
1423 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE |
1424 VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset);
1425
1426 status = __vxge_hw_pio_mem_write64(val64,
1427 &vp_reg->xmac_stats_access_cmd,
1428 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE,
1429 vpath->hldev->config.device_poll_millis);
1430 if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1431 *stat = readq(&vp_reg->xmac_stats_access_data);
1432 else
1433 *stat = 0;
1434
1435 vpath_stats_access_exit:
1436 return status;
1437 }
1438
1439 /*
1440 * __vxge_hw_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
1441 */
1442 static enum vxge_hw_status
__vxge_hw_vpath_xmac_tx_stats_get(struct __vxge_hw_virtualpath * vpath,struct vxge_hw_xmac_vpath_tx_stats * vpath_tx_stats)1443 __vxge_hw_vpath_xmac_tx_stats_get(struct __vxge_hw_virtualpath *vpath,
1444 struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats)
1445 {
1446 u64 *val64;
1447 int i;
1448 u32 offset = VXGE_HW_STATS_VPATH_TX_OFFSET;
1449 enum vxge_hw_status status = VXGE_HW_OK;
1450
1451 val64 = (u64 *)vpath_tx_stats;
1452
1453 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1454 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1455 goto exit;
1456 }
1457
1458 for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_tx_stats) / 8; i++) {
1459 status = __vxge_hw_vpath_stats_access(vpath,
1460 VXGE_HW_STATS_OP_READ,
1461 offset, val64);
1462 if (status != VXGE_HW_OK)
1463 goto exit;
1464 offset++;
1465 val64++;
1466 }
1467 exit:
1468 return status;
1469 }
1470
1471 /*
1472 * __vxge_hw_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
1473 */
1474 static enum vxge_hw_status
__vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath * vpath,struct vxge_hw_xmac_vpath_rx_stats * vpath_rx_stats)1475 __vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath,
1476 struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats)
1477 {
1478 u64 *val64;
1479 enum vxge_hw_status status = VXGE_HW_OK;
1480 int i;
1481 u32 offset = VXGE_HW_STATS_VPATH_RX_OFFSET;
1482 val64 = (u64 *) vpath_rx_stats;
1483
1484 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1485 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1486 goto exit;
1487 }
1488 for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_rx_stats) / 8; i++) {
1489 status = __vxge_hw_vpath_stats_access(vpath,
1490 VXGE_HW_STATS_OP_READ,
1491 offset >> 3, val64);
1492 if (status != VXGE_HW_OK)
1493 goto exit;
1494
1495 offset += 8;
1496 val64++;
1497 }
1498 exit:
1499 return status;
1500 }
1501
1502 /*
1503 * __vxge_hw_vpath_stats_get - Get the vpath hw statistics.
1504 */
1505 static enum vxge_hw_status
__vxge_hw_vpath_stats_get(struct __vxge_hw_virtualpath * vpath,struct vxge_hw_vpath_stats_hw_info * hw_stats)1506 __vxge_hw_vpath_stats_get(struct __vxge_hw_virtualpath *vpath,
1507 struct vxge_hw_vpath_stats_hw_info *hw_stats)
1508 {
1509 u64 val64;
1510 enum vxge_hw_status status = VXGE_HW_OK;
1511 struct vxge_hw_vpath_reg __iomem *vp_reg;
1512
1513 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1514 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1515 goto exit;
1516 }
1517 vp_reg = vpath->vp_reg;
1518
1519 val64 = readq(&vp_reg->vpath_debug_stats0);
1520 hw_stats->ini_num_mwr_sent =
1521 (u32)VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
1522
1523 val64 = readq(&vp_reg->vpath_debug_stats1);
1524 hw_stats->ini_num_mrd_sent =
1525 (u32)VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
1526
1527 val64 = readq(&vp_reg->vpath_debug_stats2);
1528 hw_stats->ini_num_cpl_rcvd =
1529 (u32)VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
1530
1531 val64 = readq(&vp_reg->vpath_debug_stats3);
1532 hw_stats->ini_num_mwr_byte_sent =
1533 VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
1534
1535 val64 = readq(&vp_reg->vpath_debug_stats4);
1536 hw_stats->ini_num_cpl_byte_rcvd =
1537 VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
1538
1539 val64 = readq(&vp_reg->vpath_debug_stats5);
1540 hw_stats->wrcrdtarb_xoff =
1541 (u32)VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
1542
1543 val64 = readq(&vp_reg->vpath_debug_stats6);
1544 hw_stats->rdcrdtarb_xoff =
1545 (u32)VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
1546
1547 val64 = readq(&vp_reg->vpath_genstats_count01);
1548 hw_stats->vpath_genstats_count0 =
1549 (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(
1550 val64);
1551
1552 val64 = readq(&vp_reg->vpath_genstats_count01);
1553 hw_stats->vpath_genstats_count1 =
1554 (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(
1555 val64);
1556
1557 val64 = readq(&vp_reg->vpath_genstats_count23);
1558 hw_stats->vpath_genstats_count2 =
1559 (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(
1560 val64);
1561
1562 val64 = readq(&vp_reg->vpath_genstats_count01);
1563 hw_stats->vpath_genstats_count3 =
1564 (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(
1565 val64);
1566
1567 val64 = readq(&vp_reg->vpath_genstats_count4);
1568 hw_stats->vpath_genstats_count4 =
1569 (u32)VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(
1570 val64);
1571
1572 val64 = readq(&vp_reg->vpath_genstats_count5);
1573 hw_stats->vpath_genstats_count5 =
1574 (u32)VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(
1575 val64);
1576
1577 status = __vxge_hw_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats);
1578 if (status != VXGE_HW_OK)
1579 goto exit;
1580
1581 status = __vxge_hw_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats);
1582 if (status != VXGE_HW_OK)
1583 goto exit;
1584
1585 VXGE_HW_VPATH_STATS_PIO_READ(
1586 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET);
1587
1588 hw_stats->prog_event_vnum0 =
1589 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
1590
1591 hw_stats->prog_event_vnum1 =
1592 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
1593
1594 VXGE_HW_VPATH_STATS_PIO_READ(
1595 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET);
1596
1597 hw_stats->prog_event_vnum2 =
1598 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
1599
1600 hw_stats->prog_event_vnum3 =
1601 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
1602
1603 val64 = readq(&vp_reg->rx_multi_cast_stats);
1604 hw_stats->rx_multi_cast_frame_discard =
1605 (u16)VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
1606
1607 val64 = readq(&vp_reg->rx_frm_transferred);
1608 hw_stats->rx_frm_transferred =
1609 (u32)VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
1610
1611 val64 = readq(&vp_reg->rxd_returned);
1612 hw_stats->rxd_returned =
1613 (u16)VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(val64);
1614
1615 val64 = readq(&vp_reg->dbg_stats_rx_mpa);
1616 hw_stats->rx_mpa_len_fail_frms =
1617 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
1618 hw_stats->rx_mpa_mrk_fail_frms =
1619 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
1620 hw_stats->rx_mpa_crc_fail_frms =
1621 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
1622
1623 val64 = readq(&vp_reg->dbg_stats_rx_fau);
1624 hw_stats->rx_permitted_frms =
1625 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
1626 hw_stats->rx_vp_reset_discarded_frms =
1627 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
1628 hw_stats->rx_wol_frms =
1629 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
1630
1631 val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);
1632 hw_stats->tx_vp_reset_discarded_frms =
1633 (u16)VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(
1634 val64);
1635 exit:
1636 return status;
1637 }
1638
1639 /*
1640 * vxge_hw_device_stats_get - Get the device hw statistics.
1641 * Returns the vpath h/w stats for the device.
1642 */
1643 enum vxge_hw_status
vxge_hw_device_stats_get(struct __vxge_hw_device * hldev,struct vxge_hw_device_stats_hw_info * hw_stats)1644 vxge_hw_device_stats_get(struct __vxge_hw_device *hldev,
1645 struct vxge_hw_device_stats_hw_info *hw_stats)
1646 {
1647 u32 i;
1648 enum vxge_hw_status status = VXGE_HW_OK;
1649
1650 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1651 if (!(hldev->vpaths_deployed & vxge_mBIT(i)) ||
1652 (hldev->virtual_paths[i].vp_open ==
1653 VXGE_HW_VP_NOT_OPEN))
1654 continue;
1655
1656 memcpy(hldev->virtual_paths[i].hw_stats_sav,
1657 hldev->virtual_paths[i].hw_stats,
1658 sizeof(struct vxge_hw_vpath_stats_hw_info));
1659
1660 status = __vxge_hw_vpath_stats_get(
1661 &hldev->virtual_paths[i],
1662 hldev->virtual_paths[i].hw_stats);
1663 }
1664
1665 memcpy(hw_stats, &hldev->stats.hw_dev_info_stats,
1666 sizeof(struct vxge_hw_device_stats_hw_info));
1667
1668 return status;
1669 }
1670
1671 /*
1672 * vxge_hw_driver_stats_get - Get the device sw statistics.
1673 * Returns the vpath s/w stats for the device.
1674 */
vxge_hw_driver_stats_get(struct __vxge_hw_device * hldev,struct vxge_hw_device_stats_sw_info * sw_stats)1675 enum vxge_hw_status vxge_hw_driver_stats_get(
1676 struct __vxge_hw_device *hldev,
1677 struct vxge_hw_device_stats_sw_info *sw_stats)
1678 {
1679 memcpy(sw_stats, &hldev->stats.sw_dev_info_stats,
1680 sizeof(struct vxge_hw_device_stats_sw_info));
1681
1682 return VXGE_HW_OK;
1683 }
1684
1685 /*
1686 * vxge_hw_mrpcim_stats_access - Access the statistics from the given location
1687 * and offset and perform an operation
1688 * Get the statistics from the given location and offset.
1689 */
1690 enum vxge_hw_status
vxge_hw_mrpcim_stats_access(struct __vxge_hw_device * hldev,u32 operation,u32 location,u32 offset,u64 * stat)1691 vxge_hw_mrpcim_stats_access(struct __vxge_hw_device *hldev,
1692 u32 operation, u32 location, u32 offset, u64 *stat)
1693 {
1694 u64 val64;
1695 enum vxge_hw_status status = VXGE_HW_OK;
1696
1697 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1698 hldev->func_id);
1699 if (status != VXGE_HW_OK)
1700 goto exit;
1701
1702 val64 = VXGE_HW_XMAC_STATS_SYS_CMD_OP(operation) |
1703 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE |
1704 VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(location) |
1705 VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset);
1706
1707 status = __vxge_hw_pio_mem_write64(val64,
1708 &hldev->mrpcim_reg->xmac_stats_sys_cmd,
1709 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE,
1710 hldev->config.device_poll_millis);
1711
1712 if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1713 *stat = readq(&hldev->mrpcim_reg->xmac_stats_sys_data);
1714 else
1715 *stat = 0;
1716 exit:
1717 return status;
1718 }
1719
1720 /*
1721 * vxge_hw_device_xmac_aggr_stats_get - Get the Statistics on aggregate port
1722 * Get the Statistics on aggregate port
1723 */
1724 static enum vxge_hw_status
vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device * hldev,u32 port,struct vxge_hw_xmac_aggr_stats * aggr_stats)1725 vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device *hldev, u32 port,
1726 struct vxge_hw_xmac_aggr_stats *aggr_stats)
1727 {
1728 u64 *val64;
1729 int i;
1730 u32 offset = VXGE_HW_STATS_AGGRn_OFFSET;
1731 enum vxge_hw_status status = VXGE_HW_OK;
1732
1733 val64 = (u64 *)aggr_stats;
1734
1735 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1736 hldev->func_id);
1737 if (status != VXGE_HW_OK)
1738 goto exit;
1739
1740 for (i = 0; i < sizeof(struct vxge_hw_xmac_aggr_stats) / 8; i++) {
1741 status = vxge_hw_mrpcim_stats_access(hldev,
1742 VXGE_HW_STATS_OP_READ,
1743 VXGE_HW_STATS_LOC_AGGR,
1744 ((offset + (104 * port)) >> 3), val64);
1745 if (status != VXGE_HW_OK)
1746 goto exit;
1747
1748 offset += 8;
1749 val64++;
1750 }
1751 exit:
1752 return status;
1753 }
1754
1755 /*
1756 * vxge_hw_device_xmac_port_stats_get - Get the Statistics on a port
1757 * Get the Statistics on port
1758 */
1759 static enum vxge_hw_status
vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device * hldev,u32 port,struct vxge_hw_xmac_port_stats * port_stats)1760 vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device *hldev, u32 port,
1761 struct vxge_hw_xmac_port_stats *port_stats)
1762 {
1763 u64 *val64;
1764 enum vxge_hw_status status = VXGE_HW_OK;
1765 int i;
1766 u32 offset = 0x0;
1767 val64 = (u64 *) port_stats;
1768
1769 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1770 hldev->func_id);
1771 if (status != VXGE_HW_OK)
1772 goto exit;
1773
1774 for (i = 0; i < sizeof(struct vxge_hw_xmac_port_stats) / 8; i++) {
1775 status = vxge_hw_mrpcim_stats_access(hldev,
1776 VXGE_HW_STATS_OP_READ,
1777 VXGE_HW_STATS_LOC_AGGR,
1778 ((offset + (608 * port)) >> 3), val64);
1779 if (status != VXGE_HW_OK)
1780 goto exit;
1781
1782 offset += 8;
1783 val64++;
1784 }
1785
1786 exit:
1787 return status;
1788 }
1789
1790 /*
1791 * vxge_hw_device_xmac_stats_get - Get the XMAC Statistics
1792 * Get the XMAC Statistics
1793 */
1794 enum vxge_hw_status
vxge_hw_device_xmac_stats_get(struct __vxge_hw_device * hldev,struct vxge_hw_xmac_stats * xmac_stats)1795 vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *hldev,
1796 struct vxge_hw_xmac_stats *xmac_stats)
1797 {
1798 enum vxge_hw_status status = VXGE_HW_OK;
1799 u32 i;
1800
1801 status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1802 0, &xmac_stats->aggr_stats[0]);
1803 if (status != VXGE_HW_OK)
1804 goto exit;
1805
1806 status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1807 1, &xmac_stats->aggr_stats[1]);
1808 if (status != VXGE_HW_OK)
1809 goto exit;
1810
1811 for (i = 0; i <= VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
1812
1813 status = vxge_hw_device_xmac_port_stats_get(hldev,
1814 i, &xmac_stats->port_stats[i]);
1815 if (status != VXGE_HW_OK)
1816 goto exit;
1817 }
1818
1819 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1820
1821 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
1822 continue;
1823
1824 status = __vxge_hw_vpath_xmac_tx_stats_get(
1825 &hldev->virtual_paths[i],
1826 &xmac_stats->vpath_tx_stats[i]);
1827 if (status != VXGE_HW_OK)
1828 goto exit;
1829
1830 status = __vxge_hw_vpath_xmac_rx_stats_get(
1831 &hldev->virtual_paths[i],
1832 &xmac_stats->vpath_rx_stats[i]);
1833 if (status != VXGE_HW_OK)
1834 goto exit;
1835 }
1836 exit:
1837 return status;
1838 }
1839
1840 /*
1841 * vxge_hw_device_debug_set - Set the debug module, level and timestamp
1842 * This routine is used to dynamically change the debug output
1843 */
vxge_hw_device_debug_set(struct __vxge_hw_device * hldev,enum vxge_debug_level level,u32 mask)1844 void vxge_hw_device_debug_set(struct __vxge_hw_device *hldev,
1845 enum vxge_debug_level level, u32 mask)
1846 {
1847 if (hldev == NULL)
1848 return;
1849
1850 #if defined(VXGE_DEBUG_TRACE_MASK) || \
1851 defined(VXGE_DEBUG_ERR_MASK)
1852 hldev->debug_module_mask = mask;
1853 hldev->debug_level = level;
1854 #endif
1855
1856 #if defined(VXGE_DEBUG_ERR_MASK)
1857 hldev->level_err = level & VXGE_ERR;
1858 #endif
1859
1860 #if defined(VXGE_DEBUG_TRACE_MASK)
1861 hldev->level_trace = level & VXGE_TRACE;
1862 #endif
1863 }
1864
1865 /*
1866 * vxge_hw_device_error_level_get - Get the error level
1867 * This routine returns the current error level set
1868 */
vxge_hw_device_error_level_get(struct __vxge_hw_device * hldev)1869 u32 vxge_hw_device_error_level_get(struct __vxge_hw_device *hldev)
1870 {
1871 #if defined(VXGE_DEBUG_ERR_MASK)
1872 if (hldev == NULL)
1873 return VXGE_ERR;
1874 else
1875 return hldev->level_err;
1876 #else
1877 return 0;
1878 #endif
1879 }
1880
1881 /*
1882 * vxge_hw_device_trace_level_get - Get the trace level
1883 * This routine returns the current trace level set
1884 */
vxge_hw_device_trace_level_get(struct __vxge_hw_device * hldev)1885 u32 vxge_hw_device_trace_level_get(struct __vxge_hw_device *hldev)
1886 {
1887 #if defined(VXGE_DEBUG_TRACE_MASK)
1888 if (hldev == NULL)
1889 return VXGE_TRACE;
1890 else
1891 return hldev->level_trace;
1892 #else
1893 return 0;
1894 #endif
1895 }
1896
1897 /*
1898 * vxge_hw_getpause_data -Pause frame frame generation and reception.
1899 * Returns the Pause frame generation and reception capability of the NIC.
1900 */
vxge_hw_device_getpause_data(struct __vxge_hw_device * hldev,u32 port,u32 * tx,u32 * rx)1901 enum vxge_hw_status vxge_hw_device_getpause_data(struct __vxge_hw_device *hldev,
1902 u32 port, u32 *tx, u32 *rx)
1903 {
1904 u64 val64;
1905 enum vxge_hw_status status = VXGE_HW_OK;
1906
1907 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1908 status = VXGE_HW_ERR_INVALID_DEVICE;
1909 goto exit;
1910 }
1911
1912 if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1913 status = VXGE_HW_ERR_INVALID_PORT;
1914 goto exit;
1915 }
1916
1917 if (!(hldev->access_rights & VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1918 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
1919 goto exit;
1920 }
1921
1922 val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1923 if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN)
1924 *tx = 1;
1925 if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN)
1926 *rx = 1;
1927 exit:
1928 return status;
1929 }
1930
1931 /*
1932 * vxge_hw_device_setpause_data - set/reset pause frame generation.
1933 * It can be used to set or reset Pause frame generation or reception
1934 * support of the NIC.
1935 */
vxge_hw_device_setpause_data(struct __vxge_hw_device * hldev,u32 port,u32 tx,u32 rx)1936 enum vxge_hw_status vxge_hw_device_setpause_data(struct __vxge_hw_device *hldev,
1937 u32 port, u32 tx, u32 rx)
1938 {
1939 u64 val64;
1940 enum vxge_hw_status status = VXGE_HW_OK;
1941
1942 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1943 status = VXGE_HW_ERR_INVALID_DEVICE;
1944 goto exit;
1945 }
1946
1947 if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1948 status = VXGE_HW_ERR_INVALID_PORT;
1949 goto exit;
1950 }
1951
1952 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1953 hldev->func_id);
1954 if (status != VXGE_HW_OK)
1955 goto exit;
1956
1957 val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1958 if (tx)
1959 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1960 else
1961 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1962 if (rx)
1963 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1964 else
1965 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1966
1967 writeq(val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1968 exit:
1969 return status;
1970 }
1971
vxge_hw_device_link_width_get(struct __vxge_hw_device * hldev)1972 u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *hldev)
1973 {
1974 struct pci_dev *dev = hldev->pdev;
1975 u16 lnk;
1976
1977 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
1978 return (lnk & VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4;
1979 }
1980
1981 /*
1982 * __vxge_hw_ring_block_memblock_idx - Return the memblock index
1983 * This function returns the index of memory block
1984 */
1985 static inline u32
__vxge_hw_ring_block_memblock_idx(u8 * block)1986 __vxge_hw_ring_block_memblock_idx(u8 *block)
1987 {
1988 return (u32)*((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET));
1989 }
1990
1991 /*
1992 * __vxge_hw_ring_block_memblock_idx_set - Sets the memblock index
1993 * This function sets index to a memory block
1994 */
1995 static inline void
__vxge_hw_ring_block_memblock_idx_set(u8 * block,u32 memblock_idx)1996 __vxge_hw_ring_block_memblock_idx_set(u8 *block, u32 memblock_idx)
1997 {
1998 *((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET)) = memblock_idx;
1999 }
2000
2001 /*
2002 * __vxge_hw_ring_block_next_pointer_set - Sets the next block pointer
2003 * in RxD block
2004 * Sets the next block pointer in RxD block
2005 */
2006 static inline void
__vxge_hw_ring_block_next_pointer_set(u8 * block,dma_addr_t dma_next)2007 __vxge_hw_ring_block_next_pointer_set(u8 *block, dma_addr_t dma_next)
2008 {
2009 *((u64 *)(block + VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET)) = dma_next;
2010 }
2011
2012 /*
2013 * __vxge_hw_ring_first_block_address_get - Returns the dma address of the
2014 * first block
2015 * Returns the dma address of the first RxD block
2016 */
__vxge_hw_ring_first_block_address_get(struct __vxge_hw_ring * ring)2017 static u64 __vxge_hw_ring_first_block_address_get(struct __vxge_hw_ring *ring)
2018 {
2019 struct vxge_hw_mempool_dma *dma_object;
2020
2021 dma_object = ring->mempool->memblocks_dma_arr;
2022 vxge_assert(dma_object != NULL);
2023
2024 return dma_object->addr;
2025 }
2026
2027 /*
2028 * __vxge_hw_ring_item_dma_addr - Return the dma address of an item
2029 * This function returns the dma address of a given item
2030 */
__vxge_hw_ring_item_dma_addr(struct vxge_hw_mempool * mempoolh,void * item)2031 static dma_addr_t __vxge_hw_ring_item_dma_addr(struct vxge_hw_mempool *mempoolh,
2032 void *item)
2033 {
2034 u32 memblock_idx;
2035 void *memblock;
2036 struct vxge_hw_mempool_dma *memblock_dma_object;
2037 ptrdiff_t dma_item_offset;
2038
2039 /* get owner memblock index */
2040 memblock_idx = __vxge_hw_ring_block_memblock_idx(item);
2041
2042 /* get owner memblock by memblock index */
2043 memblock = mempoolh->memblocks_arr[memblock_idx];
2044
2045 /* get memblock DMA object by memblock index */
2046 memblock_dma_object = mempoolh->memblocks_dma_arr + memblock_idx;
2047
2048 /* calculate offset in the memblock of this item */
2049 dma_item_offset = (u8 *)item - (u8 *)memblock;
2050
2051 return memblock_dma_object->addr + dma_item_offset;
2052 }
2053
2054 /*
2055 * __vxge_hw_ring_rxdblock_link - Link the RxD blocks
2056 * This function returns the dma address of a given item
2057 */
__vxge_hw_ring_rxdblock_link(struct vxge_hw_mempool * mempoolh,struct __vxge_hw_ring * ring,u32 from,u32 to)2058 static void __vxge_hw_ring_rxdblock_link(struct vxge_hw_mempool *mempoolh,
2059 struct __vxge_hw_ring *ring, u32 from,
2060 u32 to)
2061 {
2062 u8 *to_item , *from_item;
2063 dma_addr_t to_dma;
2064
2065 /* get "from" RxD block */
2066 from_item = mempoolh->items_arr[from];
2067 vxge_assert(from_item);
2068
2069 /* get "to" RxD block */
2070 to_item = mempoolh->items_arr[to];
2071 vxge_assert(to_item);
2072
2073 /* return address of the beginning of previous RxD block */
2074 to_dma = __vxge_hw_ring_item_dma_addr(mempoolh, to_item);
2075
2076 /* set next pointer for this RxD block to point on
2077 * previous item's DMA start address */
2078 __vxge_hw_ring_block_next_pointer_set(from_item, to_dma);
2079 }
2080
2081 /*
2082 * __vxge_hw_ring_mempool_item_alloc - Allocate List blocks for RxD
2083 * block callback
2084 * This function is callback passed to __vxge_hw_mempool_create to create memory
2085 * pool for RxD block
2086 */
2087 static void
__vxge_hw_ring_mempool_item_alloc(struct vxge_hw_mempool * mempoolh,u32 memblock_index,struct vxge_hw_mempool_dma * dma_object,u32 index,u32 is_last)2088 __vxge_hw_ring_mempool_item_alloc(struct vxge_hw_mempool *mempoolh,
2089 u32 memblock_index,
2090 struct vxge_hw_mempool_dma *dma_object,
2091 u32 index, u32 is_last)
2092 {
2093 u32 i;
2094 void *item = mempoolh->items_arr[index];
2095 struct __vxge_hw_ring *ring =
2096 (struct __vxge_hw_ring *)mempoolh->userdata;
2097
2098 /* format rxds array */
2099 for (i = 0; i < ring->rxds_per_block; i++) {
2100 void *rxdblock_priv;
2101 void *uld_priv;
2102 struct vxge_hw_ring_rxd_1 *rxdp;
2103
2104 u32 reserve_index = ring->channel.reserve_ptr -
2105 (index * ring->rxds_per_block + i + 1);
2106 u32 memblock_item_idx;
2107
2108 ring->channel.reserve_arr[reserve_index] = ((u8 *)item) +
2109 i * ring->rxd_size;
2110
2111 /* Note: memblock_item_idx is index of the item within
2112 * the memblock. For instance, in case of three RxD-blocks
2113 * per memblock this value can be 0, 1 or 2. */
2114 rxdblock_priv = __vxge_hw_mempool_item_priv(mempoolh,
2115 memblock_index, item,
2116 &memblock_item_idx);
2117
2118 rxdp = ring->channel.reserve_arr[reserve_index];
2119
2120 uld_priv = ((u8 *)rxdblock_priv + ring->rxd_priv_size * i);
2121
2122 /* pre-format Host_Control */
2123 rxdp->host_control = (u64)(size_t)uld_priv;
2124 }
2125
2126 __vxge_hw_ring_block_memblock_idx_set(item, memblock_index);
2127
2128 if (is_last) {
2129 /* link last one with first one */
2130 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index, 0);
2131 }
2132
2133 if (index > 0) {
2134 /* link this RxD block with previous one */
2135 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index - 1, index);
2136 }
2137 }
2138
2139 /*
2140 * __vxge_hw_ring_replenish - Initial replenish of RxDs
2141 * This function replenishes the RxDs from reserve array to work array
2142 */
2143 static enum vxge_hw_status
vxge_hw_ring_replenish(struct __vxge_hw_ring * ring)2144 vxge_hw_ring_replenish(struct __vxge_hw_ring *ring)
2145 {
2146 void *rxd;
2147 struct __vxge_hw_channel *channel;
2148 enum vxge_hw_status status = VXGE_HW_OK;
2149
2150 channel = &ring->channel;
2151
2152 while (vxge_hw_channel_dtr_count(channel) > 0) {
2153
2154 status = vxge_hw_ring_rxd_reserve(ring, &rxd);
2155
2156 vxge_assert(status == VXGE_HW_OK);
2157
2158 if (ring->rxd_init) {
2159 status = ring->rxd_init(rxd, channel->userdata);
2160 if (status != VXGE_HW_OK) {
2161 vxge_hw_ring_rxd_free(ring, rxd);
2162 goto exit;
2163 }
2164 }
2165
2166 vxge_hw_ring_rxd_post(ring, rxd);
2167 }
2168 status = VXGE_HW_OK;
2169 exit:
2170 return status;
2171 }
2172
2173 /*
2174 * __vxge_hw_channel_allocate - Allocate memory for channel
2175 * This function allocates required memory for the channel and various arrays
2176 * in the channel
2177 */
2178 static struct __vxge_hw_channel *
__vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle * vph,enum __vxge_hw_channel_type type,u32 length,u32 per_dtr_space,void * userdata)2179 __vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
2180 enum __vxge_hw_channel_type type,
2181 u32 length, u32 per_dtr_space,
2182 void *userdata)
2183 {
2184 struct __vxge_hw_channel *channel;
2185 struct __vxge_hw_device *hldev;
2186 int size = 0;
2187 u32 vp_id;
2188
2189 hldev = vph->vpath->hldev;
2190 vp_id = vph->vpath->vp_id;
2191
2192 switch (type) {
2193 case VXGE_HW_CHANNEL_TYPE_FIFO:
2194 size = sizeof(struct __vxge_hw_fifo);
2195 break;
2196 case VXGE_HW_CHANNEL_TYPE_RING:
2197 size = sizeof(struct __vxge_hw_ring);
2198 break;
2199 default:
2200 break;
2201 }
2202
2203 channel = kzalloc(size, GFP_KERNEL);
2204 if (channel == NULL)
2205 goto exit0;
2206 INIT_LIST_HEAD(&channel->item);
2207
2208 channel->common_reg = hldev->common_reg;
2209 channel->first_vp_id = hldev->first_vp_id;
2210 channel->type = type;
2211 channel->devh = hldev;
2212 channel->vph = vph;
2213 channel->userdata = userdata;
2214 channel->per_dtr_space = per_dtr_space;
2215 channel->length = length;
2216 channel->vp_id = vp_id;
2217
2218 channel->work_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2219 if (channel->work_arr == NULL)
2220 goto exit1;
2221
2222 channel->free_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2223 if (channel->free_arr == NULL)
2224 goto exit1;
2225 channel->free_ptr = length;
2226
2227 channel->reserve_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2228 if (channel->reserve_arr == NULL)
2229 goto exit1;
2230 channel->reserve_ptr = length;
2231 channel->reserve_top = 0;
2232
2233 channel->orig_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2234 if (channel->orig_arr == NULL)
2235 goto exit1;
2236
2237 return channel;
2238 exit1:
2239 __vxge_hw_channel_free(channel);
2240
2241 exit0:
2242 return NULL;
2243 }
2244
2245 /*
2246 * vxge_hw_blockpool_block_add - callback for vxge_os_dma_malloc_async
2247 * Adds a block to block pool
2248 */
vxge_hw_blockpool_block_add(struct __vxge_hw_device * devh,void * block_addr,u32 length,struct pci_dev * dma_h,struct pci_dev * acc_handle)2249 static void vxge_hw_blockpool_block_add(struct __vxge_hw_device *devh,
2250 void *block_addr,
2251 u32 length,
2252 struct pci_dev *dma_h,
2253 struct pci_dev *acc_handle)
2254 {
2255 struct __vxge_hw_blockpool *blockpool;
2256 struct __vxge_hw_blockpool_entry *entry = NULL;
2257 dma_addr_t dma_addr;
2258
2259 blockpool = &devh->block_pool;
2260
2261 if (block_addr == NULL) {
2262 blockpool->req_out--;
2263 goto exit;
2264 }
2265
2266 dma_addr = pci_map_single(devh->pdev, block_addr, length,
2267 PCI_DMA_BIDIRECTIONAL);
2268
2269 if (unlikely(pci_dma_mapping_error(devh->pdev, dma_addr))) {
2270 vxge_os_dma_free(devh->pdev, block_addr, &acc_handle);
2271 blockpool->req_out--;
2272 goto exit;
2273 }
2274
2275 if (!list_empty(&blockpool->free_entry_list))
2276 entry = (struct __vxge_hw_blockpool_entry *)
2277 list_first_entry(&blockpool->free_entry_list,
2278 struct __vxge_hw_blockpool_entry,
2279 item);
2280
2281 if (entry == NULL)
2282 entry = vmalloc(sizeof(struct __vxge_hw_blockpool_entry));
2283 else
2284 list_del(&entry->item);
2285
2286 if (entry) {
2287 entry->length = length;
2288 entry->memblock = block_addr;
2289 entry->dma_addr = dma_addr;
2290 entry->acc_handle = acc_handle;
2291 entry->dma_handle = dma_h;
2292 list_add(&entry->item, &blockpool->free_block_list);
2293 blockpool->pool_size++;
2294 }
2295
2296 blockpool->req_out--;
2297
2298 exit:
2299 return;
2300 }
2301
2302 static inline void
vxge_os_dma_malloc_async(struct pci_dev * pdev,void * devh,unsigned long size)2303 vxge_os_dma_malloc_async(struct pci_dev *pdev, void *devh, unsigned long size)
2304 {
2305 gfp_t flags;
2306 void *vaddr;
2307
2308 if (in_interrupt())
2309 flags = GFP_ATOMIC | GFP_DMA;
2310 else
2311 flags = GFP_KERNEL | GFP_DMA;
2312
2313 vaddr = kmalloc((size), flags);
2314
2315 vxge_hw_blockpool_block_add(devh, vaddr, size, pdev, pdev);
2316 }
2317
2318 /*
2319 * __vxge_hw_blockpool_blocks_add - Request additional blocks
2320 */
2321 static
__vxge_hw_blockpool_blocks_add(struct __vxge_hw_blockpool * blockpool)2322 void __vxge_hw_blockpool_blocks_add(struct __vxge_hw_blockpool *blockpool)
2323 {
2324 u32 nreq = 0, i;
2325
2326 if ((blockpool->pool_size + blockpool->req_out) <
2327 VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE) {
2328 nreq = VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE;
2329 blockpool->req_out += nreq;
2330 }
2331
2332 for (i = 0; i < nreq; i++)
2333 vxge_os_dma_malloc_async(
2334 (blockpool->hldev)->pdev,
2335 blockpool->hldev, VXGE_HW_BLOCK_SIZE);
2336 }
2337
2338 /*
2339 * __vxge_hw_blockpool_malloc - Allocate a memory block from pool
2340 * Allocates a block of memory of given size, either from block pool
2341 * or by calling vxge_os_dma_malloc()
2342 */
__vxge_hw_blockpool_malloc(struct __vxge_hw_device * devh,u32 size,struct vxge_hw_mempool_dma * dma_object)2343 static void *__vxge_hw_blockpool_malloc(struct __vxge_hw_device *devh, u32 size,
2344 struct vxge_hw_mempool_dma *dma_object)
2345 {
2346 struct __vxge_hw_blockpool_entry *entry = NULL;
2347 struct __vxge_hw_blockpool *blockpool;
2348 void *memblock = NULL;
2349
2350 blockpool = &devh->block_pool;
2351
2352 if (size != blockpool->block_size) {
2353
2354 memblock = vxge_os_dma_malloc(devh->pdev, size,
2355 &dma_object->handle,
2356 &dma_object->acc_handle);
2357
2358 if (!memblock)
2359 goto exit;
2360
2361 dma_object->addr = pci_map_single(devh->pdev, memblock, size,
2362 PCI_DMA_BIDIRECTIONAL);
2363
2364 if (unlikely(pci_dma_mapping_error(devh->pdev,
2365 dma_object->addr))) {
2366 vxge_os_dma_free(devh->pdev, memblock,
2367 &dma_object->acc_handle);
2368 goto exit;
2369 }
2370
2371 } else {
2372
2373 if (!list_empty(&blockpool->free_block_list))
2374 entry = (struct __vxge_hw_blockpool_entry *)
2375 list_first_entry(&blockpool->free_block_list,
2376 struct __vxge_hw_blockpool_entry,
2377 item);
2378
2379 if (entry != NULL) {
2380 list_del(&entry->item);
2381 dma_object->addr = entry->dma_addr;
2382 dma_object->handle = entry->dma_handle;
2383 dma_object->acc_handle = entry->acc_handle;
2384 memblock = entry->memblock;
2385
2386 list_add(&entry->item,
2387 &blockpool->free_entry_list);
2388 blockpool->pool_size--;
2389 }
2390
2391 if (memblock != NULL)
2392 __vxge_hw_blockpool_blocks_add(blockpool);
2393 }
2394 exit:
2395 return memblock;
2396 }
2397
2398 /*
2399 * __vxge_hw_blockpool_blocks_remove - Free additional blocks
2400 */
2401 static void
__vxge_hw_blockpool_blocks_remove(struct __vxge_hw_blockpool * blockpool)2402 __vxge_hw_blockpool_blocks_remove(struct __vxge_hw_blockpool *blockpool)
2403 {
2404 struct list_head *p, *n;
2405
2406 list_for_each_safe(p, n, &blockpool->free_block_list) {
2407
2408 if (blockpool->pool_size < blockpool->pool_max)
2409 break;
2410
2411 pci_unmap_single(
2412 (blockpool->hldev)->pdev,
2413 ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
2414 ((struct __vxge_hw_blockpool_entry *)p)->length,
2415 PCI_DMA_BIDIRECTIONAL);
2416
2417 vxge_os_dma_free(
2418 (blockpool->hldev)->pdev,
2419 ((struct __vxge_hw_blockpool_entry *)p)->memblock,
2420 &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
2421
2422 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
2423
2424 list_add(p, &blockpool->free_entry_list);
2425
2426 blockpool->pool_size--;
2427
2428 }
2429 }
2430
2431 /*
2432 * __vxge_hw_blockpool_free - Frees the memory allcoated with
2433 * __vxge_hw_blockpool_malloc
2434 */
__vxge_hw_blockpool_free(struct __vxge_hw_device * devh,void * memblock,u32 size,struct vxge_hw_mempool_dma * dma_object)2435 static void __vxge_hw_blockpool_free(struct __vxge_hw_device *devh,
2436 void *memblock, u32 size,
2437 struct vxge_hw_mempool_dma *dma_object)
2438 {
2439 struct __vxge_hw_blockpool_entry *entry = NULL;
2440 struct __vxge_hw_blockpool *blockpool;
2441 enum vxge_hw_status status = VXGE_HW_OK;
2442
2443 blockpool = &devh->block_pool;
2444
2445 if (size != blockpool->block_size) {
2446 pci_unmap_single(devh->pdev, dma_object->addr, size,
2447 PCI_DMA_BIDIRECTIONAL);
2448 vxge_os_dma_free(devh->pdev, memblock, &dma_object->acc_handle);
2449 } else {
2450
2451 if (!list_empty(&blockpool->free_entry_list))
2452 entry = (struct __vxge_hw_blockpool_entry *)
2453 list_first_entry(&blockpool->free_entry_list,
2454 struct __vxge_hw_blockpool_entry,
2455 item);
2456
2457 if (entry == NULL)
2458 entry = vmalloc(sizeof(
2459 struct __vxge_hw_blockpool_entry));
2460 else
2461 list_del(&entry->item);
2462
2463 if (entry != NULL) {
2464 entry->length = size;
2465 entry->memblock = memblock;
2466 entry->dma_addr = dma_object->addr;
2467 entry->acc_handle = dma_object->acc_handle;
2468 entry->dma_handle = dma_object->handle;
2469 list_add(&entry->item,
2470 &blockpool->free_block_list);
2471 blockpool->pool_size++;
2472 status = VXGE_HW_OK;
2473 } else
2474 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2475
2476 if (status == VXGE_HW_OK)
2477 __vxge_hw_blockpool_blocks_remove(blockpool);
2478 }
2479 }
2480
2481 /*
2482 * vxge_hw_mempool_destroy
2483 */
__vxge_hw_mempool_destroy(struct vxge_hw_mempool * mempool)2484 static void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool)
2485 {
2486 u32 i, j;
2487 struct __vxge_hw_device *devh = mempool->devh;
2488
2489 for (i = 0; i < mempool->memblocks_allocated; i++) {
2490 struct vxge_hw_mempool_dma *dma_object;
2491
2492 vxge_assert(mempool->memblocks_arr[i]);
2493 vxge_assert(mempool->memblocks_dma_arr + i);
2494
2495 dma_object = mempool->memblocks_dma_arr + i;
2496
2497 for (j = 0; j < mempool->items_per_memblock; j++) {
2498 u32 index = i * mempool->items_per_memblock + j;
2499
2500 /* to skip last partially filled(if any) memblock */
2501 if (index >= mempool->items_current)
2502 break;
2503 }
2504
2505 vfree(mempool->memblocks_priv_arr[i]);
2506
2507 __vxge_hw_blockpool_free(devh, mempool->memblocks_arr[i],
2508 mempool->memblock_size, dma_object);
2509 }
2510
2511 vfree(mempool->items_arr);
2512 vfree(mempool->memblocks_dma_arr);
2513 vfree(mempool->memblocks_priv_arr);
2514 vfree(mempool->memblocks_arr);
2515 vfree(mempool);
2516 }
2517
2518 /*
2519 * __vxge_hw_mempool_grow
2520 * Will resize mempool up to %num_allocate value.
2521 */
2522 static enum vxge_hw_status
__vxge_hw_mempool_grow(struct vxge_hw_mempool * mempool,u32 num_allocate,u32 * num_allocated)2523 __vxge_hw_mempool_grow(struct vxge_hw_mempool *mempool, u32 num_allocate,
2524 u32 *num_allocated)
2525 {
2526 u32 i, first_time = mempool->memblocks_allocated == 0 ? 1 : 0;
2527 u32 n_items = mempool->items_per_memblock;
2528 u32 start_block_idx = mempool->memblocks_allocated;
2529 u32 end_block_idx = mempool->memblocks_allocated + num_allocate;
2530 enum vxge_hw_status status = VXGE_HW_OK;
2531
2532 *num_allocated = 0;
2533
2534 if (end_block_idx > mempool->memblocks_max) {
2535 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2536 goto exit;
2537 }
2538
2539 for (i = start_block_idx; i < end_block_idx; i++) {
2540 u32 j;
2541 u32 is_last = ((end_block_idx - 1) == i);
2542 struct vxge_hw_mempool_dma *dma_object =
2543 mempool->memblocks_dma_arr + i;
2544 void *the_memblock;
2545
2546 /* allocate memblock's private part. Each DMA memblock
2547 * has a space allocated for item's private usage upon
2548 * mempool's user request. Each time mempool grows, it will
2549 * allocate new memblock and its private part at once.
2550 * This helps to minimize memory usage a lot. */
2551 mempool->memblocks_priv_arr[i] =
2552 vzalloc(array_size(mempool->items_priv_size, n_items));
2553 if (mempool->memblocks_priv_arr[i] == NULL) {
2554 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2555 goto exit;
2556 }
2557
2558 /* allocate DMA-capable memblock */
2559 mempool->memblocks_arr[i] =
2560 __vxge_hw_blockpool_malloc(mempool->devh,
2561 mempool->memblock_size, dma_object);
2562 if (mempool->memblocks_arr[i] == NULL) {
2563 vfree(mempool->memblocks_priv_arr[i]);
2564 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2565 goto exit;
2566 }
2567
2568 (*num_allocated)++;
2569 mempool->memblocks_allocated++;
2570
2571 memset(mempool->memblocks_arr[i], 0, mempool->memblock_size);
2572
2573 the_memblock = mempool->memblocks_arr[i];
2574
2575 /* fill the items hash array */
2576 for (j = 0; j < n_items; j++) {
2577 u32 index = i * n_items + j;
2578
2579 if (first_time && index >= mempool->items_initial)
2580 break;
2581
2582 mempool->items_arr[index] =
2583 ((char *)the_memblock + j*mempool->item_size);
2584
2585 /* let caller to do more job on each item */
2586 if (mempool->item_func_alloc != NULL)
2587 mempool->item_func_alloc(mempool, i,
2588 dma_object, index, is_last);
2589
2590 mempool->items_current = index + 1;
2591 }
2592
2593 if (first_time && mempool->items_current ==
2594 mempool->items_initial)
2595 break;
2596 }
2597 exit:
2598 return status;
2599 }
2600
2601 /*
2602 * vxge_hw_mempool_create
2603 * This function will create memory pool object. Pool may grow but will
2604 * never shrink. Pool consists of number of dynamically allocated blocks
2605 * with size enough to hold %items_initial number of items. Memory is
2606 * DMA-able but client must map/unmap before interoperating with the device.
2607 */
2608 static struct vxge_hw_mempool *
__vxge_hw_mempool_create(struct __vxge_hw_device * devh,u32 memblock_size,u32 item_size,u32 items_priv_size,u32 items_initial,u32 items_max,const struct vxge_hw_mempool_cbs * mp_callback,void * userdata)2609 __vxge_hw_mempool_create(struct __vxge_hw_device *devh,
2610 u32 memblock_size,
2611 u32 item_size,
2612 u32 items_priv_size,
2613 u32 items_initial,
2614 u32 items_max,
2615 const struct vxge_hw_mempool_cbs *mp_callback,
2616 void *userdata)
2617 {
2618 enum vxge_hw_status status = VXGE_HW_OK;
2619 u32 memblocks_to_allocate;
2620 struct vxge_hw_mempool *mempool = NULL;
2621 u32 allocated;
2622
2623 if (memblock_size < item_size) {
2624 status = VXGE_HW_FAIL;
2625 goto exit;
2626 }
2627
2628 mempool = vzalloc(sizeof(struct vxge_hw_mempool));
2629 if (mempool == NULL) {
2630 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2631 goto exit;
2632 }
2633
2634 mempool->devh = devh;
2635 mempool->memblock_size = memblock_size;
2636 mempool->items_max = items_max;
2637 mempool->items_initial = items_initial;
2638 mempool->item_size = item_size;
2639 mempool->items_priv_size = items_priv_size;
2640 mempool->item_func_alloc = mp_callback->item_func_alloc;
2641 mempool->userdata = userdata;
2642
2643 mempool->memblocks_allocated = 0;
2644
2645 mempool->items_per_memblock = memblock_size / item_size;
2646
2647 mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) /
2648 mempool->items_per_memblock;
2649
2650 /* allocate array of memblocks */
2651 mempool->memblocks_arr =
2652 vzalloc(array_size(sizeof(void *), mempool->memblocks_max));
2653 if (mempool->memblocks_arr == NULL) {
2654 __vxge_hw_mempool_destroy(mempool);
2655 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2656 mempool = NULL;
2657 goto exit;
2658 }
2659
2660 /* allocate array of private parts of items per memblocks */
2661 mempool->memblocks_priv_arr =
2662 vzalloc(array_size(sizeof(void *), mempool->memblocks_max));
2663 if (mempool->memblocks_priv_arr == NULL) {
2664 __vxge_hw_mempool_destroy(mempool);
2665 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2666 mempool = NULL;
2667 goto exit;
2668 }
2669
2670 /* allocate array of memblocks DMA objects */
2671 mempool->memblocks_dma_arr =
2672 vzalloc(array_size(sizeof(struct vxge_hw_mempool_dma),
2673 mempool->memblocks_max));
2674 if (mempool->memblocks_dma_arr == NULL) {
2675 __vxge_hw_mempool_destroy(mempool);
2676 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2677 mempool = NULL;
2678 goto exit;
2679 }
2680
2681 /* allocate hash array of items */
2682 mempool->items_arr = vzalloc(array_size(sizeof(void *),
2683 mempool->items_max));
2684 if (mempool->items_arr == NULL) {
2685 __vxge_hw_mempool_destroy(mempool);
2686 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2687 mempool = NULL;
2688 goto exit;
2689 }
2690
2691 /* calculate initial number of memblocks */
2692 memblocks_to_allocate = (mempool->items_initial +
2693 mempool->items_per_memblock - 1) /
2694 mempool->items_per_memblock;
2695
2696 /* pre-allocate the mempool */
2697 status = __vxge_hw_mempool_grow(mempool, memblocks_to_allocate,
2698 &allocated);
2699 if (status != VXGE_HW_OK) {
2700 __vxge_hw_mempool_destroy(mempool);
2701 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2702 mempool = NULL;
2703 goto exit;
2704 }
2705
2706 exit:
2707 return mempool;
2708 }
2709
2710 /*
2711 * __vxge_hw_ring_abort - Returns the RxD
2712 * This function terminates the RxDs of ring
2713 */
__vxge_hw_ring_abort(struct __vxge_hw_ring * ring)2714 static enum vxge_hw_status __vxge_hw_ring_abort(struct __vxge_hw_ring *ring)
2715 {
2716 void *rxdh;
2717 struct __vxge_hw_channel *channel;
2718
2719 channel = &ring->channel;
2720
2721 for (;;) {
2722 vxge_hw_channel_dtr_try_complete(channel, &rxdh);
2723
2724 if (rxdh == NULL)
2725 break;
2726
2727 vxge_hw_channel_dtr_complete(channel);
2728
2729 if (ring->rxd_term)
2730 ring->rxd_term(rxdh, VXGE_HW_RXD_STATE_POSTED,
2731 channel->userdata);
2732
2733 vxge_hw_channel_dtr_free(channel, rxdh);
2734 }
2735
2736 return VXGE_HW_OK;
2737 }
2738
2739 /*
2740 * __vxge_hw_ring_reset - Resets the ring
2741 * This function resets the ring during vpath reset operation
2742 */
__vxge_hw_ring_reset(struct __vxge_hw_ring * ring)2743 static enum vxge_hw_status __vxge_hw_ring_reset(struct __vxge_hw_ring *ring)
2744 {
2745 enum vxge_hw_status status = VXGE_HW_OK;
2746 struct __vxge_hw_channel *channel;
2747
2748 channel = &ring->channel;
2749
2750 __vxge_hw_ring_abort(ring);
2751
2752 status = __vxge_hw_channel_reset(channel);
2753
2754 if (status != VXGE_HW_OK)
2755 goto exit;
2756
2757 if (ring->rxd_init) {
2758 status = vxge_hw_ring_replenish(ring);
2759 if (status != VXGE_HW_OK)
2760 goto exit;
2761 }
2762 exit:
2763 return status;
2764 }
2765
2766 /*
2767 * __vxge_hw_ring_delete - Removes the ring
2768 * This function freeup the memory pool and removes the ring
2769 */
2770 static enum vxge_hw_status
__vxge_hw_ring_delete(struct __vxge_hw_vpath_handle * vp)2771 __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp)
2772 {
2773 struct __vxge_hw_ring *ring = vp->vpath->ringh;
2774
2775 __vxge_hw_ring_abort(ring);
2776
2777 if (ring->mempool)
2778 __vxge_hw_mempool_destroy(ring->mempool);
2779
2780 vp->vpath->ringh = NULL;
2781 __vxge_hw_channel_free(&ring->channel);
2782
2783 return VXGE_HW_OK;
2784 }
2785
2786 /*
2787 * __vxge_hw_ring_create - Create a Ring
2788 * This function creates Ring and initializes it.
2789 */
2790 static enum vxge_hw_status
__vxge_hw_ring_create(struct __vxge_hw_vpath_handle * vp,struct vxge_hw_ring_attr * attr)2791 __vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp,
2792 struct vxge_hw_ring_attr *attr)
2793 {
2794 enum vxge_hw_status status = VXGE_HW_OK;
2795 struct __vxge_hw_ring *ring;
2796 u32 ring_length;
2797 struct vxge_hw_ring_config *config;
2798 struct __vxge_hw_device *hldev;
2799 u32 vp_id;
2800 static const struct vxge_hw_mempool_cbs ring_mp_callback = {
2801 .item_func_alloc = __vxge_hw_ring_mempool_item_alloc,
2802 };
2803
2804 if ((vp == NULL) || (attr == NULL)) {
2805 status = VXGE_HW_FAIL;
2806 goto exit;
2807 }
2808
2809 hldev = vp->vpath->hldev;
2810 vp_id = vp->vpath->vp_id;
2811
2812 config = &hldev->config.vp_config[vp_id].ring;
2813
2814 ring_length = config->ring_blocks *
2815 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
2816
2817 ring = (struct __vxge_hw_ring *)__vxge_hw_channel_allocate(vp,
2818 VXGE_HW_CHANNEL_TYPE_RING,
2819 ring_length,
2820 attr->per_rxd_space,
2821 attr->userdata);
2822 if (ring == NULL) {
2823 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2824 goto exit;
2825 }
2826
2827 vp->vpath->ringh = ring;
2828 ring->vp_id = vp_id;
2829 ring->vp_reg = vp->vpath->vp_reg;
2830 ring->common_reg = hldev->common_reg;
2831 ring->stats = &vp->vpath->sw_stats->ring_stats;
2832 ring->config = config;
2833 ring->callback = attr->callback;
2834 ring->rxd_init = attr->rxd_init;
2835 ring->rxd_term = attr->rxd_term;
2836 ring->buffer_mode = config->buffer_mode;
2837 ring->tim_rti_cfg1_saved = vp->vpath->tim_rti_cfg1_saved;
2838 ring->tim_rti_cfg3_saved = vp->vpath->tim_rti_cfg3_saved;
2839 ring->rxds_limit = config->rxds_limit;
2840
2841 ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode);
2842 ring->rxd_priv_size =
2843 sizeof(struct __vxge_hw_ring_rxd_priv) + attr->per_rxd_space;
2844 ring->per_rxd_space = attr->per_rxd_space;
2845
2846 ring->rxd_priv_size =
2847 ((ring->rxd_priv_size + VXGE_CACHE_LINE_SIZE - 1) /
2848 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
2849
2850 /* how many RxDs can fit into one block. Depends on configured
2851 * buffer_mode. */
2852 ring->rxds_per_block =
2853 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
2854
2855 /* calculate actual RxD block private size */
2856 ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
2857 ring->mempool = __vxge_hw_mempool_create(hldev,
2858 VXGE_HW_BLOCK_SIZE,
2859 VXGE_HW_BLOCK_SIZE,
2860 ring->rxdblock_priv_size,
2861 ring->config->ring_blocks,
2862 ring->config->ring_blocks,
2863 &ring_mp_callback,
2864 ring);
2865 if (ring->mempool == NULL) {
2866 __vxge_hw_ring_delete(vp);
2867 return VXGE_HW_ERR_OUT_OF_MEMORY;
2868 }
2869
2870 status = __vxge_hw_channel_initialize(&ring->channel);
2871 if (status != VXGE_HW_OK) {
2872 __vxge_hw_ring_delete(vp);
2873 goto exit;
2874 }
2875
2876 /* Note:
2877 * Specifying rxd_init callback means two things:
2878 * 1) rxds need to be initialized by driver at channel-open time;
2879 * 2) rxds need to be posted at channel-open time
2880 * (that's what the initial_replenish() below does)
2881 * Currently we don't have a case when the 1) is done without the 2).
2882 */
2883 if (ring->rxd_init) {
2884 status = vxge_hw_ring_replenish(ring);
2885 if (status != VXGE_HW_OK) {
2886 __vxge_hw_ring_delete(vp);
2887 goto exit;
2888 }
2889 }
2890
2891 /* initial replenish will increment the counter in its post() routine,
2892 * we have to reset it */
2893 ring->stats->common_stats.usage_cnt = 0;
2894 exit:
2895 return status;
2896 }
2897
2898 /*
2899 * vxge_hw_device_config_default_get - Initialize device config with defaults.
2900 * Initialize Titan device config with default values.
2901 */
2902 enum vxge_hw_status
vxge_hw_device_config_default_get(struct vxge_hw_device_config * device_config)2903 vxge_hw_device_config_default_get(struct vxge_hw_device_config *device_config)
2904 {
2905 u32 i;
2906
2907 device_config->dma_blockpool_initial =
2908 VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE;
2909 device_config->dma_blockpool_max = VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE;
2910 device_config->intr_mode = VXGE_HW_INTR_MODE_DEF;
2911 device_config->rth_en = VXGE_HW_RTH_DEFAULT;
2912 device_config->rth_it_type = VXGE_HW_RTH_IT_TYPE_DEFAULT;
2913 device_config->device_poll_millis = VXGE_HW_DEF_DEVICE_POLL_MILLIS;
2914 device_config->rts_mac_en = VXGE_HW_RTS_MAC_DEFAULT;
2915
2916 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
2917 device_config->vp_config[i].vp_id = i;
2918
2919 device_config->vp_config[i].min_bandwidth =
2920 VXGE_HW_VPATH_BANDWIDTH_DEFAULT;
2921
2922 device_config->vp_config[i].ring.enable = VXGE_HW_RING_DEFAULT;
2923
2924 device_config->vp_config[i].ring.ring_blocks =
2925 VXGE_HW_DEF_RING_BLOCKS;
2926
2927 device_config->vp_config[i].ring.buffer_mode =
2928 VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT;
2929
2930 device_config->vp_config[i].ring.scatter_mode =
2931 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT;
2932
2933 device_config->vp_config[i].ring.rxds_limit =
2934 VXGE_HW_DEF_RING_RXDS_LIMIT;
2935
2936 device_config->vp_config[i].fifo.enable = VXGE_HW_FIFO_ENABLE;
2937
2938 device_config->vp_config[i].fifo.fifo_blocks =
2939 VXGE_HW_MIN_FIFO_BLOCKS;
2940
2941 device_config->vp_config[i].fifo.max_frags =
2942 VXGE_HW_MAX_FIFO_FRAGS;
2943
2944 device_config->vp_config[i].fifo.memblock_size =
2945 VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE;
2946
2947 device_config->vp_config[i].fifo.alignment_size =
2948 VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE;
2949
2950 device_config->vp_config[i].fifo.intr =
2951 VXGE_HW_FIFO_QUEUE_INTR_DEFAULT;
2952
2953 device_config->vp_config[i].fifo.no_snoop_bits =
2954 VXGE_HW_FIFO_NO_SNOOP_DEFAULT;
2955 device_config->vp_config[i].tti.intr_enable =
2956 VXGE_HW_TIM_INTR_DEFAULT;
2957
2958 device_config->vp_config[i].tti.btimer_val =
2959 VXGE_HW_USE_FLASH_DEFAULT;
2960
2961 device_config->vp_config[i].tti.timer_ac_en =
2962 VXGE_HW_USE_FLASH_DEFAULT;
2963
2964 device_config->vp_config[i].tti.timer_ci_en =
2965 VXGE_HW_USE_FLASH_DEFAULT;
2966
2967 device_config->vp_config[i].tti.timer_ri_en =
2968 VXGE_HW_USE_FLASH_DEFAULT;
2969
2970 device_config->vp_config[i].tti.rtimer_val =
2971 VXGE_HW_USE_FLASH_DEFAULT;
2972
2973 device_config->vp_config[i].tti.util_sel =
2974 VXGE_HW_USE_FLASH_DEFAULT;
2975
2976 device_config->vp_config[i].tti.ltimer_val =
2977 VXGE_HW_USE_FLASH_DEFAULT;
2978
2979 device_config->vp_config[i].tti.urange_a =
2980 VXGE_HW_USE_FLASH_DEFAULT;
2981
2982 device_config->vp_config[i].tti.uec_a =
2983 VXGE_HW_USE_FLASH_DEFAULT;
2984
2985 device_config->vp_config[i].tti.urange_b =
2986 VXGE_HW_USE_FLASH_DEFAULT;
2987
2988 device_config->vp_config[i].tti.uec_b =
2989 VXGE_HW_USE_FLASH_DEFAULT;
2990
2991 device_config->vp_config[i].tti.urange_c =
2992 VXGE_HW_USE_FLASH_DEFAULT;
2993
2994 device_config->vp_config[i].tti.uec_c =
2995 VXGE_HW_USE_FLASH_DEFAULT;
2996
2997 device_config->vp_config[i].tti.uec_d =
2998 VXGE_HW_USE_FLASH_DEFAULT;
2999
3000 device_config->vp_config[i].rti.intr_enable =
3001 VXGE_HW_TIM_INTR_DEFAULT;
3002
3003 device_config->vp_config[i].rti.btimer_val =
3004 VXGE_HW_USE_FLASH_DEFAULT;
3005
3006 device_config->vp_config[i].rti.timer_ac_en =
3007 VXGE_HW_USE_FLASH_DEFAULT;
3008
3009 device_config->vp_config[i].rti.timer_ci_en =
3010 VXGE_HW_USE_FLASH_DEFAULT;
3011
3012 device_config->vp_config[i].rti.timer_ri_en =
3013 VXGE_HW_USE_FLASH_DEFAULT;
3014
3015 device_config->vp_config[i].rti.rtimer_val =
3016 VXGE_HW_USE_FLASH_DEFAULT;
3017
3018 device_config->vp_config[i].rti.util_sel =
3019 VXGE_HW_USE_FLASH_DEFAULT;
3020
3021 device_config->vp_config[i].rti.ltimer_val =
3022 VXGE_HW_USE_FLASH_DEFAULT;
3023
3024 device_config->vp_config[i].rti.urange_a =
3025 VXGE_HW_USE_FLASH_DEFAULT;
3026
3027 device_config->vp_config[i].rti.uec_a =
3028 VXGE_HW_USE_FLASH_DEFAULT;
3029
3030 device_config->vp_config[i].rti.urange_b =
3031 VXGE_HW_USE_FLASH_DEFAULT;
3032
3033 device_config->vp_config[i].rti.uec_b =
3034 VXGE_HW_USE_FLASH_DEFAULT;
3035
3036 device_config->vp_config[i].rti.urange_c =
3037 VXGE_HW_USE_FLASH_DEFAULT;
3038
3039 device_config->vp_config[i].rti.uec_c =
3040 VXGE_HW_USE_FLASH_DEFAULT;
3041
3042 device_config->vp_config[i].rti.uec_d =
3043 VXGE_HW_USE_FLASH_DEFAULT;
3044
3045 device_config->vp_config[i].mtu =
3046 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU;
3047
3048 device_config->vp_config[i].rpa_strip_vlan_tag =
3049 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT;
3050 }
3051
3052 return VXGE_HW_OK;
3053 }
3054
3055 /*
3056 * __vxge_hw_vpath_swapper_set - Set the swapper bits for the vpath.
3057 * Set the swapper bits appropriately for the vpath.
3058 */
3059 static enum vxge_hw_status
__vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem * vpath_reg)3060 __vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
3061 {
3062 #ifndef __BIG_ENDIAN
3063 u64 val64;
3064
3065 val64 = readq(&vpath_reg->vpath_general_cfg1);
3066 wmb();
3067 val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
3068 writeq(val64, &vpath_reg->vpath_general_cfg1);
3069 wmb();
3070 #endif
3071 return VXGE_HW_OK;
3072 }
3073
3074 /*
3075 * __vxge_hw_kdfc_swapper_set - Set the swapper bits for the kdfc.
3076 * Set the swapper bits appropriately for the vpath.
3077 */
3078 static enum vxge_hw_status
__vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem * legacy_reg,struct vxge_hw_vpath_reg __iomem * vpath_reg)3079 __vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg,
3080 struct vxge_hw_vpath_reg __iomem *vpath_reg)
3081 {
3082 u64 val64;
3083
3084 val64 = readq(&legacy_reg->pifm_wr_swap_en);
3085
3086 if (val64 == VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE) {
3087 val64 = readq(&vpath_reg->kdfcctl_cfg0);
3088 wmb();
3089
3090 val64 |= VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 |
3091 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 |
3092 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2;
3093
3094 writeq(val64, &vpath_reg->kdfcctl_cfg0);
3095 wmb();
3096 }
3097
3098 return VXGE_HW_OK;
3099 }
3100
3101 /*
3102 * vxge_hw_mgmt_reg_read - Read Titan register.
3103 */
3104 enum vxge_hw_status
vxge_hw_mgmt_reg_read(struct __vxge_hw_device * hldev,enum vxge_hw_mgmt_reg_type type,u32 index,u32 offset,u64 * value)3105 vxge_hw_mgmt_reg_read(struct __vxge_hw_device *hldev,
3106 enum vxge_hw_mgmt_reg_type type,
3107 u32 index, u32 offset, u64 *value)
3108 {
3109 enum vxge_hw_status status = VXGE_HW_OK;
3110
3111 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
3112 status = VXGE_HW_ERR_INVALID_DEVICE;
3113 goto exit;
3114 }
3115
3116 switch (type) {
3117 case vxge_hw_mgmt_reg_type_legacy:
3118 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
3119 status = VXGE_HW_ERR_INVALID_OFFSET;
3120 break;
3121 }
3122 *value = readq((void __iomem *)hldev->legacy_reg + offset);
3123 break;
3124 case vxge_hw_mgmt_reg_type_toc:
3125 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
3126 status = VXGE_HW_ERR_INVALID_OFFSET;
3127 break;
3128 }
3129 *value = readq((void __iomem *)hldev->toc_reg + offset);
3130 break;
3131 case vxge_hw_mgmt_reg_type_common:
3132 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
3133 status = VXGE_HW_ERR_INVALID_OFFSET;
3134 break;
3135 }
3136 *value = readq((void __iomem *)hldev->common_reg + offset);
3137 break;
3138 case vxge_hw_mgmt_reg_type_mrpcim:
3139 if (!(hldev->access_rights &
3140 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
3141 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3142 break;
3143 }
3144 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
3145 status = VXGE_HW_ERR_INVALID_OFFSET;
3146 break;
3147 }
3148 *value = readq((void __iomem *)hldev->mrpcim_reg + offset);
3149 break;
3150 case vxge_hw_mgmt_reg_type_srpcim:
3151 if (!(hldev->access_rights &
3152 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
3153 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3154 break;
3155 }
3156 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
3157 status = VXGE_HW_ERR_INVALID_INDEX;
3158 break;
3159 }
3160 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
3161 status = VXGE_HW_ERR_INVALID_OFFSET;
3162 break;
3163 }
3164 *value = readq((void __iomem *)hldev->srpcim_reg[index] +
3165 offset);
3166 break;
3167 case vxge_hw_mgmt_reg_type_vpmgmt:
3168 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
3169 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3170 status = VXGE_HW_ERR_INVALID_INDEX;
3171 break;
3172 }
3173 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
3174 status = VXGE_HW_ERR_INVALID_OFFSET;
3175 break;
3176 }
3177 *value = readq((void __iomem *)hldev->vpmgmt_reg[index] +
3178 offset);
3179 break;
3180 case vxge_hw_mgmt_reg_type_vpath:
3181 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) ||
3182 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3183 status = VXGE_HW_ERR_INVALID_INDEX;
3184 break;
3185 }
3186 if (index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) {
3187 status = VXGE_HW_ERR_INVALID_INDEX;
3188 break;
3189 }
3190 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
3191 status = VXGE_HW_ERR_INVALID_OFFSET;
3192 break;
3193 }
3194 *value = readq((void __iomem *)hldev->vpath_reg[index] +
3195 offset);
3196 break;
3197 default:
3198 status = VXGE_HW_ERR_INVALID_TYPE;
3199 break;
3200 }
3201
3202 exit:
3203 return status;
3204 }
3205
3206 /*
3207 * vxge_hw_vpath_strip_fcs_check - Check for FCS strip.
3208 */
3209 enum vxge_hw_status
vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device * hldev,u64 vpath_mask)3210 vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask)
3211 {
3212 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
3213 int i = 0, j = 0;
3214
3215 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3216 if (!((vpath_mask) & vxge_mBIT(i)))
3217 continue;
3218 vpmgmt_reg = hldev->vpmgmt_reg[i];
3219 for (j = 0; j < VXGE_HW_MAC_MAX_MAC_PORT_ID; j++) {
3220 if (readq(&vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[j])
3221 & VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS)
3222 return VXGE_HW_FAIL;
3223 }
3224 }
3225 return VXGE_HW_OK;
3226 }
3227 /*
3228 * vxge_hw_mgmt_reg_Write - Write Titan register.
3229 */
3230 enum vxge_hw_status
vxge_hw_mgmt_reg_write(struct __vxge_hw_device * hldev,enum vxge_hw_mgmt_reg_type type,u32 index,u32 offset,u64 value)3231 vxge_hw_mgmt_reg_write(struct __vxge_hw_device *hldev,
3232 enum vxge_hw_mgmt_reg_type type,
3233 u32 index, u32 offset, u64 value)
3234 {
3235 enum vxge_hw_status status = VXGE_HW_OK;
3236
3237 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
3238 status = VXGE_HW_ERR_INVALID_DEVICE;
3239 goto exit;
3240 }
3241
3242 switch (type) {
3243 case vxge_hw_mgmt_reg_type_legacy:
3244 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
3245 status = VXGE_HW_ERR_INVALID_OFFSET;
3246 break;
3247 }
3248 writeq(value, (void __iomem *)hldev->legacy_reg + offset);
3249 break;
3250 case vxge_hw_mgmt_reg_type_toc:
3251 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
3252 status = VXGE_HW_ERR_INVALID_OFFSET;
3253 break;
3254 }
3255 writeq(value, (void __iomem *)hldev->toc_reg + offset);
3256 break;
3257 case vxge_hw_mgmt_reg_type_common:
3258 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
3259 status = VXGE_HW_ERR_INVALID_OFFSET;
3260 break;
3261 }
3262 writeq(value, (void __iomem *)hldev->common_reg + offset);
3263 break;
3264 case vxge_hw_mgmt_reg_type_mrpcim:
3265 if (!(hldev->access_rights &
3266 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
3267 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3268 break;
3269 }
3270 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
3271 status = VXGE_HW_ERR_INVALID_OFFSET;
3272 break;
3273 }
3274 writeq(value, (void __iomem *)hldev->mrpcim_reg + offset);
3275 break;
3276 case vxge_hw_mgmt_reg_type_srpcim:
3277 if (!(hldev->access_rights &
3278 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
3279 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3280 break;
3281 }
3282 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
3283 status = VXGE_HW_ERR_INVALID_INDEX;
3284 break;
3285 }
3286 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
3287 status = VXGE_HW_ERR_INVALID_OFFSET;
3288 break;
3289 }
3290 writeq(value, (void __iomem *)hldev->srpcim_reg[index] +
3291 offset);
3292
3293 break;
3294 case vxge_hw_mgmt_reg_type_vpmgmt:
3295 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
3296 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3297 status = VXGE_HW_ERR_INVALID_INDEX;
3298 break;
3299 }
3300 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
3301 status = VXGE_HW_ERR_INVALID_OFFSET;
3302 break;
3303 }
3304 writeq(value, (void __iomem *)hldev->vpmgmt_reg[index] +
3305 offset);
3306 break;
3307 case vxge_hw_mgmt_reg_type_vpath:
3308 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES-1) ||
3309 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3310 status = VXGE_HW_ERR_INVALID_INDEX;
3311 break;
3312 }
3313 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
3314 status = VXGE_HW_ERR_INVALID_OFFSET;
3315 break;
3316 }
3317 writeq(value, (void __iomem *)hldev->vpath_reg[index] +
3318 offset);
3319 break;
3320 default:
3321 status = VXGE_HW_ERR_INVALID_TYPE;
3322 break;
3323 }
3324 exit:
3325 return status;
3326 }
3327
3328 /*
3329 * __vxge_hw_fifo_abort - Returns the TxD
3330 * This function terminates the TxDs of fifo
3331 */
__vxge_hw_fifo_abort(struct __vxge_hw_fifo * fifo)3332 static enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo)
3333 {
3334 void *txdlh;
3335
3336 for (;;) {
3337 vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh);
3338
3339 if (txdlh == NULL)
3340 break;
3341
3342 vxge_hw_channel_dtr_complete(&fifo->channel);
3343
3344 if (fifo->txdl_term) {
3345 fifo->txdl_term(txdlh,
3346 VXGE_HW_TXDL_STATE_POSTED,
3347 fifo->channel.userdata);
3348 }
3349
3350 vxge_hw_channel_dtr_free(&fifo->channel, txdlh);
3351 }
3352
3353 return VXGE_HW_OK;
3354 }
3355
3356 /*
3357 * __vxge_hw_fifo_reset - Resets the fifo
3358 * This function resets the fifo during vpath reset operation
3359 */
__vxge_hw_fifo_reset(struct __vxge_hw_fifo * fifo)3360 static enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo)
3361 {
3362 enum vxge_hw_status status = VXGE_HW_OK;
3363
3364 __vxge_hw_fifo_abort(fifo);
3365 status = __vxge_hw_channel_reset(&fifo->channel);
3366
3367 return status;
3368 }
3369
3370 /*
3371 * __vxge_hw_fifo_delete - Removes the FIFO
3372 * This function freeup the memory pool and removes the FIFO
3373 */
3374 static enum vxge_hw_status
__vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle * vp)3375 __vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle *vp)
3376 {
3377 struct __vxge_hw_fifo *fifo = vp->vpath->fifoh;
3378
3379 __vxge_hw_fifo_abort(fifo);
3380
3381 if (fifo->mempool)
3382 __vxge_hw_mempool_destroy(fifo->mempool);
3383
3384 vp->vpath->fifoh = NULL;
3385
3386 __vxge_hw_channel_free(&fifo->channel);
3387
3388 return VXGE_HW_OK;
3389 }
3390
3391 /*
3392 * __vxge_hw_fifo_mempool_item_alloc - Allocate List blocks for TxD
3393 * list callback
3394 * This function is callback passed to __vxge_hw_mempool_create to create memory
3395 * pool for TxD list
3396 */
3397 static void
__vxge_hw_fifo_mempool_item_alloc(struct vxge_hw_mempool * mempoolh,u32 memblock_index,struct vxge_hw_mempool_dma * dma_object,u32 index,u32 is_last)3398 __vxge_hw_fifo_mempool_item_alloc(
3399 struct vxge_hw_mempool *mempoolh,
3400 u32 memblock_index, struct vxge_hw_mempool_dma *dma_object,
3401 u32 index, u32 is_last)
3402 {
3403 u32 memblock_item_idx;
3404 struct __vxge_hw_fifo_txdl_priv *txdl_priv;
3405 struct vxge_hw_fifo_txd *txdp =
3406 (struct vxge_hw_fifo_txd *)mempoolh->items_arr[index];
3407 struct __vxge_hw_fifo *fifo =
3408 (struct __vxge_hw_fifo *)mempoolh->userdata;
3409 void *memblock = mempoolh->memblocks_arr[memblock_index];
3410
3411 vxge_assert(txdp);
3412
3413 txdp->host_control = (u64) (size_t)
3414 __vxge_hw_mempool_item_priv(mempoolh, memblock_index, txdp,
3415 &memblock_item_idx);
3416
3417 txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
3418
3419 vxge_assert(txdl_priv);
3420
3421 fifo->channel.reserve_arr[fifo->channel.reserve_ptr - 1 - index] = txdp;
3422
3423 /* pre-format HW's TxDL's private */
3424 txdl_priv->dma_offset = (char *)txdp - (char *)memblock;
3425 txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset;
3426 txdl_priv->dma_handle = dma_object->handle;
3427 txdl_priv->memblock = memblock;
3428 txdl_priv->first_txdp = txdp;
3429 txdl_priv->next_txdl_priv = NULL;
3430 txdl_priv->alloc_frags = 0;
3431 }
3432
3433 /*
3434 * __vxge_hw_fifo_create - Create a FIFO
3435 * This function creates FIFO and initializes it.
3436 */
3437 static enum vxge_hw_status
__vxge_hw_fifo_create(struct __vxge_hw_vpath_handle * vp,struct vxge_hw_fifo_attr * attr)3438 __vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp,
3439 struct vxge_hw_fifo_attr *attr)
3440 {
3441 enum vxge_hw_status status = VXGE_HW_OK;
3442 struct __vxge_hw_fifo *fifo;
3443 struct vxge_hw_fifo_config *config;
3444 u32 txdl_size, txdl_per_memblock;
3445 struct vxge_hw_mempool_cbs fifo_mp_callback;
3446 struct __vxge_hw_virtualpath *vpath;
3447
3448 if ((vp == NULL) || (attr == NULL)) {
3449 status = VXGE_HW_ERR_INVALID_HANDLE;
3450 goto exit;
3451 }
3452 vpath = vp->vpath;
3453 config = &vpath->hldev->config.vp_config[vpath->vp_id].fifo;
3454
3455 txdl_size = config->max_frags * sizeof(struct vxge_hw_fifo_txd);
3456
3457 txdl_per_memblock = config->memblock_size / txdl_size;
3458
3459 fifo = (struct __vxge_hw_fifo *)__vxge_hw_channel_allocate(vp,
3460 VXGE_HW_CHANNEL_TYPE_FIFO,
3461 config->fifo_blocks * txdl_per_memblock,
3462 attr->per_txdl_space, attr->userdata);
3463
3464 if (fifo == NULL) {
3465 status = VXGE_HW_ERR_OUT_OF_MEMORY;
3466 goto exit;
3467 }
3468
3469 vpath->fifoh = fifo;
3470 fifo->nofl_db = vpath->nofl_db;
3471
3472 fifo->vp_id = vpath->vp_id;
3473 fifo->vp_reg = vpath->vp_reg;
3474 fifo->stats = &vpath->sw_stats->fifo_stats;
3475
3476 fifo->config = config;
3477
3478 /* apply "interrupts per txdl" attribute */
3479 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ;
3480 fifo->tim_tti_cfg1_saved = vpath->tim_tti_cfg1_saved;
3481 fifo->tim_tti_cfg3_saved = vpath->tim_tti_cfg3_saved;
3482
3483 if (fifo->config->intr)
3484 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
3485
3486 fifo->no_snoop_bits = config->no_snoop_bits;
3487
3488 /*
3489 * FIFO memory management strategy:
3490 *
3491 * TxDL split into three independent parts:
3492 * - set of TxD's
3493 * - TxD HW private part
3494 * - driver private part
3495 *
3496 * Adaptative memory allocation used. i.e. Memory allocated on
3497 * demand with the size which will fit into one memory block.
3498 * One memory block may contain more than one TxDL.
3499 *
3500 * During "reserve" operations more memory can be allocated on demand
3501 * for example due to FIFO full condition.
3502 *
3503 * Pool of memory memblocks never shrinks except in __vxge_hw_fifo_close
3504 * routine which will essentially stop the channel and free resources.
3505 */
3506
3507 /* TxDL common private size == TxDL private + driver private */
3508 fifo->priv_size =
3509 sizeof(struct __vxge_hw_fifo_txdl_priv) + attr->per_txdl_space;
3510 fifo->priv_size = ((fifo->priv_size + VXGE_CACHE_LINE_SIZE - 1) /
3511 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
3512
3513 fifo->per_txdl_space = attr->per_txdl_space;
3514
3515 /* recompute txdl size to be cacheline aligned */
3516 fifo->txdl_size = txdl_size;
3517 fifo->txdl_per_memblock = txdl_per_memblock;
3518
3519 fifo->txdl_term = attr->txdl_term;
3520 fifo->callback = attr->callback;
3521
3522 if (fifo->txdl_per_memblock == 0) {
3523 __vxge_hw_fifo_delete(vp);
3524 status = VXGE_HW_ERR_INVALID_BLOCK_SIZE;
3525 goto exit;
3526 }
3527
3528 fifo_mp_callback.item_func_alloc = __vxge_hw_fifo_mempool_item_alloc;
3529
3530 fifo->mempool =
3531 __vxge_hw_mempool_create(vpath->hldev,
3532 fifo->config->memblock_size,
3533 fifo->txdl_size,
3534 fifo->priv_size,
3535 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3536 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3537 &fifo_mp_callback,
3538 fifo);
3539
3540 if (fifo->mempool == NULL) {
3541 __vxge_hw_fifo_delete(vp);
3542 status = VXGE_HW_ERR_OUT_OF_MEMORY;
3543 goto exit;
3544 }
3545
3546 status = __vxge_hw_channel_initialize(&fifo->channel);
3547 if (status != VXGE_HW_OK) {
3548 __vxge_hw_fifo_delete(vp);
3549 goto exit;
3550 }
3551
3552 vxge_assert(fifo->channel.reserve_ptr);
3553 exit:
3554 return status;
3555 }
3556
3557 /*
3558 * __vxge_hw_vpath_pci_read - Read the content of given address
3559 * in pci config space.
3560 * Read from the vpath pci config space.
3561 */
3562 static enum vxge_hw_status
__vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath * vpath,u32 phy_func_0,u32 offset,u32 * val)3563 __vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath *vpath,
3564 u32 phy_func_0, u32 offset, u32 *val)
3565 {
3566 u64 val64;
3567 enum vxge_hw_status status = VXGE_HW_OK;
3568 struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
3569
3570 val64 = VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(offset);
3571
3572 if (phy_func_0)
3573 val64 |= VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0;
3574
3575 writeq(val64, &vp_reg->pci_config_access_cfg1);
3576 wmb();
3577 writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ,
3578 &vp_reg->pci_config_access_cfg2);
3579 wmb();
3580
3581 status = __vxge_hw_device_register_poll(
3582 &vp_reg->pci_config_access_cfg2,
3583 VXGE_HW_INTR_MASK_ALL, VXGE_HW_DEF_DEVICE_POLL_MILLIS);
3584
3585 if (status != VXGE_HW_OK)
3586 goto exit;
3587
3588 val64 = readq(&vp_reg->pci_config_access_status);
3589
3590 if (val64 & VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR) {
3591 status = VXGE_HW_FAIL;
3592 *val = 0;
3593 } else
3594 *val = (u32)vxge_bVALn(val64, 32, 32);
3595 exit:
3596 return status;
3597 }
3598
3599 /**
3600 * vxge_hw_device_flick_link_led - Flick (blink) link LED.
3601 * @hldev: HW device.
3602 * @on_off: TRUE if flickering to be on, FALSE to be off
3603 *
3604 * Flicker the link LED.
3605 */
3606 enum vxge_hw_status
vxge_hw_device_flick_link_led(struct __vxge_hw_device * hldev,u64 on_off)3607 vxge_hw_device_flick_link_led(struct __vxge_hw_device *hldev, u64 on_off)
3608 {
3609 struct __vxge_hw_virtualpath *vpath;
3610 u64 data0, data1 = 0, steer_ctrl = 0;
3611 enum vxge_hw_status status;
3612
3613 if (hldev == NULL) {
3614 status = VXGE_HW_ERR_INVALID_DEVICE;
3615 goto exit;
3616 }
3617
3618 vpath = &hldev->virtual_paths[hldev->first_vp_id];
3619
3620 data0 = on_off;
3621 status = vxge_hw_vpath_fw_api(vpath,
3622 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL,
3623 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
3624 0, &data0, &data1, &steer_ctrl);
3625 exit:
3626 return status;
3627 }
3628
3629 /*
3630 * __vxge_hw_vpath_rts_table_get - Get the entries from RTS access tables
3631 */
3632 enum vxge_hw_status
__vxge_hw_vpath_rts_table_get(struct __vxge_hw_vpath_handle * vp,u32 action,u32 rts_table,u32 offset,u64 * data0,u64 * data1)3633 __vxge_hw_vpath_rts_table_get(struct __vxge_hw_vpath_handle *vp,
3634 u32 action, u32 rts_table, u32 offset,
3635 u64 *data0, u64 *data1)
3636 {
3637 enum vxge_hw_status status;
3638 u64 steer_ctrl = 0;
3639
3640 if (vp == NULL) {
3641 status = VXGE_HW_ERR_INVALID_HANDLE;
3642 goto exit;
3643 }
3644
3645 if ((rts_table ==
3646 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
3647 (rts_table ==
3648 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
3649 (rts_table ==
3650 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
3651 (rts_table ==
3652 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
3653 steer_ctrl = VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
3654 }
3655
3656 status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3657 data0, data1, &steer_ctrl);
3658 if (status != VXGE_HW_OK)
3659 goto exit;
3660
3661 if ((rts_table != VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) &&
3662 (rts_table !=
3663 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3664 *data1 = 0;
3665 exit:
3666 return status;
3667 }
3668
3669 /*
3670 * __vxge_hw_vpath_rts_table_set - Set the entries of RTS access tables
3671 */
3672 enum vxge_hw_status
__vxge_hw_vpath_rts_table_set(struct __vxge_hw_vpath_handle * vp,u32 action,u32 rts_table,u32 offset,u64 steer_data0,u64 steer_data1)3673 __vxge_hw_vpath_rts_table_set(struct __vxge_hw_vpath_handle *vp, u32 action,
3674 u32 rts_table, u32 offset, u64 steer_data0,
3675 u64 steer_data1)
3676 {
3677 u64 data0, data1 = 0, steer_ctrl = 0;
3678 enum vxge_hw_status status;
3679
3680 if (vp == NULL) {
3681 status = VXGE_HW_ERR_INVALID_HANDLE;
3682 goto exit;
3683 }
3684
3685 data0 = steer_data0;
3686
3687 if ((rts_table == VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
3688 (rts_table ==
3689 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3690 data1 = steer_data1;
3691
3692 status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3693 &data0, &data1, &steer_ctrl);
3694 exit:
3695 return status;
3696 }
3697
3698 /*
3699 * vxge_hw_vpath_rts_rth_set - Set/configure RTS hashing.
3700 */
vxge_hw_vpath_rts_rth_set(struct __vxge_hw_vpath_handle * vp,enum vxge_hw_rth_algoritms algorithm,struct vxge_hw_rth_hash_types * hash_type,u16 bucket_size)3701 enum vxge_hw_status vxge_hw_vpath_rts_rth_set(
3702 struct __vxge_hw_vpath_handle *vp,
3703 enum vxge_hw_rth_algoritms algorithm,
3704 struct vxge_hw_rth_hash_types *hash_type,
3705 u16 bucket_size)
3706 {
3707 u64 data0, data1;
3708 enum vxge_hw_status status = VXGE_HW_OK;
3709
3710 if (vp == NULL) {
3711 status = VXGE_HW_ERR_INVALID_HANDLE;
3712 goto exit;
3713 }
3714
3715 status = __vxge_hw_vpath_rts_table_get(vp,
3716 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
3717 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3718 0, &data0, &data1);
3719 if (status != VXGE_HW_OK)
3720 goto exit;
3721
3722 data0 &= ~(VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(0xf) |
3723 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(0x3));
3724
3725 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN |
3726 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(bucket_size) |
3727 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(algorithm);
3728
3729 if (hash_type->hash_type_tcpipv4_en)
3730 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN;
3731
3732 if (hash_type->hash_type_ipv4_en)
3733 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN;
3734
3735 if (hash_type->hash_type_tcpipv6_en)
3736 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN;
3737
3738 if (hash_type->hash_type_ipv6_en)
3739 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN;
3740
3741 if (hash_type->hash_type_tcpipv6ex_en)
3742 data0 |=
3743 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN;
3744
3745 if (hash_type->hash_type_ipv6ex_en)
3746 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN;
3747
3748 if (VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(data0))
3749 data0 &= ~VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3750 else
3751 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3752
3753 status = __vxge_hw_vpath_rts_table_set(vp,
3754 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3755 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3756 0, data0, 0);
3757 exit:
3758 return status;
3759 }
3760
3761 static void
vxge_hw_rts_rth_data0_data1_get(u32 j,u64 * data0,u64 * data1,u16 flag,u8 * itable)3762 vxge_hw_rts_rth_data0_data1_get(u32 j, u64 *data0, u64 *data1,
3763 u16 flag, u8 *itable)
3764 {
3765 switch (flag) {
3766 case 1:
3767 *data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j)|
3768 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN |
3769 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(
3770 itable[j]);
3771 /* fall through */
3772 case 2:
3773 *data0 |=
3774 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j)|
3775 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN |
3776 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(
3777 itable[j]);
3778 /* fall through */
3779 case 3:
3780 *data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j)|
3781 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN |
3782 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(
3783 itable[j]);
3784 /* fall through */
3785 case 4:
3786 *data1 |=
3787 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j)|
3788 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN |
3789 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(
3790 itable[j]);
3791 default:
3792 return;
3793 }
3794 }
3795 /*
3796 * vxge_hw_vpath_rts_rth_itable_set - Set/configure indirection table (IT).
3797 */
vxge_hw_vpath_rts_rth_itable_set(struct __vxge_hw_vpath_handle ** vpath_handles,u32 vpath_count,u8 * mtable,u8 * itable,u32 itable_size)3798 enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set(
3799 struct __vxge_hw_vpath_handle **vpath_handles,
3800 u32 vpath_count,
3801 u8 *mtable,
3802 u8 *itable,
3803 u32 itable_size)
3804 {
3805 u32 i, j, action, rts_table;
3806 u64 data0;
3807 u64 data1;
3808 u32 max_entries;
3809 enum vxge_hw_status status = VXGE_HW_OK;
3810 struct __vxge_hw_vpath_handle *vp = vpath_handles[0];
3811
3812 if (vp == NULL) {
3813 status = VXGE_HW_ERR_INVALID_HANDLE;
3814 goto exit;
3815 }
3816
3817 max_entries = (((u32)1) << itable_size);
3818
3819 if (vp->vpath->hldev->config.rth_it_type
3820 == VXGE_HW_RTH_IT_TYPE_SOLO_IT) {
3821 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3822 rts_table =
3823 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT;
3824
3825 for (j = 0; j < max_entries; j++) {
3826
3827 data1 = 0;
3828
3829 data0 =
3830 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3831 itable[j]);
3832
3833 status = __vxge_hw_vpath_rts_table_set(vpath_handles[0],
3834 action, rts_table, j, data0, data1);
3835
3836 if (status != VXGE_HW_OK)
3837 goto exit;
3838 }
3839
3840 for (j = 0; j < max_entries; j++) {
3841
3842 data1 = 0;
3843
3844 data0 =
3845 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN |
3846 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3847 itable[j]);
3848
3849 status = __vxge_hw_vpath_rts_table_set(
3850 vpath_handles[mtable[itable[j]]], action,
3851 rts_table, j, data0, data1);
3852
3853 if (status != VXGE_HW_OK)
3854 goto exit;
3855 }
3856 } else {
3857 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3858 rts_table =
3859 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT;
3860 for (i = 0; i < vpath_count; i++) {
3861
3862 for (j = 0; j < max_entries;) {
3863
3864 data0 = 0;
3865 data1 = 0;
3866
3867 while (j < max_entries) {
3868 if (mtable[itable[j]] != i) {
3869 j++;
3870 continue;
3871 }
3872 vxge_hw_rts_rth_data0_data1_get(j,
3873 &data0, &data1, 1, itable);
3874 j++;
3875 break;
3876 }
3877
3878 while (j < max_entries) {
3879 if (mtable[itable[j]] != i) {
3880 j++;
3881 continue;
3882 }
3883 vxge_hw_rts_rth_data0_data1_get(j,
3884 &data0, &data1, 2, itable);
3885 j++;
3886 break;
3887 }
3888
3889 while (j < max_entries) {
3890 if (mtable[itable[j]] != i) {
3891 j++;
3892 continue;
3893 }
3894 vxge_hw_rts_rth_data0_data1_get(j,
3895 &data0, &data1, 3, itable);
3896 j++;
3897 break;
3898 }
3899
3900 while (j < max_entries) {
3901 if (mtable[itable[j]] != i) {
3902 j++;
3903 continue;
3904 }
3905 vxge_hw_rts_rth_data0_data1_get(j,
3906 &data0, &data1, 4, itable);
3907 j++;
3908 break;
3909 }
3910
3911 if (data0 != 0) {
3912 status = __vxge_hw_vpath_rts_table_set(
3913 vpath_handles[i],
3914 action, rts_table,
3915 0, data0, data1);
3916
3917 if (status != VXGE_HW_OK)
3918 goto exit;
3919 }
3920 }
3921 }
3922 }
3923 exit:
3924 return status;
3925 }
3926
3927 /**
3928 * vxge_hw_vpath_check_leak - Check for memory leak
3929 * @ringh: Handle to the ring object used for receive
3930 *
3931 * If PRC_RXD_DOORBELL_VPn.NEW_QW_CNT is larger or equal to
3932 * PRC_CFG6_VPn.RXD_SPAT then a leak has occurred.
3933 * Returns: VXGE_HW_FAIL, if leak has occurred.
3934 *
3935 */
3936 enum vxge_hw_status
vxge_hw_vpath_check_leak(struct __vxge_hw_ring * ring)3937 vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ring)
3938 {
3939 enum vxge_hw_status status = VXGE_HW_OK;
3940 u64 rxd_new_count, rxd_spat;
3941
3942 if (ring == NULL)
3943 return status;
3944
3945 rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell);
3946 rxd_spat = readq(&ring->vp_reg->prc_cfg6);
3947 rxd_spat = VXGE_HW_PRC_CFG6_RXD_SPAT(rxd_spat);
3948
3949 if (rxd_new_count >= rxd_spat)
3950 status = VXGE_HW_FAIL;
3951
3952 return status;
3953 }
3954
3955 /*
3956 * __vxge_hw_vpath_mgmt_read
3957 * This routine reads the vpath_mgmt registers
3958 */
3959 static enum vxge_hw_status
__vxge_hw_vpath_mgmt_read(struct __vxge_hw_device * hldev,struct __vxge_hw_virtualpath * vpath)3960 __vxge_hw_vpath_mgmt_read(
3961 struct __vxge_hw_device *hldev,
3962 struct __vxge_hw_virtualpath *vpath)
3963 {
3964 u32 i, mtu = 0, max_pyld = 0;
3965 u64 val64;
3966
3967 for (i = 0; i < VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
3968
3969 val64 = readq(&vpath->vpmgmt_reg->
3970 rxmac_cfg0_port_vpmgmt_clone[i]);
3971 max_pyld =
3972 (u32)
3973 VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN
3974 (val64);
3975 if (mtu < max_pyld)
3976 mtu = max_pyld;
3977 }
3978
3979 vpath->max_mtu = mtu + VXGE_HW_MAC_HEADER_MAX_SIZE;
3980
3981 val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp);
3982
3983 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3984 if (val64 & vxge_mBIT(i))
3985 vpath->vsport_number = i;
3986 }
3987
3988 val64 = readq(&vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
3989
3990 if (val64 & VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK)
3991 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_UP);
3992 else
3993 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_DOWN);
3994
3995 return VXGE_HW_OK;
3996 }
3997
3998 /*
3999 * __vxge_hw_vpath_reset_check - Check if resetting the vpath completed
4000 * This routine checks the vpath_rst_in_prog register to see if
4001 * adapter completed the reset process for the vpath
4002 */
4003 static enum vxge_hw_status
__vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath * vpath)4004 __vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath)
4005 {
4006 enum vxge_hw_status status;
4007
4008 status = __vxge_hw_device_register_poll(
4009 &vpath->hldev->common_reg->vpath_rst_in_prog,
4010 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(
4011 1 << (16 - vpath->vp_id)),
4012 vpath->hldev->config.device_poll_millis);
4013
4014 return status;
4015 }
4016
4017 /*
4018 * __vxge_hw_vpath_reset
4019 * This routine resets the vpath on the device
4020 */
4021 static enum vxge_hw_status
__vxge_hw_vpath_reset(struct __vxge_hw_device * hldev,u32 vp_id)4022 __vxge_hw_vpath_reset(struct __vxge_hw_device *hldev, u32 vp_id)
4023 {
4024 u64 val64;
4025
4026 val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id));
4027
4028 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
4029 &hldev->common_reg->cmn_rsthdlr_cfg0);
4030
4031 return VXGE_HW_OK;
4032 }
4033
4034 /*
4035 * __vxge_hw_vpath_sw_reset
4036 * This routine resets the vpath structures
4037 */
4038 static enum vxge_hw_status
__vxge_hw_vpath_sw_reset(struct __vxge_hw_device * hldev,u32 vp_id)4039 __vxge_hw_vpath_sw_reset(struct __vxge_hw_device *hldev, u32 vp_id)
4040 {
4041 enum vxge_hw_status status = VXGE_HW_OK;
4042 struct __vxge_hw_virtualpath *vpath;
4043
4044 vpath = &hldev->virtual_paths[vp_id];
4045
4046 if (vpath->ringh) {
4047 status = __vxge_hw_ring_reset(vpath->ringh);
4048 if (status != VXGE_HW_OK)
4049 goto exit;
4050 }
4051
4052 if (vpath->fifoh)
4053 status = __vxge_hw_fifo_reset(vpath->fifoh);
4054 exit:
4055 return status;
4056 }
4057
4058 /*
4059 * __vxge_hw_vpath_prc_configure
4060 * This routine configures the prc registers of virtual path using the config
4061 * passed
4062 */
4063 static void
__vxge_hw_vpath_prc_configure(struct __vxge_hw_device * hldev,u32 vp_id)4064 __vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4065 {
4066 u64 val64;
4067 struct __vxge_hw_virtualpath *vpath;
4068 struct vxge_hw_vp_config *vp_config;
4069 struct vxge_hw_vpath_reg __iomem *vp_reg;
4070
4071 vpath = &hldev->virtual_paths[vp_id];
4072 vp_reg = vpath->vp_reg;
4073 vp_config = vpath->vp_config;
4074
4075 if (vp_config->ring.enable == VXGE_HW_RING_DISABLE)
4076 return;
4077
4078 val64 = readq(&vp_reg->prc_cfg1);
4079 val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE;
4080 writeq(val64, &vp_reg->prc_cfg1);
4081
4082 val64 = readq(&vpath->vp_reg->prc_cfg6);
4083 val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN;
4084 writeq(val64, &vpath->vp_reg->prc_cfg6);
4085
4086 val64 = readq(&vp_reg->prc_cfg7);
4087
4088 if (vpath->vp_config->ring.scatter_mode !=
4089 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT) {
4090
4091 val64 &= ~VXGE_HW_PRC_CFG7_SCATTER_MODE(0x3);
4092
4093 switch (vpath->vp_config->ring.scatter_mode) {
4094 case VXGE_HW_RING_SCATTER_MODE_A:
4095 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4096 VXGE_HW_PRC_CFG7_SCATTER_MODE_A);
4097 break;
4098 case VXGE_HW_RING_SCATTER_MODE_B:
4099 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4100 VXGE_HW_PRC_CFG7_SCATTER_MODE_B);
4101 break;
4102 case VXGE_HW_RING_SCATTER_MODE_C:
4103 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4104 VXGE_HW_PRC_CFG7_SCATTER_MODE_C);
4105 break;
4106 }
4107 }
4108
4109 writeq(val64, &vp_reg->prc_cfg7);
4110
4111 writeq(VXGE_HW_PRC_CFG5_RXD0_ADD(
4112 __vxge_hw_ring_first_block_address_get(
4113 vpath->ringh) >> 3), &vp_reg->prc_cfg5);
4114
4115 val64 = readq(&vp_reg->prc_cfg4);
4116 val64 |= VXGE_HW_PRC_CFG4_IN_SVC;
4117 val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3);
4118
4119 val64 |= VXGE_HW_PRC_CFG4_RING_MODE(
4120 VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER);
4121
4122 if (hldev->config.rth_en == VXGE_HW_RTH_DISABLE)
4123 val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE;
4124 else
4125 val64 &= ~VXGE_HW_PRC_CFG4_RTH_DISABLE;
4126
4127 writeq(val64, &vp_reg->prc_cfg4);
4128 }
4129
4130 /*
4131 * __vxge_hw_vpath_kdfc_configure
4132 * This routine configures the kdfc registers of virtual path using the
4133 * config passed
4134 */
4135 static enum vxge_hw_status
__vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device * hldev,u32 vp_id)4136 __vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4137 {
4138 u64 val64;
4139 u64 vpath_stride;
4140 enum vxge_hw_status status = VXGE_HW_OK;
4141 struct __vxge_hw_virtualpath *vpath;
4142 struct vxge_hw_vpath_reg __iomem *vp_reg;
4143
4144 vpath = &hldev->virtual_paths[vp_id];
4145 vp_reg = vpath->vp_reg;
4146 status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);
4147
4148 if (status != VXGE_HW_OK)
4149 goto exit;
4150
4151 val64 = readq(&vp_reg->kdfc_drbl_triplet_total);
4152
4153 vpath->max_kdfc_db =
4154 (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(
4155 val64+1)/2;
4156
4157 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4158
4159 vpath->max_nofl_db = vpath->max_kdfc_db;
4160
4161 if (vpath->max_nofl_db <
4162 ((vpath->vp_config->fifo.memblock_size /
4163 (vpath->vp_config->fifo.max_frags *
4164 sizeof(struct vxge_hw_fifo_txd))) *
4165 vpath->vp_config->fifo.fifo_blocks)) {
4166
4167 return VXGE_HW_BADCFG_FIFO_BLOCKS;
4168 }
4169 val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(
4170 (vpath->max_nofl_db*2)-1);
4171 }
4172
4173 writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);
4174
4175 writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE,
4176 &vp_reg->kdfc_fifo_trpl_ctrl);
4177
4178 val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);
4179
4180 val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) |
4181 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF));
4182
4183 val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(
4184 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
4185 #ifndef __BIG_ENDIAN
4186 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
4187 #endif
4188 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
4189
4190 writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);
4191 writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);
4192 wmb();
4193 vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride);
4194
4195 vpath->nofl_db =
4196 (struct __vxge_hw_non_offload_db_wrapper __iomem *)
4197 (hldev->kdfc + (vp_id *
4198 VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
4199 vpath_stride)));
4200 exit:
4201 return status;
4202 }
4203
4204 /*
4205 * __vxge_hw_vpath_mac_configure
4206 * This routine configures the mac of virtual path using the config passed
4207 */
4208 static enum vxge_hw_status
__vxge_hw_vpath_mac_configure(struct __vxge_hw_device * hldev,u32 vp_id)4209 __vxge_hw_vpath_mac_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4210 {
4211 u64 val64;
4212 struct __vxge_hw_virtualpath *vpath;
4213 struct vxge_hw_vp_config *vp_config;
4214 struct vxge_hw_vpath_reg __iomem *vp_reg;
4215
4216 vpath = &hldev->virtual_paths[vp_id];
4217 vp_reg = vpath->vp_reg;
4218 vp_config = vpath->vp_config;
4219
4220 writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(
4221 vpath->vsport_number), &vp_reg->xmac_vsport_choice);
4222
4223 if (vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4224
4225 val64 = readq(&vp_reg->xmac_rpa_vcfg);
4226
4227 if (vp_config->rpa_strip_vlan_tag !=
4228 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) {
4229 if (vp_config->rpa_strip_vlan_tag)
4230 val64 |= VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4231 else
4232 val64 &= ~VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4233 }
4234
4235 writeq(val64, &vp_reg->xmac_rpa_vcfg);
4236 val64 = readq(&vp_reg->rxmac_vcfg0);
4237
4238 if (vp_config->mtu !=
4239 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) {
4240 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4241 if ((vp_config->mtu +
4242 VXGE_HW_MAC_HEADER_MAX_SIZE) < vpath->max_mtu)
4243 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
4244 vp_config->mtu +
4245 VXGE_HW_MAC_HEADER_MAX_SIZE);
4246 else
4247 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
4248 vpath->max_mtu);
4249 }
4250
4251 writeq(val64, &vp_reg->rxmac_vcfg0);
4252
4253 val64 = readq(&vp_reg->rxmac_vcfg1);
4254
4255 val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) |
4256 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE);
4257
4258 if (hldev->config.rth_it_type ==
4259 VXGE_HW_RTH_IT_TYPE_MULTI_IT) {
4260 val64 |= VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(
4261 0x2) |
4262 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE;
4263 }
4264
4265 writeq(val64, &vp_reg->rxmac_vcfg1);
4266 }
4267 return VXGE_HW_OK;
4268 }
4269
4270 /*
4271 * __vxge_hw_vpath_tim_configure
4272 * This routine configures the tim registers of virtual path using the config
4273 * passed
4274 */
4275 static enum vxge_hw_status
__vxge_hw_vpath_tim_configure(struct __vxge_hw_device * hldev,u32 vp_id)4276 __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4277 {
4278 u64 val64;
4279 struct __vxge_hw_virtualpath *vpath;
4280 struct vxge_hw_vpath_reg __iomem *vp_reg;
4281 struct vxge_hw_vp_config *config;
4282
4283 vpath = &hldev->virtual_paths[vp_id];
4284 vp_reg = vpath->vp_reg;
4285 config = vpath->vp_config;
4286
4287 writeq(0, &vp_reg->tim_dest_addr);
4288 writeq(0, &vp_reg->tim_vpath_map);
4289 writeq(0, &vp_reg->tim_bitmap);
4290 writeq(0, &vp_reg->tim_remap);
4291
4292 if (config->ring.enable == VXGE_HW_RING_ENABLE)
4293 writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM(
4294 (vp_id * VXGE_HW_MAX_INTR_PER_VP) +
4295 VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);
4296
4297 val64 = readq(&vp_reg->tim_pci_cfg);
4298 val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD;
4299 writeq(val64, &vp_reg->tim_pci_cfg);
4300
4301 if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4302
4303 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4304
4305 if (config->tti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4306 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4307 0x3ffffff);
4308 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4309 config->tti.btimer_val);
4310 }
4311
4312 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
4313
4314 if (config->tti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
4315 if (config->tti.timer_ac_en)
4316 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4317 else
4318 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4319 }
4320
4321 if (config->tti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
4322 if (config->tti.timer_ci_en)
4323 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4324 else
4325 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4326 }
4327
4328 if (config->tti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
4329 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
4330 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
4331 config->tti.urange_a);
4332 }
4333
4334 if (config->tti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
4335 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
4336 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
4337 config->tti.urange_b);
4338 }
4339
4340 if (config->tti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
4341 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
4342 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
4343 config->tti.urange_c);
4344 }
4345
4346 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4347 vpath->tim_tti_cfg1_saved = val64;
4348
4349 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
4350
4351 if (config->tti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
4352 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
4353 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
4354 config->tti.uec_a);
4355 }
4356
4357 if (config->tti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
4358 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
4359 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
4360 config->tti.uec_b);
4361 }
4362
4363 if (config->tti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
4364 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
4365 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
4366 config->tti.uec_c);
4367 }
4368
4369 if (config->tti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
4370 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
4371 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
4372 config->tti.uec_d);
4373 }
4374
4375 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
4376 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
4377
4378 if (config->tti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
4379 if (config->tti.timer_ri_en)
4380 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4381 else
4382 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4383 }
4384
4385 if (config->tti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4386 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4387 0x3ffffff);
4388 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4389 config->tti.rtimer_val);
4390 }
4391
4392 if (config->tti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
4393 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
4394 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
4395 }
4396
4397 if (config->tti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4398 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4399 0x3ffffff);
4400 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4401 config->tti.ltimer_val);
4402 }
4403
4404 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
4405 vpath->tim_tti_cfg3_saved = val64;
4406 }
4407
4408 if (config->ring.enable == VXGE_HW_RING_ENABLE) {
4409
4410 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
4411
4412 if (config->rti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4413 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4414 0x3ffffff);
4415 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4416 config->rti.btimer_val);
4417 }
4418
4419 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
4420
4421 if (config->rti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
4422 if (config->rti.timer_ac_en)
4423 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4424 else
4425 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4426 }
4427
4428 if (config->rti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
4429 if (config->rti.timer_ci_en)
4430 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4431 else
4432 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4433 }
4434
4435 if (config->rti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
4436 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
4437 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
4438 config->rti.urange_a);
4439 }
4440
4441 if (config->rti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
4442 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
4443 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
4444 config->rti.urange_b);
4445 }
4446
4447 if (config->rti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
4448 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
4449 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
4450 config->rti.urange_c);
4451 }
4452
4453 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
4454 vpath->tim_rti_cfg1_saved = val64;
4455
4456 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
4457
4458 if (config->rti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
4459 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
4460 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
4461 config->rti.uec_a);
4462 }
4463
4464 if (config->rti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
4465 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
4466 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
4467 config->rti.uec_b);
4468 }
4469
4470 if (config->rti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
4471 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
4472 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
4473 config->rti.uec_c);
4474 }
4475
4476 if (config->rti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
4477 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
4478 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
4479 config->rti.uec_d);
4480 }
4481
4482 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
4483 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
4484
4485 if (config->rti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
4486 if (config->rti.timer_ri_en)
4487 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4488 else
4489 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4490 }
4491
4492 if (config->rti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4493 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4494 0x3ffffff);
4495 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4496 config->rti.rtimer_val);
4497 }
4498
4499 if (config->rti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
4500 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
4501 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
4502 }
4503
4504 if (config->rti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4505 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4506 0x3ffffff);
4507 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4508 config->rti.ltimer_val);
4509 }
4510
4511 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
4512 vpath->tim_rti_cfg3_saved = val64;
4513 }
4514
4515 val64 = 0;
4516 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4517 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4518 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4519 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4520 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4521 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4522
4523 val64 = VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(150);
4524 val64 |= VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(0);
4525 val64 |= VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX(3);
4526 writeq(val64, &vp_reg->tim_wrkld_clc);
4527
4528 return VXGE_HW_OK;
4529 }
4530
4531 /*
4532 * __vxge_hw_vpath_initialize
4533 * This routine is the final phase of init which initializes the
4534 * registers of the vpath using the configuration passed.
4535 */
4536 static enum vxge_hw_status
__vxge_hw_vpath_initialize(struct __vxge_hw_device * hldev,u32 vp_id)4537 __vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id)
4538 {
4539 u64 val64;
4540 u32 val32;
4541 enum vxge_hw_status status = VXGE_HW_OK;
4542 struct __vxge_hw_virtualpath *vpath;
4543 struct vxge_hw_vpath_reg __iomem *vp_reg;
4544
4545 vpath = &hldev->virtual_paths[vp_id];
4546
4547 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4548 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4549 goto exit;
4550 }
4551 vp_reg = vpath->vp_reg;
4552
4553 status = __vxge_hw_vpath_swapper_set(vpath->vp_reg);
4554 if (status != VXGE_HW_OK)
4555 goto exit;
4556
4557 status = __vxge_hw_vpath_mac_configure(hldev, vp_id);
4558 if (status != VXGE_HW_OK)
4559 goto exit;
4560
4561 status = __vxge_hw_vpath_kdfc_configure(hldev, vp_id);
4562 if (status != VXGE_HW_OK)
4563 goto exit;
4564
4565 status = __vxge_hw_vpath_tim_configure(hldev, vp_id);
4566 if (status != VXGE_HW_OK)
4567 goto exit;
4568
4569 val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);
4570
4571 /* Get MRRS value from device control */
4572 status = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32);
4573 if (status == VXGE_HW_OK) {
4574 val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12;
4575 val64 &=
4576 ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7));
4577 val64 |=
4578 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32);
4579
4580 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE;
4581 }
4582
4583 val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7));
4584 val64 |=
4585 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(
4586 VXGE_HW_MAX_PAYLOAD_SIZE_512);
4587
4588 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN;
4589 writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);
4590
4591 exit:
4592 return status;
4593 }
4594
4595 /*
4596 * __vxge_hw_vp_terminate - Terminate Virtual Path structure
4597 * This routine closes all channels it opened and freeup memory
4598 */
__vxge_hw_vp_terminate(struct __vxge_hw_device * hldev,u32 vp_id)4599 static void __vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, u32 vp_id)
4600 {
4601 struct __vxge_hw_virtualpath *vpath;
4602
4603 vpath = &hldev->virtual_paths[vp_id];
4604
4605 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN)
4606 goto exit;
4607
4608 VXGE_HW_DEVICE_TIM_INT_MASK_RESET(vpath->hldev->tim_int_mask0,
4609 vpath->hldev->tim_int_mask1, vpath->vp_id);
4610 hldev->stats.hw_dev_info_stats.vpath_info[vpath->vp_id] = NULL;
4611
4612 /* If the whole struct __vxge_hw_virtualpath is zeroed, nothing will
4613 * work after the interface is brought down.
4614 */
4615 spin_lock(&vpath->lock);
4616 vpath->vp_open = VXGE_HW_VP_NOT_OPEN;
4617 spin_unlock(&vpath->lock);
4618
4619 vpath->vpmgmt_reg = NULL;
4620 vpath->nofl_db = NULL;
4621 vpath->max_mtu = 0;
4622 vpath->vsport_number = 0;
4623 vpath->max_kdfc_db = 0;
4624 vpath->max_nofl_db = 0;
4625 vpath->ringh = NULL;
4626 vpath->fifoh = NULL;
4627 memset(&vpath->vpath_handles, 0, sizeof(struct list_head));
4628 vpath->stats_block = NULL;
4629 vpath->hw_stats = NULL;
4630 vpath->hw_stats_sav = NULL;
4631 vpath->sw_stats = NULL;
4632
4633 exit:
4634 return;
4635 }
4636
4637 /*
4638 * __vxge_hw_vp_initialize - Initialize Virtual Path structure
4639 * This routine is the initial phase of init which resets the vpath and
4640 * initializes the software support structures.
4641 */
4642 static enum vxge_hw_status
__vxge_hw_vp_initialize(struct __vxge_hw_device * hldev,u32 vp_id,struct vxge_hw_vp_config * config)4643 __vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id,
4644 struct vxge_hw_vp_config *config)
4645 {
4646 struct __vxge_hw_virtualpath *vpath;
4647 enum vxge_hw_status status = VXGE_HW_OK;
4648
4649 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4650 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4651 goto exit;
4652 }
4653
4654 vpath = &hldev->virtual_paths[vp_id];
4655
4656 spin_lock_init(&vpath->lock);
4657 vpath->vp_id = vp_id;
4658 vpath->vp_open = VXGE_HW_VP_OPEN;
4659 vpath->hldev = hldev;
4660 vpath->vp_config = config;
4661 vpath->vp_reg = hldev->vpath_reg[vp_id];
4662 vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id];
4663
4664 __vxge_hw_vpath_reset(hldev, vp_id);
4665
4666 status = __vxge_hw_vpath_reset_check(vpath);
4667 if (status != VXGE_HW_OK) {
4668 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4669 goto exit;
4670 }
4671
4672 status = __vxge_hw_vpath_mgmt_read(hldev, vpath);
4673 if (status != VXGE_HW_OK) {
4674 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4675 goto exit;
4676 }
4677
4678 INIT_LIST_HEAD(&vpath->vpath_handles);
4679
4680 vpath->sw_stats = &hldev->stats.sw_dev_info_stats.vpath_info[vp_id];
4681
4682 VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0,
4683 hldev->tim_int_mask1, vp_id);
4684
4685 status = __vxge_hw_vpath_initialize(hldev, vp_id);
4686 if (status != VXGE_HW_OK)
4687 __vxge_hw_vp_terminate(hldev, vp_id);
4688 exit:
4689 return status;
4690 }
4691
4692 /*
4693 * vxge_hw_vpath_mtu_set - Set MTU.
4694 * Set new MTU value. Example, to use jumbo frames:
4695 * vxge_hw_vpath_mtu_set(my_device, 9600);
4696 */
4697 enum vxge_hw_status
vxge_hw_vpath_mtu_set(struct __vxge_hw_vpath_handle * vp,u32 new_mtu)4698 vxge_hw_vpath_mtu_set(struct __vxge_hw_vpath_handle *vp, u32 new_mtu)
4699 {
4700 u64 val64;
4701 enum vxge_hw_status status = VXGE_HW_OK;
4702 struct __vxge_hw_virtualpath *vpath;
4703
4704 if (vp == NULL) {
4705 status = VXGE_HW_ERR_INVALID_HANDLE;
4706 goto exit;
4707 }
4708 vpath = vp->vpath;
4709
4710 new_mtu += VXGE_HW_MAC_HEADER_MAX_SIZE;
4711
4712 if ((new_mtu < VXGE_HW_MIN_MTU) || (new_mtu > vpath->max_mtu))
4713 status = VXGE_HW_ERR_INVALID_MTU_SIZE;
4714
4715 val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
4716
4717 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4718 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu);
4719
4720 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
4721
4722 vpath->vp_config->mtu = new_mtu - VXGE_HW_MAC_HEADER_MAX_SIZE;
4723
4724 exit:
4725 return status;
4726 }
4727
4728 /*
4729 * vxge_hw_vpath_stats_enable - Enable vpath h/wstatistics.
4730 * Enable the DMA vpath statistics. The function is to be called to re-enable
4731 * the adapter to update stats into the host memory
4732 */
4733 static enum vxge_hw_status
vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle * vp)4734 vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vp)
4735 {
4736 enum vxge_hw_status status = VXGE_HW_OK;
4737 struct __vxge_hw_virtualpath *vpath;
4738
4739 vpath = vp->vpath;
4740
4741 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4742 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4743 goto exit;
4744 }
4745
4746 memcpy(vpath->hw_stats_sav, vpath->hw_stats,
4747 sizeof(struct vxge_hw_vpath_stats_hw_info));
4748
4749 status = __vxge_hw_vpath_stats_get(vpath, vpath->hw_stats);
4750 exit:
4751 return status;
4752 }
4753
4754 /*
4755 * __vxge_hw_blockpool_block_allocate - Allocates a block from block pool
4756 * This function allocates a block from block pool or from the system
4757 */
4758 static struct __vxge_hw_blockpool_entry *
__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device * devh,u32 size)4759 __vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *devh, u32 size)
4760 {
4761 struct __vxge_hw_blockpool_entry *entry = NULL;
4762 struct __vxge_hw_blockpool *blockpool;
4763
4764 blockpool = &devh->block_pool;
4765
4766 if (size == blockpool->block_size) {
4767
4768 if (!list_empty(&blockpool->free_block_list))
4769 entry = (struct __vxge_hw_blockpool_entry *)
4770 list_first_entry(&blockpool->free_block_list,
4771 struct __vxge_hw_blockpool_entry,
4772 item);
4773
4774 if (entry != NULL) {
4775 list_del(&entry->item);
4776 blockpool->pool_size--;
4777 }
4778 }
4779
4780 if (entry != NULL)
4781 __vxge_hw_blockpool_blocks_add(blockpool);
4782
4783 return entry;
4784 }
4785
4786 /*
4787 * vxge_hw_vpath_open - Open a virtual path on a given adapter
4788 * This function is used to open access to virtual path of an
4789 * adapter for offload, GRO operations. This function returns
4790 * synchronously.
4791 */
4792 enum vxge_hw_status
vxge_hw_vpath_open(struct __vxge_hw_device * hldev,struct vxge_hw_vpath_attr * attr,struct __vxge_hw_vpath_handle ** vpath_handle)4793 vxge_hw_vpath_open(struct __vxge_hw_device *hldev,
4794 struct vxge_hw_vpath_attr *attr,
4795 struct __vxge_hw_vpath_handle **vpath_handle)
4796 {
4797 struct __vxge_hw_virtualpath *vpath;
4798 struct __vxge_hw_vpath_handle *vp;
4799 enum vxge_hw_status status;
4800
4801 vpath = &hldev->virtual_paths[attr->vp_id];
4802
4803 if (vpath->vp_open == VXGE_HW_VP_OPEN) {
4804 status = VXGE_HW_ERR_INVALID_STATE;
4805 goto vpath_open_exit1;
4806 }
4807
4808 status = __vxge_hw_vp_initialize(hldev, attr->vp_id,
4809 &hldev->config.vp_config[attr->vp_id]);
4810 if (status != VXGE_HW_OK)
4811 goto vpath_open_exit1;
4812
4813 vp = vzalloc(sizeof(struct __vxge_hw_vpath_handle));
4814 if (vp == NULL) {
4815 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4816 goto vpath_open_exit2;
4817 }
4818
4819 vp->vpath = vpath;
4820
4821 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4822 status = __vxge_hw_fifo_create(vp, &attr->fifo_attr);
4823 if (status != VXGE_HW_OK)
4824 goto vpath_open_exit6;
4825 }
4826
4827 if (vpath->vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4828 status = __vxge_hw_ring_create(vp, &attr->ring_attr);
4829 if (status != VXGE_HW_OK)
4830 goto vpath_open_exit7;
4831
4832 __vxge_hw_vpath_prc_configure(hldev, attr->vp_id);
4833 }
4834
4835 vpath->fifoh->tx_intr_num =
4836 (attr->vp_id * VXGE_HW_MAX_INTR_PER_VP) +
4837 VXGE_HW_VPATH_INTR_TX;
4838
4839 vpath->stats_block = __vxge_hw_blockpool_block_allocate(hldev,
4840 VXGE_HW_BLOCK_SIZE);
4841 if (vpath->stats_block == NULL) {
4842 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4843 goto vpath_open_exit8;
4844 }
4845
4846 vpath->hw_stats = vpath->stats_block->memblock;
4847 memset(vpath->hw_stats, 0,
4848 sizeof(struct vxge_hw_vpath_stats_hw_info));
4849
4850 hldev->stats.hw_dev_info_stats.vpath_info[attr->vp_id] =
4851 vpath->hw_stats;
4852
4853 vpath->hw_stats_sav =
4854 &hldev->stats.hw_dev_info_stats.vpath_info_sav[attr->vp_id];
4855 memset(vpath->hw_stats_sav, 0,
4856 sizeof(struct vxge_hw_vpath_stats_hw_info));
4857
4858 writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);
4859
4860 status = vxge_hw_vpath_stats_enable(vp);
4861 if (status != VXGE_HW_OK)
4862 goto vpath_open_exit8;
4863
4864 list_add(&vp->item, &vpath->vpath_handles);
4865
4866 hldev->vpaths_deployed |= vxge_mBIT(vpath->vp_id);
4867
4868 *vpath_handle = vp;
4869
4870 attr->fifo_attr.userdata = vpath->fifoh;
4871 attr->ring_attr.userdata = vpath->ringh;
4872
4873 return VXGE_HW_OK;
4874
4875 vpath_open_exit8:
4876 if (vpath->ringh != NULL)
4877 __vxge_hw_ring_delete(vp);
4878 vpath_open_exit7:
4879 if (vpath->fifoh != NULL)
4880 __vxge_hw_fifo_delete(vp);
4881 vpath_open_exit6:
4882 vfree(vp);
4883 vpath_open_exit2:
4884 __vxge_hw_vp_terminate(hldev, attr->vp_id);
4885 vpath_open_exit1:
4886
4887 return status;
4888 }
4889
4890 /**
4891 * vxge_hw_vpath_rx_doorbell_post - Close the handle got from previous vpath
4892 * (vpath) open
4893 * @vp: Handle got from previous vpath open
4894 *
4895 * This function is used to close access to virtual path opened
4896 * earlier.
4897 */
vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle * vp)4898 void vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp)
4899 {
4900 struct __vxge_hw_virtualpath *vpath = vp->vpath;
4901 struct __vxge_hw_ring *ring = vpath->ringh;
4902 struct vxgedev *vdev = netdev_priv(vpath->hldev->ndev);
4903 u64 new_count, val64, val164;
4904
4905 if (vdev->titan1) {
4906 new_count = readq(&vpath->vp_reg->rxdmem_size);
4907 new_count &= 0x1fff;
4908 } else
4909 new_count = ring->config->ring_blocks * VXGE_HW_BLOCK_SIZE / 8;
4910
4911 val164 = VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count);
4912
4913 writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164),
4914 &vpath->vp_reg->prc_rxd_doorbell);
4915 readl(&vpath->vp_reg->prc_rxd_doorbell);
4916
4917 val164 /= 2;
4918 val64 = readq(&vpath->vp_reg->prc_cfg6);
4919 val64 = VXGE_HW_PRC_CFG6_RXD_SPAT(val64);
4920 val64 &= 0x1ff;
4921
4922 /*
4923 * Each RxD is of 4 qwords
4924 */
4925 new_count -= (val64 + 1);
4926 val64 = min(val164, new_count) / 4;
4927
4928 ring->rxds_limit = min(ring->rxds_limit, val64);
4929 if (ring->rxds_limit < 4)
4930 ring->rxds_limit = 4;
4931 }
4932
4933 /*
4934 * __vxge_hw_blockpool_block_free - Frees a block from block pool
4935 * @devh: Hal device
4936 * @entry: Entry of block to be freed
4937 *
4938 * This function frees a block from block pool
4939 */
4940 static void
__vxge_hw_blockpool_block_free(struct __vxge_hw_device * devh,struct __vxge_hw_blockpool_entry * entry)4941 __vxge_hw_blockpool_block_free(struct __vxge_hw_device *devh,
4942 struct __vxge_hw_blockpool_entry *entry)
4943 {
4944 struct __vxge_hw_blockpool *blockpool;
4945
4946 blockpool = &devh->block_pool;
4947
4948 if (entry->length == blockpool->block_size) {
4949 list_add(&entry->item, &blockpool->free_block_list);
4950 blockpool->pool_size++;
4951 }
4952
4953 __vxge_hw_blockpool_blocks_remove(blockpool);
4954 }
4955
4956 /*
4957 * vxge_hw_vpath_close - Close the handle got from previous vpath (vpath) open
4958 * This function is used to close access to virtual path opened
4959 * earlier.
4960 */
vxge_hw_vpath_close(struct __vxge_hw_vpath_handle * vp)4961 enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_vpath_handle *vp)
4962 {
4963 struct __vxge_hw_virtualpath *vpath = NULL;
4964 struct __vxge_hw_device *devh = NULL;
4965 u32 vp_id = vp->vpath->vp_id;
4966 u32 is_empty = TRUE;
4967 enum vxge_hw_status status = VXGE_HW_OK;
4968
4969 vpath = vp->vpath;
4970 devh = vpath->hldev;
4971
4972 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4973 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4974 goto vpath_close_exit;
4975 }
4976
4977 list_del(&vp->item);
4978
4979 if (!list_empty(&vpath->vpath_handles)) {
4980 list_add(&vp->item, &vpath->vpath_handles);
4981 is_empty = FALSE;
4982 }
4983
4984 if (!is_empty) {
4985 status = VXGE_HW_FAIL;
4986 goto vpath_close_exit;
4987 }
4988
4989 devh->vpaths_deployed &= ~vxge_mBIT(vp_id);
4990
4991 if (vpath->ringh != NULL)
4992 __vxge_hw_ring_delete(vp);
4993
4994 if (vpath->fifoh != NULL)
4995 __vxge_hw_fifo_delete(vp);
4996
4997 if (vpath->stats_block != NULL)
4998 __vxge_hw_blockpool_block_free(devh, vpath->stats_block);
4999
5000 vfree(vp);
5001
5002 __vxge_hw_vp_terminate(devh, vp_id);
5003
5004 vpath_close_exit:
5005 return status;
5006 }
5007
5008 /*
5009 * vxge_hw_vpath_reset - Resets vpath
5010 * This function is used to request a reset of vpath
5011 */
vxge_hw_vpath_reset(struct __vxge_hw_vpath_handle * vp)5012 enum vxge_hw_status vxge_hw_vpath_reset(struct __vxge_hw_vpath_handle *vp)
5013 {
5014 enum vxge_hw_status status;
5015 u32 vp_id;
5016 struct __vxge_hw_virtualpath *vpath = vp->vpath;
5017
5018 vp_id = vpath->vp_id;
5019
5020 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
5021 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
5022 goto exit;
5023 }
5024
5025 status = __vxge_hw_vpath_reset(vpath->hldev, vp_id);
5026 if (status == VXGE_HW_OK)
5027 vpath->sw_stats->soft_reset_cnt++;
5028 exit:
5029 return status;
5030 }
5031
5032 /*
5033 * vxge_hw_vpath_recover_from_reset - Poll for reset complete and re-initialize.
5034 * This function poll's for the vpath reset completion and re initializes
5035 * the vpath.
5036 */
5037 enum vxge_hw_status
vxge_hw_vpath_recover_from_reset(struct __vxge_hw_vpath_handle * vp)5038 vxge_hw_vpath_recover_from_reset(struct __vxge_hw_vpath_handle *vp)
5039 {
5040 struct __vxge_hw_virtualpath *vpath = NULL;
5041 enum vxge_hw_status status;
5042 struct __vxge_hw_device *hldev;
5043 u32 vp_id;
5044
5045 vp_id = vp->vpath->vp_id;
5046 vpath = vp->vpath;
5047 hldev = vpath->hldev;
5048
5049 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
5050 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
5051 goto exit;
5052 }
5053
5054 status = __vxge_hw_vpath_reset_check(vpath);
5055 if (status != VXGE_HW_OK)
5056 goto exit;
5057
5058 status = __vxge_hw_vpath_sw_reset(hldev, vp_id);
5059 if (status != VXGE_HW_OK)
5060 goto exit;
5061
5062 status = __vxge_hw_vpath_initialize(hldev, vp_id);
5063 if (status != VXGE_HW_OK)
5064 goto exit;
5065
5066 if (vpath->ringh != NULL)
5067 __vxge_hw_vpath_prc_configure(hldev, vp_id);
5068
5069 memset(vpath->hw_stats, 0,
5070 sizeof(struct vxge_hw_vpath_stats_hw_info));
5071
5072 memset(vpath->hw_stats_sav, 0,
5073 sizeof(struct vxge_hw_vpath_stats_hw_info));
5074
5075 writeq(vpath->stats_block->dma_addr,
5076 &vpath->vp_reg->stats_cfg);
5077
5078 status = vxge_hw_vpath_stats_enable(vp);
5079
5080 exit:
5081 return status;
5082 }
5083
5084 /*
5085 * vxge_hw_vpath_enable - Enable vpath.
5086 * This routine clears the vpath reset thereby enabling a vpath
5087 * to start forwarding frames and generating interrupts.
5088 */
5089 void
vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle * vp)5090 vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp)
5091 {
5092 struct __vxge_hw_device *hldev;
5093 u64 val64;
5094
5095 hldev = vp->vpath->hldev;
5096
5097 val64 = VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(
5098 1 << (16 - vp->vpath->vp_id));
5099
5100 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
5101 &hldev->common_reg->cmn_rsthdlr_cfg1);
5102 }
5103
