1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /**************************************************************************
3 *
4 * Copyright 2009-2015 VMware, Inc., Palo Alto, CA., USA
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/sched/signal.h>
30
31 #include "vmwgfx_drv.h"
32
33 #define VMW_FENCE_WRAP (1 << 24)
34
35 /**
36 * vmw_thread_fn - Deferred (process context) irq handler
37 *
38 * @irq: irq number
39 * @arg: Closure argument. Pointer to a struct drm_device cast to void *
40 *
41 * This function implements the deferred part of irq processing.
42 * The function is guaranteed to run at least once after the
43 * vmw_irq_handler has returned with IRQ_WAKE_THREAD.
44 *
45 */
vmw_thread_fn(int irq,void * arg)46 static irqreturn_t vmw_thread_fn(int irq, void *arg)
47 {
48 struct drm_device *dev = (struct drm_device *)arg;
49 struct vmw_private *dev_priv = vmw_priv(dev);
50 irqreturn_t ret = IRQ_NONE;
51
52 if (test_and_clear_bit(VMW_IRQTHREAD_FENCE,
53 dev_priv->irqthread_pending)) {
54 vmw_fences_update(dev_priv->fman);
55 wake_up_all(&dev_priv->fence_queue);
56 ret = IRQ_HANDLED;
57 }
58
59 if (test_and_clear_bit(VMW_IRQTHREAD_CMDBUF,
60 dev_priv->irqthread_pending)) {
61 vmw_cmdbuf_irqthread(dev_priv->cman);
62 ret = IRQ_HANDLED;
63 }
64
65 return ret;
66 }
67
68 /**
69 * vmw_irq_handler: irq handler
70 *
71 * @irq: irq number
72 * @arg: Closure argument. Pointer to a struct drm_device cast to void *
73 *
74 * This function implements the quick part of irq processing.
75 * The function performs fast actions like clearing the device interrupt
76 * flags and also reasonably quick actions like waking processes waiting for
77 * FIFO space. Other IRQ actions are deferred to the IRQ thread.
78 */
vmw_irq_handler(int irq,void * arg)79 static irqreturn_t vmw_irq_handler(int irq, void *arg)
80 {
81 struct drm_device *dev = (struct drm_device *)arg;
82 struct vmw_private *dev_priv = vmw_priv(dev);
83 uint32_t status, masked_status;
84 irqreturn_t ret = IRQ_HANDLED;
85
86 status = vmw_irq_status_read(dev_priv);
87 masked_status = status & READ_ONCE(dev_priv->irq_mask);
88
89 if (likely(status))
90 vmw_irq_status_write(dev_priv, status);
91
92 if (!status)
93 return IRQ_NONE;
94
95 if (masked_status & SVGA_IRQFLAG_FIFO_PROGRESS)
96 wake_up_all(&dev_priv->fifo_queue);
97
98 if ((masked_status & (SVGA_IRQFLAG_ANY_FENCE |
99 SVGA_IRQFLAG_FENCE_GOAL)) &&
100 !test_and_set_bit(VMW_IRQTHREAD_FENCE, dev_priv->irqthread_pending))
101 ret = IRQ_WAKE_THREAD;
102
103 if ((masked_status & (SVGA_IRQFLAG_COMMAND_BUFFER |
104 SVGA_IRQFLAG_ERROR)) &&
105 !test_and_set_bit(VMW_IRQTHREAD_CMDBUF,
106 dev_priv->irqthread_pending))
107 ret = IRQ_WAKE_THREAD;
108
109 return ret;
110 }
111
vmw_fifo_idle(struct vmw_private * dev_priv,uint32_t seqno)112 static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno)
113 {
114
115 return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0);
116 }
117
vmw_update_seqno(struct vmw_private * dev_priv)118 void vmw_update_seqno(struct vmw_private *dev_priv)
119 {
120 uint32_t seqno = vmw_fence_read(dev_priv);
121
122 if (dev_priv->last_read_seqno != seqno) {
123 dev_priv->last_read_seqno = seqno;
124 vmw_fences_update(dev_priv->fman);
125 }
126 }
127
vmw_seqno_passed(struct vmw_private * dev_priv,uint32_t seqno)128 bool vmw_seqno_passed(struct vmw_private *dev_priv,
129 uint32_t seqno)
130 {
131 bool ret;
132
133 if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
134 return true;
135
136 vmw_update_seqno(dev_priv);
137 if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
138 return true;
139
140 if (!(vmw_fifo_caps(dev_priv) & SVGA_FIFO_CAP_FENCE) &&
141 vmw_fifo_idle(dev_priv, seqno))
142 return true;
143
144 /**
145 * Then check if the seqno is higher than what we've actually
146 * emitted. Then the fence is stale and signaled.
147 */
148
149 ret = ((atomic_read(&dev_priv->marker_seq) - seqno)
150 > VMW_FENCE_WRAP);
151
152 return ret;
153 }
154
vmw_fallback_wait(struct vmw_private * dev_priv,bool lazy,bool fifo_idle,uint32_t seqno,bool interruptible,unsigned long timeout)155 int vmw_fallback_wait(struct vmw_private *dev_priv,
156 bool lazy,
157 bool fifo_idle,
158 uint32_t seqno,
159 bool interruptible,
160 unsigned long timeout)
161 {
162 struct vmw_fifo_state *fifo_state = dev_priv->fifo;
163
164 uint32_t count = 0;
165 uint32_t signal_seq;
166 int ret;
167 unsigned long end_jiffies = jiffies + timeout;
168 bool (*wait_condition)(struct vmw_private *, uint32_t);
169 DEFINE_WAIT(__wait);
170
171 wait_condition = (fifo_idle) ? &vmw_fifo_idle :
172 &vmw_seqno_passed;
173
174 /**
175 * Block command submission while waiting for idle.
176 */
177
178 if (fifo_idle) {
179 down_read(&fifo_state->rwsem);
180 if (dev_priv->cman) {
181 ret = vmw_cmdbuf_idle(dev_priv->cman, interruptible,
182 10*HZ);
183 if (ret)
184 goto out_err;
185 }
186 }
187
188 signal_seq = atomic_read(&dev_priv->marker_seq);
189 ret = 0;
190
191 for (;;) {
192 prepare_to_wait(&dev_priv->fence_queue, &__wait,
193 (interruptible) ?
194 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
195 if (wait_condition(dev_priv, seqno))
196 break;
197 if (time_after_eq(jiffies, end_jiffies)) {
198 DRM_ERROR("SVGA device lockup.\n");
199 break;
200 }
201 if (lazy)
202 schedule_timeout(1);
203 else if ((++count & 0x0F) == 0) {
204 /**
205 * FIXME: Use schedule_hr_timeout here for
206 * newer kernels and lower CPU utilization.
207 */
208
209 __set_current_state(TASK_RUNNING);
210 schedule();
211 __set_current_state((interruptible) ?
212 TASK_INTERRUPTIBLE :
213 TASK_UNINTERRUPTIBLE);
214 }
215 if (interruptible && signal_pending(current)) {
216 ret = -ERESTARTSYS;
217 break;
218 }
219 }
220 finish_wait(&dev_priv->fence_queue, &__wait);
221 if (ret == 0 && fifo_idle)
222 vmw_fence_write(dev_priv, signal_seq);
223
224 wake_up_all(&dev_priv->fence_queue);
225 out_err:
226 if (fifo_idle)
227 up_read(&fifo_state->rwsem);
228
229 return ret;
230 }
231
vmw_generic_waiter_add(struct vmw_private * dev_priv,u32 flag,int * waiter_count)232 void vmw_generic_waiter_add(struct vmw_private *dev_priv,
233 u32 flag, int *waiter_count)
234 {
235 spin_lock_bh(&dev_priv->waiter_lock);
236 if ((*waiter_count)++ == 0) {
237 vmw_irq_status_write(dev_priv, flag);
238 dev_priv->irq_mask |= flag;
239 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
240 }
241 spin_unlock_bh(&dev_priv->waiter_lock);
242 }
243
vmw_generic_waiter_remove(struct vmw_private * dev_priv,u32 flag,int * waiter_count)244 void vmw_generic_waiter_remove(struct vmw_private *dev_priv,
245 u32 flag, int *waiter_count)
246 {
247 spin_lock_bh(&dev_priv->waiter_lock);
248 if (--(*waiter_count) == 0) {
249 dev_priv->irq_mask &= ~flag;
250 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
251 }
252 spin_unlock_bh(&dev_priv->waiter_lock);
253 }
254
vmw_seqno_waiter_add(struct vmw_private * dev_priv)255 void vmw_seqno_waiter_add(struct vmw_private *dev_priv)
256 {
257 vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_ANY_FENCE,
258 &dev_priv->fence_queue_waiters);
259 }
260
vmw_seqno_waiter_remove(struct vmw_private * dev_priv)261 void vmw_seqno_waiter_remove(struct vmw_private *dev_priv)
262 {
263 vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_ANY_FENCE,
264 &dev_priv->fence_queue_waiters);
265 }
266
vmw_goal_waiter_add(struct vmw_private * dev_priv)267 void vmw_goal_waiter_add(struct vmw_private *dev_priv)
268 {
269 vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FENCE_GOAL,
270 &dev_priv->goal_queue_waiters);
271 }
272
vmw_goal_waiter_remove(struct vmw_private * dev_priv)273 void vmw_goal_waiter_remove(struct vmw_private *dev_priv)
274 {
275 vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FENCE_GOAL,
276 &dev_priv->goal_queue_waiters);
277 }
278
vmw_irq_preinstall(struct drm_device * dev)279 static void vmw_irq_preinstall(struct drm_device *dev)
280 {
281 struct vmw_private *dev_priv = vmw_priv(dev);
282 uint32_t status;
283
284 status = vmw_irq_status_read(dev_priv);
285 vmw_irq_status_write(dev_priv, status);
286 }
287
vmw_irq_uninstall(struct drm_device * dev)288 void vmw_irq_uninstall(struct drm_device *dev)
289 {
290 struct vmw_private *dev_priv = vmw_priv(dev);
291 struct pci_dev *pdev = to_pci_dev(dev->dev);
292 uint32_t status;
293
294 if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
295 return;
296
297 vmw_write(dev_priv, SVGA_REG_IRQMASK, 0);
298
299 status = vmw_irq_status_read(dev_priv);
300 vmw_irq_status_write(dev_priv, status);
301
302 free_irq(pdev->irq, dev);
303 }
304
305 /**
306 * vmw_irq_install - Install the irq handlers
307 *
308 * @dev: Pointer to the drm device.
309 * @irq: The irq number.
310 * Return: Zero if successful. Negative number otherwise.
311 */
vmw_irq_install(struct drm_device * dev,int irq)312 int vmw_irq_install(struct drm_device *dev, int irq)
313 {
314 vmw_irq_preinstall(dev);
315
316 return request_threaded_irq(irq, vmw_irq_handler, vmw_thread_fn,
317 IRQF_SHARED, VMWGFX_DRIVER_NAME, dev);
318 }
319
