1 /*
2 * Copyright (C) 2015, 2016 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/irqchip/arm-gic.h>
18 #include <linux/kvm.h>
19 #include <linux/kvm_host.h>
20 #include <kvm/arm_vgic.h>
21 #include <asm/kvm_mmu.h>
22
23 #include "vgic.h"
24
vgic_v2_write_lr(int lr,u32 val)25 static inline void vgic_v2_write_lr(int lr, u32 val)
26 {
27 void __iomem *base = kvm_vgic_global_state.vctrl_base;
28
29 writel_relaxed(val, base + GICH_LR0 + (lr * 4));
30 }
31
vgic_v2_init_lrs(void)32 void vgic_v2_init_lrs(void)
33 {
34 int i;
35
36 for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
37 vgic_v2_write_lr(i, 0);
38 }
39
vgic_v2_set_underflow(struct kvm_vcpu * vcpu)40 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
41 {
42 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
43
44 cpuif->vgic_hcr |= GICH_HCR_UIE;
45 }
46
lr_signals_eoi_mi(u32 lr_val)47 static bool lr_signals_eoi_mi(u32 lr_val)
48 {
49 return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) &&
50 !(lr_val & GICH_LR_HW);
51 }
52
53 /*
54 * transfer the content of the LRs back into the corresponding ap_list:
55 * - active bit is transferred as is
56 * - pending bit is
57 * - transferred as is in case of edge sensitive IRQs
58 * - set to the line-level (resample time) for level sensitive IRQs
59 */
vgic_v2_fold_lr_state(struct kvm_vcpu * vcpu)60 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
61 {
62 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
63 struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
64 int lr;
65
66 DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
67
68 cpuif->vgic_hcr &= ~GICH_HCR_UIE;
69
70 for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
71 u32 val = cpuif->vgic_lr[lr];
72 u32 cpuid, intid = val & GICH_LR_VIRTUALID;
73 struct vgic_irq *irq;
74
75 /* Extract the source vCPU id from the LR */
76 cpuid = val & GICH_LR_PHYSID_CPUID;
77 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
78 cpuid &= 7;
79
80 /* Notify fds when the guest EOI'ed a level-triggered SPI */
81 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
82 kvm_notify_acked_irq(vcpu->kvm, 0,
83 intid - VGIC_NR_PRIVATE_IRQS);
84
85 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
86
87 spin_lock(&irq->irq_lock);
88
89 /* Always preserve the active bit */
90 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
91
92 if (irq->active && vgic_irq_is_sgi(intid))
93 irq->active_source = cpuid;
94
95 /* Edge is the only case where we preserve the pending bit */
96 if (irq->config == VGIC_CONFIG_EDGE &&
97 (val & GICH_LR_PENDING_BIT)) {
98 irq->pending_latch = true;
99
100 if (vgic_irq_is_sgi(intid))
101 irq->source |= (1 << cpuid);
102 }
103
104 /*
105 * Clear soft pending state when level irqs have been acked.
106 */
107 if (irq->config == VGIC_CONFIG_LEVEL && !(val & GICH_LR_STATE))
108 irq->pending_latch = false;
109
110 /*
111 * Level-triggered mapped IRQs are special because we only
112 * observe rising edges as input to the VGIC.
113 *
114 * If the guest never acked the interrupt we have to sample
115 * the physical line and set the line level, because the
116 * device state could have changed or we simply need to
117 * process the still pending interrupt later.
118 *
119 * If this causes us to lower the level, we have to also clear
120 * the physical active state, since we will otherwise never be
121 * told when the interrupt becomes asserted again.
122 */
123 if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT)) {
124 irq->line_level = vgic_get_phys_line_level(irq);
125
126 if (!irq->line_level)
127 vgic_irq_set_phys_active(irq, false);
128 }
129
130 spin_unlock(&irq->irq_lock);
131 vgic_put_irq(vcpu->kvm, irq);
132 }
133
134 vgic_cpu->used_lrs = 0;
135 }
136
137 /*
138 * Populates the particular LR with the state of a given IRQ:
139 * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
140 * - for a level sensitive IRQ the pending state value is unchanged;
141 * it is dictated directly by the input level
142 *
143 * If @irq describes an SGI with multiple sources, we choose the
144 * lowest-numbered source VCPU and clear that bit in the source bitmap.
145 *
146 * The irq_lock must be held by the caller.
147 */
vgic_v2_populate_lr(struct kvm_vcpu * vcpu,struct vgic_irq * irq,int lr)148 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
149 {
150 u32 val = irq->intid;
151 bool allow_pending = true;
152
153 if (irq->active) {
154 val |= GICH_LR_ACTIVE_BIT;
155 if (vgic_irq_is_sgi(irq->intid))
156 val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT;
157 if (vgic_irq_is_multi_sgi(irq)) {
158 allow_pending = false;
159 val |= GICH_LR_EOI;
160 }
161 }
162
163 if (irq->group)
164 val |= GICH_LR_GROUP1;
165
166 if (irq->hw) {
167 val |= GICH_LR_HW;
168 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
169 /*
170 * Never set pending+active on a HW interrupt, as the
171 * pending state is kept at the physical distributor
172 * level.
173 */
174 if (irq->active)
175 allow_pending = false;
176 } else {
177 if (irq->config == VGIC_CONFIG_LEVEL) {
178 val |= GICH_LR_EOI;
179
180 /*
181 * Software resampling doesn't work very well
182 * if we allow P+A, so let's not do that.
183 */
184 if (irq->active)
185 allow_pending = false;
186 }
187 }
188
189 if (allow_pending && irq_is_pending(irq)) {
190 val |= GICH_LR_PENDING_BIT;
191
192 if (irq->config == VGIC_CONFIG_EDGE)
193 irq->pending_latch = false;
194
195 if (vgic_irq_is_sgi(irq->intid)) {
196 u32 src = ffs(irq->source);
197
198 BUG_ON(!src);
199 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
200 irq->source &= ~(1 << (src - 1));
201 if (irq->source) {
202 irq->pending_latch = true;
203 val |= GICH_LR_EOI;
204 }
205 }
206 }
207
208 /*
209 * Level-triggered mapped IRQs are special because we only observe
210 * rising edges as input to the VGIC. We therefore lower the line
211 * level here, so that we can take new virtual IRQs. See
212 * vgic_v2_fold_lr_state for more info.
213 */
214 if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT))
215 irq->line_level = false;
216
217 /* The GICv2 LR only holds five bits of priority. */
218 val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
219
220 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
221 }
222
vgic_v2_clear_lr(struct kvm_vcpu * vcpu,int lr)223 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
224 {
225 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
226 }
227
vgic_v2_set_vmcr(struct kvm_vcpu * vcpu,struct vgic_vmcr * vmcrp)228 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
229 {
230 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
231 u32 vmcr;
232
233 vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
234 GICH_VMCR_ENABLE_GRP0_MASK;
235 vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
236 GICH_VMCR_ENABLE_GRP1_MASK;
237 vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
238 GICH_VMCR_ACK_CTL_MASK;
239 vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
240 GICH_VMCR_FIQ_EN_MASK;
241 vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
242 GICH_VMCR_CBPR_MASK;
243 vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
244 GICH_VMCR_EOI_MODE_MASK;
245 vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
246 GICH_VMCR_ALIAS_BINPOINT_MASK;
247 vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
248 GICH_VMCR_BINPOINT_MASK;
249 vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
250 GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
251
252 cpu_if->vgic_vmcr = vmcr;
253 }
254
vgic_v2_get_vmcr(struct kvm_vcpu * vcpu,struct vgic_vmcr * vmcrp)255 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
256 {
257 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
258 u32 vmcr;
259
260 vmcr = cpu_if->vgic_vmcr;
261
262 vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
263 GICH_VMCR_ENABLE_GRP0_SHIFT;
264 vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >>
265 GICH_VMCR_ENABLE_GRP1_SHIFT;
266 vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >>
267 GICH_VMCR_ACK_CTL_SHIFT;
268 vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >>
269 GICH_VMCR_FIQ_EN_SHIFT;
270 vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
271 GICH_VMCR_CBPR_SHIFT;
272 vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >>
273 GICH_VMCR_EOI_MODE_SHIFT;
274
275 vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
276 GICH_VMCR_ALIAS_BINPOINT_SHIFT;
277 vmcrp->bpr = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
278 GICH_VMCR_BINPOINT_SHIFT;
279 vmcrp->pmr = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
280 GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
281 }
282
vgic_v2_enable(struct kvm_vcpu * vcpu)283 void vgic_v2_enable(struct kvm_vcpu *vcpu)
284 {
285 /*
286 * By forcing VMCR to zero, the GIC will restore the binary
287 * points to their reset values. Anything else resets to zero
288 * anyway.
289 */
290 vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
291
292 /* Get the show on the road... */
293 vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
294 }
295
296 /* check for overlapping regions and for regions crossing the end of memory */
vgic_v2_check_base(gpa_t dist_base,gpa_t cpu_base)297 static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
298 {
299 if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
300 return false;
301 if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
302 return false;
303
304 if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
305 return true;
306 if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
307 return true;
308
309 return false;
310 }
311
vgic_v2_map_resources(struct kvm * kvm)312 int vgic_v2_map_resources(struct kvm *kvm)
313 {
314 struct vgic_dist *dist = &kvm->arch.vgic;
315 int ret = 0;
316
317 if (vgic_ready(kvm))
318 goto out;
319
320 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
321 IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
322 kvm_err("Need to set vgic cpu and dist addresses first\n");
323 ret = -ENXIO;
324 goto out;
325 }
326
327 if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
328 kvm_err("VGIC CPU and dist frames overlap\n");
329 ret = -EINVAL;
330 goto out;
331 }
332
333 /*
334 * Initialize the vgic if this hasn't already been done on demand by
335 * accessing the vgic state from userspace.
336 */
337 ret = vgic_init(kvm);
338 if (ret) {
339 kvm_err("Unable to initialize VGIC dynamic data structures\n");
340 goto out;
341 }
342
343 ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
344 if (ret) {
345 kvm_err("Unable to register VGIC MMIO regions\n");
346 goto out;
347 }
348
349 if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
350 ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
351 kvm_vgic_global_state.vcpu_base,
352 KVM_VGIC_V2_CPU_SIZE, true);
353 if (ret) {
354 kvm_err("Unable to remap VGIC CPU to VCPU\n");
355 goto out;
356 }
357 }
358
359 dist->ready = true;
360
361 out:
362 return ret;
363 }
364
365 DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
366
367 /**
368 * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
369 * @node: pointer to the DT node
370 *
371 * Returns 0 if a GICv2 has been found, returns an error code otherwise
372 */
vgic_v2_probe(const struct gic_kvm_info * info)373 int vgic_v2_probe(const struct gic_kvm_info *info)
374 {
375 int ret;
376 u32 vtr;
377
378 if (!info->vctrl.start) {
379 kvm_err("GICH not present in the firmware table\n");
380 return -ENXIO;
381 }
382
383 if (!PAGE_ALIGNED(info->vcpu.start) ||
384 !PAGE_ALIGNED(resource_size(&info->vcpu))) {
385 kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
386
387 ret = create_hyp_io_mappings(info->vcpu.start,
388 resource_size(&info->vcpu),
389 &kvm_vgic_global_state.vcpu_base_va,
390 &kvm_vgic_global_state.vcpu_hyp_va);
391 if (ret) {
392 kvm_err("Cannot map GICV into hyp\n");
393 goto out;
394 }
395
396 static_branch_enable(&vgic_v2_cpuif_trap);
397 }
398
399 ret = create_hyp_io_mappings(info->vctrl.start,
400 resource_size(&info->vctrl),
401 &kvm_vgic_global_state.vctrl_base,
402 &kvm_vgic_global_state.vctrl_hyp);
403 if (ret) {
404 kvm_err("Cannot map VCTRL into hyp\n");
405 goto out;
406 }
407
408 vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
409 kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
410
411 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
412 if (ret) {
413 kvm_err("Cannot register GICv2 KVM device\n");
414 goto out;
415 }
416
417 kvm_vgic_global_state.can_emulate_gicv2 = true;
418 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
419 kvm_vgic_global_state.type = VGIC_V2;
420 kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
421
422 kvm_debug("vgic-v2@%llx\n", info->vctrl.start);
423
424 return 0;
425 out:
426 if (kvm_vgic_global_state.vctrl_base)
427 iounmap(kvm_vgic_global_state.vctrl_base);
428 if (kvm_vgic_global_state.vcpu_base_va)
429 iounmap(kvm_vgic_global_state.vcpu_base_va);
430
431 return ret;
432 }
433
save_lrs(struct kvm_vcpu * vcpu,void __iomem * base)434 static void save_lrs(struct kvm_vcpu *vcpu, void __iomem *base)
435 {
436 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
437 u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
438 u64 elrsr;
439 int i;
440
441 elrsr = readl_relaxed(base + GICH_ELRSR0);
442 if (unlikely(used_lrs > 32))
443 elrsr |= ((u64)readl_relaxed(base + GICH_ELRSR1)) << 32;
444
445 for (i = 0; i < used_lrs; i++) {
446 if (elrsr & (1UL << i))
447 cpu_if->vgic_lr[i] &= ~GICH_LR_STATE;
448 else
449 cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));
450
451 writel_relaxed(0, base + GICH_LR0 + (i * 4));
452 }
453 }
454
vgic_v2_save_state(struct kvm_vcpu * vcpu)455 void vgic_v2_save_state(struct kvm_vcpu *vcpu)
456 {
457 void __iomem *base = kvm_vgic_global_state.vctrl_base;
458 u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
459
460 if (!base)
461 return;
462
463 if (used_lrs) {
464 save_lrs(vcpu, base);
465 writel_relaxed(0, base + GICH_HCR);
466 }
467 }
468
vgic_v2_restore_state(struct kvm_vcpu * vcpu)469 void vgic_v2_restore_state(struct kvm_vcpu *vcpu)
470 {
471 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
472 void __iomem *base = kvm_vgic_global_state.vctrl_base;
473 u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
474 int i;
475
476 if (!base)
477 return;
478
479 if (used_lrs) {
480 writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR);
481 for (i = 0; i < used_lrs; i++) {
482 writel_relaxed(cpu_if->vgic_lr[i],
483 base + GICH_LR0 + (i * 4));
484 }
485 }
486 }
487
vgic_v2_load(struct kvm_vcpu * vcpu)488 void vgic_v2_load(struct kvm_vcpu *vcpu)
489 {
490 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
491
492 writel_relaxed(cpu_if->vgic_vmcr,
493 kvm_vgic_global_state.vctrl_base + GICH_VMCR);
494 writel_relaxed(cpu_if->vgic_apr,
495 kvm_vgic_global_state.vctrl_base + GICH_APR);
496 }
497
vgic_v2_put(struct kvm_vcpu * vcpu)498 void vgic_v2_put(struct kvm_vcpu *vcpu)
499 {
500 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
501
502 cpu_if->vgic_vmcr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VMCR);
503 cpu_if->vgic_apr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_APR);
504 }
505
