1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include <drm/amdgpu_drm.h>
29
30 #include "amdgpu.h"
31 #include "amdgpu_atombios.h"
32 #include "amdgpu_ih.h"
33 #include "amdgpu_uvd.h"
34 #include "amdgpu_vce.h"
35 #include "amdgpu_ucode.h"
36 #include "amdgpu_psp.h"
37 #include "atom.h"
38 #include "amd_pcie.h"
39
40 #include "uvd/uvd_7_0_offset.h"
41 #include "gc/gc_9_0_offset.h"
42 #include "gc/gc_9_0_sh_mask.h"
43 #include "sdma0/sdma0_4_0_offset.h"
44 #include "sdma1/sdma1_4_0_offset.h"
45 #include "nbio/nbio_7_0_default.h"
46 #include "nbio/nbio_7_0_offset.h"
47 #include "nbio/nbio_7_0_sh_mask.h"
48 #include "nbio/nbio_7_0_smn.h"
49 #include "mp/mp_9_0_offset.h"
50
51 #include "soc15.h"
52 #include "soc15_common.h"
53 #include "gfx_v9_0.h"
54 #include "gmc_v9_0.h"
55 #include "gfxhub_v1_0.h"
56 #include "mmhub_v1_0.h"
57 #include "df_v1_7.h"
58 #include "df_v3_6.h"
59 #include "nbio_v6_1.h"
60 #include "nbio_v7_0.h"
61 #include "nbio_v7_4.h"
62 #include "hdp_v4_0.h"
63 #include "vega10_ih.h"
64 #include "vega20_ih.h"
65 #include "navi10_ih.h"
66 #include "sdma_v4_0.h"
67 #include "uvd_v7_0.h"
68 #include "vce_v4_0.h"
69 #include "vcn_v1_0.h"
70 #include "vcn_v2_0.h"
71 #include "jpeg_v2_0.h"
72 #include "vcn_v2_5.h"
73 #include "jpeg_v2_5.h"
74 #include "smuio_v9_0.h"
75 #include "smuio_v11_0.h"
76 #include "smuio_v13_0.h"
77 #include "amdgpu_vkms.h"
78 #include "mxgpu_ai.h"
79 #include "amdgpu_ras.h"
80 #include "amdgpu_xgmi.h"
81 #include <uapi/linux/kfd_ioctl.h>
82
83 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
87
88 static const struct amd_ip_funcs soc15_common_ip_funcs;
89
90 /* Vega, Raven, Arcturus */
91 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
92 {
93 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
94 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
95 };
96
97 static const struct amdgpu_video_codecs vega_video_codecs_encode =
98 {
99 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
100 .codec_array = vega_video_codecs_encode_array,
101 };
102
103 /* Vega */
104 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
105 {
106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
111 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
112 };
113
114 static const struct amdgpu_video_codecs vega_video_codecs_decode =
115 {
116 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
117 .codec_array = vega_video_codecs_decode_array,
118 };
119
120 /* Raven */
121 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
122 {
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)},
130 };
131
132 static const struct amdgpu_video_codecs rv_video_codecs_decode =
133 {
134 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
135 .codec_array = rv_video_codecs_decode_array,
136 };
137
138 /* Renoir, Arcturus */
139 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
140 {
141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
148 };
149
150 static const struct amdgpu_video_codecs rn_video_codecs_decode =
151 {
152 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
153 .codec_array = rn_video_codecs_decode_array,
154 };
155
156 static const struct amdgpu_video_codec_info vcn_4_0_3_video_codecs_decode_array[] = {
157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
162 };
163
164 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_decode = {
165 .codec_count = ARRAY_SIZE(vcn_4_0_3_video_codecs_decode_array),
166 .codec_array = vcn_4_0_3_video_codecs_decode_array,
167 };
168
169 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_encode = {
170 .codec_count = 0,
171 .codec_array = NULL,
172 };
173
soc15_query_video_codecs(struct amdgpu_device * adev,bool encode,const struct amdgpu_video_codecs ** codecs)174 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
175 const struct amdgpu_video_codecs **codecs)
176 {
177 if (adev->ip_versions[VCE_HWIP][0]) {
178 switch (adev->ip_versions[VCE_HWIP][0]) {
179 case IP_VERSION(4, 0, 0):
180 case IP_VERSION(4, 1, 0):
181 if (encode)
182 *codecs = &vega_video_codecs_encode;
183 else
184 *codecs = &vega_video_codecs_decode;
185 return 0;
186 default:
187 return -EINVAL;
188 }
189 } else {
190 switch (adev->ip_versions[UVD_HWIP][0]) {
191 case IP_VERSION(1, 0, 0):
192 case IP_VERSION(1, 0, 1):
193 if (encode)
194 *codecs = &vega_video_codecs_encode;
195 else
196 *codecs = &rv_video_codecs_decode;
197 return 0;
198 case IP_VERSION(2, 5, 0):
199 case IP_VERSION(2, 6, 0):
200 case IP_VERSION(2, 2, 0):
201 if (encode)
202 *codecs = &vega_video_codecs_encode;
203 else
204 *codecs = &rn_video_codecs_decode;
205 return 0;
206 case IP_VERSION(4, 0, 3):
207 if (encode)
208 *codecs = &vcn_4_0_3_video_codecs_encode;
209 else
210 *codecs = &vcn_4_0_3_video_codecs_decode;
211 return 0;
212 default:
213 return -EINVAL;
214 }
215 }
216 }
217
soc15_uvd_ctx_rreg(struct amdgpu_device * adev,u32 reg)218 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
219 {
220 unsigned long flags, address, data;
221 u32 r;
222
223 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
224 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
225
226 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
227 WREG32(address, ((reg) & 0x1ff));
228 r = RREG32(data);
229 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
230 return r;
231 }
232
soc15_uvd_ctx_wreg(struct amdgpu_device * adev,u32 reg,u32 v)233 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
234 {
235 unsigned long flags, address, data;
236
237 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
238 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
239
240 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
241 WREG32(address, ((reg) & 0x1ff));
242 WREG32(data, (v));
243 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
244 }
245
soc15_didt_rreg(struct amdgpu_device * adev,u32 reg)246 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
247 {
248 unsigned long flags, address, data;
249 u32 r;
250
251 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
252 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
253
254 spin_lock_irqsave(&adev->didt_idx_lock, flags);
255 WREG32(address, (reg));
256 r = RREG32(data);
257 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
258 return r;
259 }
260
soc15_didt_wreg(struct amdgpu_device * adev,u32 reg,u32 v)261 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
262 {
263 unsigned long flags, address, data;
264
265 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
266 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
267
268 spin_lock_irqsave(&adev->didt_idx_lock, flags);
269 WREG32(address, (reg));
270 WREG32(data, (v));
271 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
272 }
273
soc15_gc_cac_rreg(struct amdgpu_device * adev,u32 reg)274 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
275 {
276 unsigned long flags;
277 u32 r;
278
279 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
280 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
281 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
282 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
283 return r;
284 }
285
soc15_gc_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v)286 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
287 {
288 unsigned long flags;
289
290 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
291 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
292 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
293 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
294 }
295
soc15_se_cac_rreg(struct amdgpu_device * adev,u32 reg)296 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
297 {
298 unsigned long flags;
299 u32 r;
300
301 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
302 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
303 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
304 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
305 return r;
306 }
307
soc15_se_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v)308 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
309 {
310 unsigned long flags;
311
312 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
313 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
314 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
315 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
316 }
317
soc15_get_config_memsize(struct amdgpu_device * adev)318 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
319 {
320 return adev->nbio.funcs->get_memsize(adev);
321 }
322
soc15_get_xclk(struct amdgpu_device * adev)323 static u32 soc15_get_xclk(struct amdgpu_device *adev)
324 {
325 u32 reference_clock = adev->clock.spll.reference_freq;
326
327 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) ||
328 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1))
329 return 10000;
330 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) ||
331 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1))
332 return reference_clock / 4;
333
334 return reference_clock;
335 }
336
337
soc15_grbm_select(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue,u32 vmid,int xcc_id)338 void soc15_grbm_select(struct amdgpu_device *adev,
339 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id)
340 {
341 u32 grbm_gfx_cntl = 0;
342 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
343 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
344 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
345 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
346
347 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
348 }
349
soc15_read_disabled_bios(struct amdgpu_device * adev)350 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
351 {
352 /* todo */
353 return false;
354 }
355
356 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
357 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
358 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
359 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
360 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
361 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
362 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
363 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
364 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
365 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
366 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
367 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
368 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
369 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
370 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
371 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
372 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
373 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
374 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
375 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
376 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
377 };
378
soc15_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset)379 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
380 u32 sh_num, u32 reg_offset)
381 {
382 uint32_t val;
383
384 mutex_lock(&adev->grbm_idx_mutex);
385 if (se_num != 0xffffffff || sh_num != 0xffffffff)
386 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
387
388 val = RREG32(reg_offset);
389
390 if (se_num != 0xffffffff || sh_num != 0xffffffff)
391 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
392 mutex_unlock(&adev->grbm_idx_mutex);
393 return val;
394 }
395
soc15_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset)396 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
397 bool indexed, u32 se_num,
398 u32 sh_num, u32 reg_offset)
399 {
400 if (indexed) {
401 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
402 } else {
403 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
404 return adev->gfx.config.gb_addr_config;
405 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
406 return adev->gfx.config.db_debug2;
407 return RREG32(reg_offset);
408 }
409 }
410
soc15_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value)411 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
412 u32 sh_num, u32 reg_offset, u32 *value)
413 {
414 uint32_t i;
415 struct soc15_allowed_register_entry *en;
416
417 *value = 0;
418 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
419 en = &soc15_allowed_read_registers[i];
420 if (!adev->reg_offset[en->hwip][en->inst])
421 continue;
422 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
423 + en->reg_offset))
424 continue;
425
426 *value = soc15_get_register_value(adev,
427 soc15_allowed_read_registers[i].grbm_indexed,
428 se_num, sh_num, reg_offset);
429 return 0;
430 }
431 return -EINVAL;
432 }
433
434
435 /**
436 * soc15_program_register_sequence - program an array of registers.
437 *
438 * @adev: amdgpu_device pointer
439 * @regs: pointer to the register array
440 * @array_size: size of the register array
441 *
442 * Programs an array or registers with and and or masks.
443 * This is a helper for setting golden registers.
444 */
445
soc15_program_register_sequence(struct amdgpu_device * adev,const struct soc15_reg_golden * regs,const u32 array_size)446 void soc15_program_register_sequence(struct amdgpu_device *adev,
447 const struct soc15_reg_golden *regs,
448 const u32 array_size)
449 {
450 const struct soc15_reg_golden *entry;
451 u32 tmp, reg;
452 int i;
453
454 for (i = 0; i < array_size; ++i) {
455 entry = ®s[i];
456 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
457
458 if (entry->and_mask == 0xffffffff) {
459 tmp = entry->or_mask;
460 } else {
461 tmp = (entry->hwip == GC_HWIP) ?
462 RREG32_SOC15_IP(GC, reg) : RREG32(reg);
463
464 tmp &= ~(entry->and_mask);
465 tmp |= (entry->or_mask & entry->and_mask);
466 }
467
468 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
469 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
470 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
471 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
472 WREG32_RLC(reg, tmp);
473 else
474 (entry->hwip == GC_HWIP) ?
475 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
476
477 }
478
479 }
480
soc15_asic_baco_reset(struct amdgpu_device * adev)481 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
482 {
483 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
484 int ret = 0;
485
486 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
487 if (ras && adev->ras_enabled)
488 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
489
490 ret = amdgpu_dpm_baco_reset(adev);
491 if (ret)
492 return ret;
493
494 /* re-enable doorbell interrupt after BACO exit */
495 if (ras && adev->ras_enabled)
496 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
497
498 return 0;
499 }
500
501 static enum amd_reset_method
soc15_asic_reset_method(struct amdgpu_device * adev)502 soc15_asic_reset_method(struct amdgpu_device *adev)
503 {
504 bool baco_reset = false;
505 bool connected_to_cpu = false;
506 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
507
508 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
509 connected_to_cpu = true;
510
511 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
512 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
513 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
514 amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
515 /* If connected to cpu, driver only support mode2 */
516 if (connected_to_cpu)
517 return AMD_RESET_METHOD_MODE2;
518 return amdgpu_reset_method;
519 }
520
521 if (amdgpu_reset_method != -1)
522 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
523 amdgpu_reset_method);
524
525 switch (adev->ip_versions[MP1_HWIP][0]) {
526 case IP_VERSION(10, 0, 0):
527 case IP_VERSION(10, 0, 1):
528 case IP_VERSION(12, 0, 0):
529 case IP_VERSION(12, 0, 1):
530 return AMD_RESET_METHOD_MODE2;
531 case IP_VERSION(9, 0, 0):
532 case IP_VERSION(11, 0, 2):
533 if (adev->asic_type == CHIP_VEGA20) {
534 if (adev->psp.sos.fw_version >= 0x80067)
535 baco_reset = amdgpu_dpm_is_baco_supported(adev);
536 /*
537 * 1. PMFW version > 0x284300: all cases use baco
538 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
539 */
540 if (ras && adev->ras_enabled &&
541 adev->pm.fw_version <= 0x283400)
542 baco_reset = false;
543 } else {
544 baco_reset = amdgpu_dpm_is_baco_supported(adev);
545 }
546 break;
547 case IP_VERSION(13, 0, 2):
548 /*
549 * 1.connected to cpu: driver issue mode2 reset
550 * 2.discret gpu: driver issue mode1 reset
551 */
552 if (connected_to_cpu)
553 return AMD_RESET_METHOD_MODE2;
554 break;
555 case IP_VERSION(13, 0, 6):
556 /* Use gpu_recovery param to target a reset method.
557 * Enable triggering of GPU reset only if specified
558 * by module parameter.
559 */
560 if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5)
561 return AMD_RESET_METHOD_MODE2;
562 else if (!(adev->flags & AMD_IS_APU))
563 return AMD_RESET_METHOD_MODE1;
564 else
565 return AMD_RESET_METHOD_MODE2;
566 default:
567 break;
568 }
569
570 if (baco_reset)
571 return AMD_RESET_METHOD_BACO;
572 else
573 return AMD_RESET_METHOD_MODE1;
574 }
575
soc15_asic_reset(struct amdgpu_device * adev)576 static int soc15_asic_reset(struct amdgpu_device *adev)
577 {
578 /* original raven doesn't have full asic reset */
579 if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
580 (adev->apu_flags & AMD_APU_IS_RAVEN2))
581 return 0;
582
583 switch (soc15_asic_reset_method(adev)) {
584 case AMD_RESET_METHOD_PCI:
585 dev_info(adev->dev, "PCI reset\n");
586 return amdgpu_device_pci_reset(adev);
587 case AMD_RESET_METHOD_BACO:
588 dev_info(adev->dev, "BACO reset\n");
589 return soc15_asic_baco_reset(adev);
590 case AMD_RESET_METHOD_MODE2:
591 dev_info(adev->dev, "MODE2 reset\n");
592 return amdgpu_dpm_mode2_reset(adev);
593 default:
594 dev_info(adev->dev, "MODE1 reset\n");
595 return amdgpu_device_mode1_reset(adev);
596 }
597 }
598
soc15_supports_baco(struct amdgpu_device * adev)599 static bool soc15_supports_baco(struct amdgpu_device *adev)
600 {
601 switch (adev->ip_versions[MP1_HWIP][0]) {
602 case IP_VERSION(9, 0, 0):
603 case IP_VERSION(11, 0, 2):
604 if (adev->asic_type == CHIP_VEGA20) {
605 if (adev->psp.sos.fw_version >= 0x80067)
606 return amdgpu_dpm_is_baco_supported(adev);
607 return false;
608 } else {
609 return amdgpu_dpm_is_baco_supported(adev);
610 }
611 break;
612 default:
613 return false;
614 }
615 }
616
617 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
618 u32 cntl_reg, u32 status_reg)
619 {
620 return 0;
621 }*/
622
soc15_set_uvd_clocks(struct amdgpu_device * adev,u32 vclk,u32 dclk)623 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
624 {
625 /*int r;
626
627 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
628 if (r)
629 return r;
630
631 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
632 */
633 return 0;
634 }
635
soc15_set_vce_clocks(struct amdgpu_device * adev,u32 evclk,u32 ecclk)636 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
637 {
638 /* todo */
639
640 return 0;
641 }
642
soc15_program_aspm(struct amdgpu_device * adev)643 static void soc15_program_aspm(struct amdgpu_device *adev)
644 {
645 if (!amdgpu_device_should_use_aspm(adev))
646 return;
647
648 if (!(adev->flags & AMD_IS_APU) &&
649 (adev->nbio.funcs->program_aspm))
650 adev->nbio.funcs->program_aspm(adev);
651 }
652
653 const struct amdgpu_ip_block_version vega10_common_ip_block =
654 {
655 .type = AMD_IP_BLOCK_TYPE_COMMON,
656 .major = 2,
657 .minor = 0,
658 .rev = 0,
659 .funcs = &soc15_common_ip_funcs,
660 };
661
soc15_reg_base_init(struct amdgpu_device * adev)662 static void soc15_reg_base_init(struct amdgpu_device *adev)
663 {
664 /* Set IP register base before any HW register access */
665 switch (adev->asic_type) {
666 case CHIP_VEGA10:
667 case CHIP_VEGA12:
668 case CHIP_RAVEN:
669 case CHIP_RENOIR:
670 vega10_reg_base_init(adev);
671 break;
672 case CHIP_VEGA20:
673 vega20_reg_base_init(adev);
674 break;
675 case CHIP_ARCTURUS:
676 arct_reg_base_init(adev);
677 break;
678 case CHIP_ALDEBARAN:
679 aldebaran_reg_base_init(adev);
680 break;
681 default:
682 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
683 break;
684 }
685 }
686
soc15_set_virt_ops(struct amdgpu_device * adev)687 void soc15_set_virt_ops(struct amdgpu_device *adev)
688 {
689 adev->virt.ops = &xgpu_ai_virt_ops;
690
691 /* init soc15 reg base early enough so we can
692 * request request full access for sriov before
693 * set_ip_blocks. */
694 soc15_reg_base_init(adev);
695 }
696
soc15_need_full_reset(struct amdgpu_device * adev)697 static bool soc15_need_full_reset(struct amdgpu_device *adev)
698 {
699 /* change this when we implement soft reset */
700 return true;
701 }
702
soc15_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1)703 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
704 uint64_t *count1)
705 {
706 uint32_t perfctr = 0;
707 uint64_t cnt0_of, cnt1_of;
708 int tmp;
709
710 /* This reports 0 on APUs, so return to avoid writing/reading registers
711 * that may or may not be different from their GPU counterparts
712 */
713 if (adev->flags & AMD_IS_APU)
714 return;
715
716 /* Set the 2 events that we wish to watch, defined above */
717 /* Reg 40 is # received msgs */
718 /* Reg 104 is # of posted requests sent */
719 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
720 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
721
722 /* Write to enable desired perf counters */
723 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
724 /* Zero out and enable the perf counters
725 * Write 0x5:
726 * Bit 0 = Start all counters(1)
727 * Bit 2 = Global counter reset enable(1)
728 */
729 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
730
731 msleep(1000);
732
733 /* Load the shadow and disable the perf counters
734 * Write 0x2:
735 * Bit 0 = Stop counters(0)
736 * Bit 1 = Load the shadow counters(1)
737 */
738 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
739
740 /* Read register values to get any >32bit overflow */
741 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
742 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
743 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
744
745 /* Get the values and add the overflow */
746 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
747 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
748 }
749
vega20_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1)750 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
751 uint64_t *count1)
752 {
753 uint32_t perfctr = 0;
754 uint64_t cnt0_of, cnt1_of;
755 int tmp;
756
757 /* This reports 0 on APUs, so return to avoid writing/reading registers
758 * that may or may not be different from their GPU counterparts
759 */
760 if (adev->flags & AMD_IS_APU)
761 return;
762
763 /* Set the 2 events that we wish to watch, defined above */
764 /* Reg 40 is # received msgs */
765 /* Reg 108 is # of posted requests sent on VG20 */
766 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
767 EVENT0_SEL, 40);
768 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
769 EVENT1_SEL, 108);
770
771 /* Write to enable desired perf counters */
772 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
773 /* Zero out and enable the perf counters
774 * Write 0x5:
775 * Bit 0 = Start all counters(1)
776 * Bit 2 = Global counter reset enable(1)
777 */
778 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
779
780 msleep(1000);
781
782 /* Load the shadow and disable the perf counters
783 * Write 0x2:
784 * Bit 0 = Stop counters(0)
785 * Bit 1 = Load the shadow counters(1)
786 */
787 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
788
789 /* Read register values to get any >32bit overflow */
790 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
791 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
792 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
793
794 /* Get the values and add the overflow */
795 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
796 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
797 }
798
soc15_need_reset_on_init(struct amdgpu_device * adev)799 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
800 {
801 u32 sol_reg;
802
803 /* CP hangs in IGT reloading test on RN, reset to WA */
804 if (adev->asic_type == CHIP_RENOIR)
805 return true;
806
807 /* Just return false for soc15 GPUs. Reset does not seem to
808 * be necessary.
809 */
810 if (!amdgpu_passthrough(adev))
811 return false;
812
813 if (adev->flags & AMD_IS_APU)
814 return false;
815
816 /* Check sOS sign of life register to confirm sys driver and sOS
817 * are already been loaded.
818 */
819 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
820 if (sol_reg)
821 return true;
822
823 return false;
824 }
825
soc15_get_pcie_replay_count(struct amdgpu_device * adev)826 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
827 {
828 uint64_t nak_r, nak_g;
829
830 /* Get the number of NAKs received and generated */
831 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
832 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
833
834 /* Add the total number of NAKs, i.e the number of replays */
835 return (nak_r + nak_g);
836 }
837
soc15_pre_asic_init(struct amdgpu_device * adev)838 static void soc15_pre_asic_init(struct amdgpu_device *adev)
839 {
840 gmc_v9_0_restore_registers(adev);
841 }
842
843 static const struct amdgpu_asic_funcs soc15_asic_funcs =
844 {
845 .read_disabled_bios = &soc15_read_disabled_bios,
846 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
847 .read_register = &soc15_read_register,
848 .reset = &soc15_asic_reset,
849 .reset_method = &soc15_asic_reset_method,
850 .get_xclk = &soc15_get_xclk,
851 .set_uvd_clocks = &soc15_set_uvd_clocks,
852 .set_vce_clocks = &soc15_set_vce_clocks,
853 .get_config_memsize = &soc15_get_config_memsize,
854 .need_full_reset = &soc15_need_full_reset,
855 .init_doorbell_index = &vega10_doorbell_index_init,
856 .get_pcie_usage = &soc15_get_pcie_usage,
857 .need_reset_on_init = &soc15_need_reset_on_init,
858 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
859 .supports_baco = &soc15_supports_baco,
860 .pre_asic_init = &soc15_pre_asic_init,
861 .query_video_codecs = &soc15_query_video_codecs,
862 };
863
864 static const struct amdgpu_asic_funcs vega20_asic_funcs =
865 {
866 .read_disabled_bios = &soc15_read_disabled_bios,
867 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
868 .read_register = &soc15_read_register,
869 .reset = &soc15_asic_reset,
870 .reset_method = &soc15_asic_reset_method,
871 .get_xclk = &soc15_get_xclk,
872 .set_uvd_clocks = &soc15_set_uvd_clocks,
873 .set_vce_clocks = &soc15_set_vce_clocks,
874 .get_config_memsize = &soc15_get_config_memsize,
875 .need_full_reset = &soc15_need_full_reset,
876 .init_doorbell_index = &vega20_doorbell_index_init,
877 .get_pcie_usage = &vega20_get_pcie_usage,
878 .need_reset_on_init = &soc15_need_reset_on_init,
879 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
880 .supports_baco = &soc15_supports_baco,
881 .pre_asic_init = &soc15_pre_asic_init,
882 .query_video_codecs = &soc15_query_video_codecs,
883 };
884
885 static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs =
886 {
887 .read_disabled_bios = &soc15_read_disabled_bios,
888 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
889 .read_register = &soc15_read_register,
890 .reset = &soc15_asic_reset,
891 .reset_method = &soc15_asic_reset_method,
892 .get_xclk = &soc15_get_xclk,
893 .set_uvd_clocks = &soc15_set_uvd_clocks,
894 .set_vce_clocks = &soc15_set_vce_clocks,
895 .get_config_memsize = &soc15_get_config_memsize,
896 .need_full_reset = &soc15_need_full_reset,
897 .init_doorbell_index = &aqua_vanjaram_doorbell_index_init,
898 .get_pcie_usage = &amdgpu_nbio_get_pcie_usage,
899 .need_reset_on_init = &soc15_need_reset_on_init,
900 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
901 .supports_baco = &soc15_supports_baco,
902 .pre_asic_init = &soc15_pre_asic_init,
903 .query_video_codecs = &soc15_query_video_codecs,
904 .encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing,
905 };
906
soc15_common_early_init(void * handle)907 static int soc15_common_early_init(void *handle)
908 {
909 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
910 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
911
912 if (!amdgpu_sriov_vf(adev)) {
913 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
914 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
915 }
916 adev->smc_rreg = NULL;
917 adev->smc_wreg = NULL;
918 adev->pcie_rreg = &amdgpu_device_indirect_rreg;
919 adev->pcie_wreg = &amdgpu_device_indirect_wreg;
920 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext;
921 adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext;
922 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
923 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
924 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
925 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
926 adev->didt_rreg = &soc15_didt_rreg;
927 adev->didt_wreg = &soc15_didt_wreg;
928 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
929 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
930 adev->se_cac_rreg = &soc15_se_cac_rreg;
931 adev->se_cac_wreg = &soc15_se_cac_wreg;
932
933 adev->rev_id = amdgpu_device_get_rev_id(adev);
934 adev->external_rev_id = 0xFF;
935 /* TODO: split the GC and PG flags based on the relevant IP version for which
936 * they are relevant.
937 */
938 switch (adev->ip_versions[GC_HWIP][0]) {
939 case IP_VERSION(9, 0, 1):
940 adev->asic_funcs = &soc15_asic_funcs;
941 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
942 AMD_CG_SUPPORT_GFX_MGLS |
943 AMD_CG_SUPPORT_GFX_RLC_LS |
944 AMD_CG_SUPPORT_GFX_CP_LS |
945 AMD_CG_SUPPORT_GFX_3D_CGCG |
946 AMD_CG_SUPPORT_GFX_3D_CGLS |
947 AMD_CG_SUPPORT_GFX_CGCG |
948 AMD_CG_SUPPORT_GFX_CGLS |
949 AMD_CG_SUPPORT_BIF_MGCG |
950 AMD_CG_SUPPORT_BIF_LS |
951 AMD_CG_SUPPORT_HDP_LS |
952 AMD_CG_SUPPORT_DRM_MGCG |
953 AMD_CG_SUPPORT_DRM_LS |
954 AMD_CG_SUPPORT_ROM_MGCG |
955 AMD_CG_SUPPORT_DF_MGCG |
956 AMD_CG_SUPPORT_SDMA_MGCG |
957 AMD_CG_SUPPORT_SDMA_LS |
958 AMD_CG_SUPPORT_MC_MGCG |
959 AMD_CG_SUPPORT_MC_LS;
960 adev->pg_flags = 0;
961 adev->external_rev_id = 0x1;
962 break;
963 case IP_VERSION(9, 2, 1):
964 adev->asic_funcs = &soc15_asic_funcs;
965 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
966 AMD_CG_SUPPORT_GFX_MGLS |
967 AMD_CG_SUPPORT_GFX_CGCG |
968 AMD_CG_SUPPORT_GFX_CGLS |
969 AMD_CG_SUPPORT_GFX_3D_CGCG |
970 AMD_CG_SUPPORT_GFX_3D_CGLS |
971 AMD_CG_SUPPORT_GFX_CP_LS |
972 AMD_CG_SUPPORT_MC_LS |
973 AMD_CG_SUPPORT_MC_MGCG |
974 AMD_CG_SUPPORT_SDMA_MGCG |
975 AMD_CG_SUPPORT_SDMA_LS |
976 AMD_CG_SUPPORT_BIF_MGCG |
977 AMD_CG_SUPPORT_BIF_LS |
978 AMD_CG_SUPPORT_HDP_MGCG |
979 AMD_CG_SUPPORT_HDP_LS |
980 AMD_CG_SUPPORT_ROM_MGCG |
981 AMD_CG_SUPPORT_VCE_MGCG |
982 AMD_CG_SUPPORT_UVD_MGCG;
983 adev->pg_flags = 0;
984 adev->external_rev_id = adev->rev_id + 0x14;
985 break;
986 case IP_VERSION(9, 4, 0):
987 adev->asic_funcs = &vega20_asic_funcs;
988 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
989 AMD_CG_SUPPORT_GFX_MGLS |
990 AMD_CG_SUPPORT_GFX_CGCG |
991 AMD_CG_SUPPORT_GFX_CGLS |
992 AMD_CG_SUPPORT_GFX_3D_CGCG |
993 AMD_CG_SUPPORT_GFX_3D_CGLS |
994 AMD_CG_SUPPORT_GFX_CP_LS |
995 AMD_CG_SUPPORT_MC_LS |
996 AMD_CG_SUPPORT_MC_MGCG |
997 AMD_CG_SUPPORT_SDMA_MGCG |
998 AMD_CG_SUPPORT_SDMA_LS |
999 AMD_CG_SUPPORT_BIF_MGCG |
1000 AMD_CG_SUPPORT_BIF_LS |
1001 AMD_CG_SUPPORT_HDP_MGCG |
1002 AMD_CG_SUPPORT_HDP_LS |
1003 AMD_CG_SUPPORT_ROM_MGCG |
1004 AMD_CG_SUPPORT_VCE_MGCG |
1005 AMD_CG_SUPPORT_UVD_MGCG;
1006 adev->pg_flags = 0;
1007 adev->external_rev_id = adev->rev_id + 0x28;
1008 break;
1009 case IP_VERSION(9, 1, 0):
1010 case IP_VERSION(9, 2, 2):
1011 adev->asic_funcs = &soc15_asic_funcs;
1012
1013 if (adev->rev_id >= 0x8)
1014 adev->apu_flags |= AMD_APU_IS_RAVEN2;
1015
1016 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1017 adev->external_rev_id = adev->rev_id + 0x79;
1018 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1019 adev->external_rev_id = adev->rev_id + 0x41;
1020 else if (adev->rev_id == 1)
1021 adev->external_rev_id = adev->rev_id + 0x20;
1022 else
1023 adev->external_rev_id = adev->rev_id + 0x01;
1024
1025 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1026 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1027 AMD_CG_SUPPORT_GFX_MGLS |
1028 AMD_CG_SUPPORT_GFX_CP_LS |
1029 AMD_CG_SUPPORT_GFX_3D_CGCG |
1030 AMD_CG_SUPPORT_GFX_3D_CGLS |
1031 AMD_CG_SUPPORT_GFX_CGCG |
1032 AMD_CG_SUPPORT_GFX_CGLS |
1033 AMD_CG_SUPPORT_BIF_LS |
1034 AMD_CG_SUPPORT_HDP_LS |
1035 AMD_CG_SUPPORT_MC_MGCG |
1036 AMD_CG_SUPPORT_MC_LS |
1037 AMD_CG_SUPPORT_SDMA_MGCG |
1038 AMD_CG_SUPPORT_SDMA_LS |
1039 AMD_CG_SUPPORT_VCN_MGCG;
1040
1041 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1042 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1043 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1044 AMD_CG_SUPPORT_GFX_MGLS |
1045 AMD_CG_SUPPORT_GFX_CP_LS |
1046 AMD_CG_SUPPORT_GFX_3D_CGLS |
1047 AMD_CG_SUPPORT_GFX_CGCG |
1048 AMD_CG_SUPPORT_GFX_CGLS |
1049 AMD_CG_SUPPORT_BIF_LS |
1050 AMD_CG_SUPPORT_HDP_LS |
1051 AMD_CG_SUPPORT_MC_MGCG |
1052 AMD_CG_SUPPORT_MC_LS |
1053 AMD_CG_SUPPORT_SDMA_MGCG |
1054 AMD_CG_SUPPORT_SDMA_LS |
1055 AMD_CG_SUPPORT_VCN_MGCG;
1056
1057 /*
1058 * MMHUB PG needs to be disabled for Picasso for
1059 * stability reasons.
1060 */
1061 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1062 AMD_PG_SUPPORT_VCN;
1063 } else {
1064 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1065 AMD_CG_SUPPORT_GFX_MGLS |
1066 AMD_CG_SUPPORT_GFX_RLC_LS |
1067 AMD_CG_SUPPORT_GFX_CP_LS |
1068 AMD_CG_SUPPORT_GFX_3D_CGLS |
1069 AMD_CG_SUPPORT_GFX_CGCG |
1070 AMD_CG_SUPPORT_GFX_CGLS |
1071 AMD_CG_SUPPORT_BIF_MGCG |
1072 AMD_CG_SUPPORT_BIF_LS |
1073 AMD_CG_SUPPORT_HDP_MGCG |
1074 AMD_CG_SUPPORT_HDP_LS |
1075 AMD_CG_SUPPORT_DRM_MGCG |
1076 AMD_CG_SUPPORT_DRM_LS |
1077 AMD_CG_SUPPORT_MC_MGCG |
1078 AMD_CG_SUPPORT_MC_LS |
1079 AMD_CG_SUPPORT_SDMA_MGCG |
1080 AMD_CG_SUPPORT_SDMA_LS |
1081 AMD_CG_SUPPORT_VCN_MGCG;
1082
1083 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1084 }
1085 break;
1086 case IP_VERSION(9, 4, 1):
1087 adev->asic_funcs = &vega20_asic_funcs;
1088 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1089 AMD_CG_SUPPORT_GFX_MGLS |
1090 AMD_CG_SUPPORT_GFX_CGCG |
1091 AMD_CG_SUPPORT_GFX_CGLS |
1092 AMD_CG_SUPPORT_GFX_CP_LS |
1093 AMD_CG_SUPPORT_HDP_MGCG |
1094 AMD_CG_SUPPORT_HDP_LS |
1095 AMD_CG_SUPPORT_SDMA_MGCG |
1096 AMD_CG_SUPPORT_SDMA_LS |
1097 AMD_CG_SUPPORT_MC_MGCG |
1098 AMD_CG_SUPPORT_MC_LS |
1099 AMD_CG_SUPPORT_IH_CG |
1100 AMD_CG_SUPPORT_VCN_MGCG |
1101 AMD_CG_SUPPORT_JPEG_MGCG;
1102 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1103 adev->external_rev_id = adev->rev_id + 0x32;
1104 break;
1105 case IP_VERSION(9, 3, 0):
1106 adev->asic_funcs = &soc15_asic_funcs;
1107
1108 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1109 adev->external_rev_id = adev->rev_id + 0x91;
1110 else
1111 adev->external_rev_id = adev->rev_id + 0xa1;
1112 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1113 AMD_CG_SUPPORT_GFX_MGLS |
1114 AMD_CG_SUPPORT_GFX_3D_CGCG |
1115 AMD_CG_SUPPORT_GFX_3D_CGLS |
1116 AMD_CG_SUPPORT_GFX_CGCG |
1117 AMD_CG_SUPPORT_GFX_CGLS |
1118 AMD_CG_SUPPORT_GFX_CP_LS |
1119 AMD_CG_SUPPORT_MC_MGCG |
1120 AMD_CG_SUPPORT_MC_LS |
1121 AMD_CG_SUPPORT_SDMA_MGCG |
1122 AMD_CG_SUPPORT_SDMA_LS |
1123 AMD_CG_SUPPORT_BIF_LS |
1124 AMD_CG_SUPPORT_HDP_LS |
1125 AMD_CG_SUPPORT_VCN_MGCG |
1126 AMD_CG_SUPPORT_JPEG_MGCG |
1127 AMD_CG_SUPPORT_IH_CG |
1128 AMD_CG_SUPPORT_ATHUB_LS |
1129 AMD_CG_SUPPORT_ATHUB_MGCG |
1130 AMD_CG_SUPPORT_DF_MGCG;
1131 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1132 AMD_PG_SUPPORT_VCN |
1133 AMD_PG_SUPPORT_JPEG |
1134 AMD_PG_SUPPORT_VCN_DPG;
1135 break;
1136 case IP_VERSION(9, 4, 2):
1137 adev->asic_funcs = &vega20_asic_funcs;
1138 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1139 AMD_CG_SUPPORT_GFX_MGLS |
1140 AMD_CG_SUPPORT_GFX_CP_LS |
1141 AMD_CG_SUPPORT_HDP_LS |
1142 AMD_CG_SUPPORT_SDMA_MGCG |
1143 AMD_CG_SUPPORT_SDMA_LS |
1144 AMD_CG_SUPPORT_IH_CG |
1145 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG;
1146 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
1147 adev->external_rev_id = adev->rev_id + 0x3c;
1148 break;
1149 case IP_VERSION(9, 4, 3):
1150 adev->asic_funcs = &aqua_vanjaram_asic_funcs;
1151 adev->cg_flags =
1152 AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG |
1153 AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG |
1154 AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_REPEATER_FGCG |
1155 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG |
1156 AMD_CG_SUPPORT_IH_CG;
1157 adev->pg_flags =
1158 AMD_PG_SUPPORT_VCN |
1159 AMD_PG_SUPPORT_VCN_DPG |
1160 AMD_PG_SUPPORT_JPEG;
1161 adev->external_rev_id = adev->rev_id + 0x46;
1162 break;
1163 default:
1164 /* FIXME: not supported yet */
1165 return -EINVAL;
1166 }
1167
1168 if (amdgpu_sriov_vf(adev)) {
1169 amdgpu_virt_init_setting(adev);
1170 xgpu_ai_mailbox_set_irq_funcs(adev);
1171 }
1172
1173 return 0;
1174 }
1175
soc15_common_late_init(void * handle)1176 static int soc15_common_late_init(void *handle)
1177 {
1178 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1179
1180 if (amdgpu_sriov_vf(adev))
1181 xgpu_ai_mailbox_get_irq(adev);
1182
1183 /* Enable selfring doorbell aperture late because doorbell BAR
1184 * aperture will change if resize BAR successfully in gmc sw_init.
1185 */
1186 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
1187
1188 return 0;
1189 }
1190
soc15_common_sw_init(void * handle)1191 static int soc15_common_sw_init(void *handle)
1192 {
1193 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1194
1195 if (amdgpu_sriov_vf(adev))
1196 xgpu_ai_mailbox_add_irq_id(adev);
1197
1198 if (adev->df.funcs &&
1199 adev->df.funcs->sw_init)
1200 adev->df.funcs->sw_init(adev);
1201
1202 return 0;
1203 }
1204
soc15_common_sw_fini(void * handle)1205 static int soc15_common_sw_fini(void *handle)
1206 {
1207 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1208
1209 if (adev->df.funcs &&
1210 adev->df.funcs->sw_fini)
1211 adev->df.funcs->sw_fini(adev);
1212 return 0;
1213 }
1214
soc15_sdma_doorbell_range_init(struct amdgpu_device * adev)1215 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)
1216 {
1217 int i;
1218
1219 /* sdma doorbell range is programed by hypervisor */
1220 if (!amdgpu_sriov_vf(adev)) {
1221 for (i = 0; i < adev->sdma.num_instances; i++) {
1222 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1223 true, adev->doorbell_index.sdma_engine[i] << 1,
1224 adev->doorbell_index.sdma_doorbell_range);
1225 }
1226 }
1227 }
1228
soc15_common_hw_init(void * handle)1229 static int soc15_common_hw_init(void *handle)
1230 {
1231 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1232
1233 /* enable aspm */
1234 soc15_program_aspm(adev);
1235 /* setup nbio registers */
1236 adev->nbio.funcs->init_registers(adev);
1237 /* remap HDP registers to a hole in mmio space,
1238 * for the purpose of expose those registers
1239 * to process space
1240 */
1241 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1242 adev->nbio.funcs->remap_hdp_registers(adev);
1243
1244 /* enable the doorbell aperture */
1245 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
1246
1247 /* HW doorbell routing policy: doorbell writing not
1248 * in SDMA/IH/MM/ACV range will be routed to CP. So
1249 * we need to init SDMA doorbell range prior
1250 * to CP ip block init and ring test. IH already
1251 * happens before CP.
1252 */
1253 soc15_sdma_doorbell_range_init(adev);
1254
1255 return 0;
1256 }
1257
soc15_common_hw_fini(void * handle)1258 static int soc15_common_hw_fini(void *handle)
1259 {
1260 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1261
1262 /* Disable the doorbell aperture and selfring doorbell aperture
1263 * separately in hw_fini because soc15_enable_doorbell_aperture
1264 * has been removed and there is no need to delay disabling
1265 * selfring doorbell.
1266 */
1267 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
1268 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
1269
1270 if (amdgpu_sriov_vf(adev))
1271 xgpu_ai_mailbox_put_irq(adev);
1272
1273 if (adev->nbio.ras_if &&
1274 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1275 if (adev->nbio.ras &&
1276 adev->nbio.ras->init_ras_controller_interrupt)
1277 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1278 if (adev->nbio.ras &&
1279 adev->nbio.ras->init_ras_err_event_athub_interrupt)
1280 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1281 }
1282
1283 return 0;
1284 }
1285
soc15_common_suspend(void * handle)1286 static int soc15_common_suspend(void *handle)
1287 {
1288 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1289
1290 return soc15_common_hw_fini(adev);
1291 }
1292
soc15_common_resume(void * handle)1293 static int soc15_common_resume(void *handle)
1294 {
1295 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1296
1297 return soc15_common_hw_init(adev);
1298 }
1299
soc15_common_is_idle(void * handle)1300 static bool soc15_common_is_idle(void *handle)
1301 {
1302 return true;
1303 }
1304
soc15_common_wait_for_idle(void * handle)1305 static int soc15_common_wait_for_idle(void *handle)
1306 {
1307 return 0;
1308 }
1309
soc15_common_soft_reset(void * handle)1310 static int soc15_common_soft_reset(void *handle)
1311 {
1312 return 0;
1313 }
1314
soc15_update_drm_clock_gating(struct amdgpu_device * adev,bool enable)1315 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1316 {
1317 uint32_t def, data;
1318
1319 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1320
1321 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1322 data &= ~(0x01000000 |
1323 0x02000000 |
1324 0x04000000 |
1325 0x08000000 |
1326 0x10000000 |
1327 0x20000000 |
1328 0x40000000 |
1329 0x80000000);
1330 else
1331 data |= (0x01000000 |
1332 0x02000000 |
1333 0x04000000 |
1334 0x08000000 |
1335 0x10000000 |
1336 0x20000000 |
1337 0x40000000 |
1338 0x80000000);
1339
1340 if (def != data)
1341 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1342 }
1343
soc15_update_drm_light_sleep(struct amdgpu_device * adev,bool enable)1344 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1345 {
1346 uint32_t def, data;
1347
1348 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1349
1350 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1351 data |= 1;
1352 else
1353 data &= ~1;
1354
1355 if (def != data)
1356 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1357 }
1358
soc15_common_set_clockgating_state(void * handle,enum amd_clockgating_state state)1359 static int soc15_common_set_clockgating_state(void *handle,
1360 enum amd_clockgating_state state)
1361 {
1362 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1363
1364 if (amdgpu_sriov_vf(adev))
1365 return 0;
1366
1367 switch (adev->ip_versions[NBIO_HWIP][0]) {
1368 case IP_VERSION(6, 1, 0):
1369 case IP_VERSION(6, 2, 0):
1370 case IP_VERSION(7, 4, 0):
1371 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1372 state == AMD_CG_STATE_GATE);
1373 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1374 state == AMD_CG_STATE_GATE);
1375 adev->hdp.funcs->update_clock_gating(adev,
1376 state == AMD_CG_STATE_GATE);
1377 soc15_update_drm_clock_gating(adev,
1378 state == AMD_CG_STATE_GATE);
1379 soc15_update_drm_light_sleep(adev,
1380 state == AMD_CG_STATE_GATE);
1381 adev->smuio.funcs->update_rom_clock_gating(adev,
1382 state == AMD_CG_STATE_GATE);
1383 adev->df.funcs->update_medium_grain_clock_gating(adev,
1384 state == AMD_CG_STATE_GATE);
1385 break;
1386 case IP_VERSION(7, 0, 0):
1387 case IP_VERSION(7, 0, 1):
1388 case IP_VERSION(2, 5, 0):
1389 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1390 state == AMD_CG_STATE_GATE);
1391 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1392 state == AMD_CG_STATE_GATE);
1393 adev->hdp.funcs->update_clock_gating(adev,
1394 state == AMD_CG_STATE_GATE);
1395 soc15_update_drm_clock_gating(adev,
1396 state == AMD_CG_STATE_GATE);
1397 soc15_update_drm_light_sleep(adev,
1398 state == AMD_CG_STATE_GATE);
1399 break;
1400 case IP_VERSION(7, 4, 1):
1401 case IP_VERSION(7, 4, 4):
1402 adev->hdp.funcs->update_clock_gating(adev,
1403 state == AMD_CG_STATE_GATE);
1404 break;
1405 default:
1406 break;
1407 }
1408 return 0;
1409 }
1410
soc15_common_get_clockgating_state(void * handle,u64 * flags)1411 static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
1412 {
1413 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1414 int data;
1415
1416 if (amdgpu_sriov_vf(adev))
1417 *flags = 0;
1418
1419 adev->nbio.funcs->get_clockgating_state(adev, flags);
1420
1421 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1422
1423 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) {
1424
1425 /* AMD_CG_SUPPORT_DRM_MGCG */
1426 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1427 if (!(data & 0x01000000))
1428 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1429
1430 /* AMD_CG_SUPPORT_DRM_LS */
1431 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1432 if (data & 0x1)
1433 *flags |= AMD_CG_SUPPORT_DRM_LS;
1434 }
1435
1436 /* AMD_CG_SUPPORT_ROM_MGCG */
1437 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1438
1439 adev->df.funcs->get_clockgating_state(adev, flags);
1440 }
1441
soc15_common_set_powergating_state(void * handle,enum amd_powergating_state state)1442 static int soc15_common_set_powergating_state(void *handle,
1443 enum amd_powergating_state state)
1444 {
1445 /* todo */
1446 return 0;
1447 }
1448
1449 static const struct amd_ip_funcs soc15_common_ip_funcs = {
1450 .name = "soc15_common",
1451 .early_init = soc15_common_early_init,
1452 .late_init = soc15_common_late_init,
1453 .sw_init = soc15_common_sw_init,
1454 .sw_fini = soc15_common_sw_fini,
1455 .hw_init = soc15_common_hw_init,
1456 .hw_fini = soc15_common_hw_fini,
1457 .suspend = soc15_common_suspend,
1458 .resume = soc15_common_resume,
1459 .is_idle = soc15_common_is_idle,
1460 .wait_for_idle = soc15_common_wait_for_idle,
1461 .soft_reset = soc15_common_soft_reset,
1462 .set_clockgating_state = soc15_common_set_clockgating_state,
1463 .set_powergating_state = soc15_common_set_powergating_state,
1464 .get_clockgating_state= soc15_common_get_clockgating_state,
1465 };
1466
