1 /*
2 * Copyright (C) 2015 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 /**
10 * DOC: VC4 CRTC module
11 *
12 * In VC4, the Pixel Valve is what most closely corresponds to the
13 * DRM's concept of a CRTC. The PV generates video timings from the
14 * encoder's clock plus its configuration. It pulls scaled pixels from
15 * the HVS at that timing, and feeds it to the encoder.
16 *
17 * However, the DRM CRTC also collects the configuration of all the
18 * DRM planes attached to it. As a result, the CRTC is also
19 * responsible for writing the display list for the HVS channel that
20 * the CRTC will use.
21 *
22 * The 2835 has 3 different pixel valves. pv0 in the audio power
23 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
24 * image domain can feed either HDMI or the SDTV controller. The
25 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
26 * SDTV, etc.) according to which output type is chosen in the mux.
27 *
28 * For power management, the pixel valve's registers are all clocked
29 * by the AXI clock, while the timings and FIFOs make use of the
30 * output-specific clock. Since the encoders also directly consume
31 * the CPRMAN clocks, and know what timings they need, they are the
32 * ones that set the clock.
33 */
34
35 #include <drm/drm_atomic.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc_helper.h>
38 #include <linux/clk.h>
39 #include <drm/drm_fb_cma_helper.h>
40 #include <linux/component.h>
41 #include <linux/of_device.h>
42 #include "vc4_drv.h"
43 #include "vc4_regs.h"
44
45 struct vc4_crtc_state {
46 struct drm_crtc_state base;
47 /* Dlist area for this CRTC configuration. */
48 struct drm_mm_node mm;
49 bool feed_txp;
50 bool txp_armed;
51 };
52
53 static inline struct vc4_crtc_state *
to_vc4_crtc_state(struct drm_crtc_state * crtc_state)54 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
55 {
56 return (struct vc4_crtc_state *)crtc_state;
57 }
58
59 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
60 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
61
62 #define CRTC_REG(reg) { reg, #reg }
63 static const struct {
64 u32 reg;
65 const char *name;
66 } crtc_regs[] = {
67 CRTC_REG(PV_CONTROL),
68 CRTC_REG(PV_V_CONTROL),
69 CRTC_REG(PV_VSYNCD_EVEN),
70 CRTC_REG(PV_HORZA),
71 CRTC_REG(PV_HORZB),
72 CRTC_REG(PV_VERTA),
73 CRTC_REG(PV_VERTB),
74 CRTC_REG(PV_VERTA_EVEN),
75 CRTC_REG(PV_VERTB_EVEN),
76 CRTC_REG(PV_INTEN),
77 CRTC_REG(PV_INTSTAT),
78 CRTC_REG(PV_STAT),
79 CRTC_REG(PV_HACT_ACT),
80 };
81
vc4_crtc_dump_regs(struct vc4_crtc * vc4_crtc)82 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
83 {
84 int i;
85
86 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
87 DRM_INFO("0x%04x (%s): 0x%08x\n",
88 crtc_regs[i].reg, crtc_regs[i].name,
89 CRTC_READ(crtc_regs[i].reg));
90 }
91 }
92
93 #ifdef CONFIG_DEBUG_FS
vc4_crtc_debugfs_regs(struct seq_file * m,void * unused)94 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
95 {
96 struct drm_info_node *node = (struct drm_info_node *)m->private;
97 struct drm_device *dev = node->minor->dev;
98 int crtc_index = (uintptr_t)node->info_ent->data;
99 struct drm_crtc *crtc;
100 struct vc4_crtc *vc4_crtc;
101 int i;
102
103 i = 0;
104 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
105 if (i == crtc_index)
106 break;
107 i++;
108 }
109 if (!crtc)
110 return 0;
111 vc4_crtc = to_vc4_crtc(crtc);
112
113 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
114 seq_printf(m, "%s (0x%04x): 0x%08x\n",
115 crtc_regs[i].name, crtc_regs[i].reg,
116 CRTC_READ(crtc_regs[i].reg));
117 }
118
119 return 0;
120 }
121 #endif
122
vc4_crtc_get_scanoutpos(struct drm_device * dev,unsigned int crtc_id,bool in_vblank_irq,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)123 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
124 bool in_vblank_irq, int *vpos, int *hpos,
125 ktime_t *stime, ktime_t *etime,
126 const struct drm_display_mode *mode)
127 {
128 struct vc4_dev *vc4 = to_vc4_dev(dev);
129 struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
130 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
131 u32 val;
132 int fifo_lines;
133 int vblank_lines;
134 bool ret = false;
135
136 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
137
138 /* Get optional system timestamp before query. */
139 if (stime)
140 *stime = ktime_get();
141
142 /*
143 * Read vertical scanline which is currently composed for our
144 * pixelvalve by the HVS, and also the scaler status.
145 */
146 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
147
148 /* Get optional system timestamp after query. */
149 if (etime)
150 *etime = ktime_get();
151
152 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
153
154 /* Vertical position of hvs composed scanline. */
155 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
156 *hpos = 0;
157
158 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
159 *vpos /= 2;
160
161 /* Use hpos to correct for field offset in interlaced mode. */
162 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
163 *hpos += mode->crtc_htotal / 2;
164 }
165
166 /* This is the offset we need for translating hvs -> pv scanout pos. */
167 fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
168
169 if (fifo_lines > 0)
170 ret = true;
171
172 /* HVS more than fifo_lines into frame for compositing? */
173 if (*vpos > fifo_lines) {
174 /*
175 * We are in active scanout and can get some meaningful results
176 * from HVS. The actual PV scanout can not trail behind more
177 * than fifo_lines as that is the fifo's capacity. Assume that
178 * in active scanout the HVS and PV work in lockstep wrt. HVS
179 * refilling the fifo and PV consuming from the fifo, ie.
180 * whenever the PV consumes and frees up a scanline in the
181 * fifo, the HVS will immediately refill it, therefore
182 * incrementing vpos. Therefore we choose HVS read position -
183 * fifo size in scanlines as a estimate of the real scanout
184 * position of the PV.
185 */
186 *vpos -= fifo_lines + 1;
187
188 return ret;
189 }
190
191 /*
192 * Less: This happens when we are in vblank and the HVS, after getting
193 * the VSTART restart signal from the PV, just started refilling its
194 * fifo with new lines from the top-most lines of the new framebuffers.
195 * The PV does not scan out in vblank, so does not remove lines from
196 * the fifo, so the fifo will be full quickly and the HVS has to pause.
197 * We can't get meaningful readings wrt. scanline position of the PV
198 * and need to make things up in a approximative but consistent way.
199 */
200 vblank_lines = mode->vtotal - mode->vdisplay;
201
202 if (in_vblank_irq) {
203 /*
204 * Assume the irq handler got called close to first
205 * line of vblank, so PV has about a full vblank
206 * scanlines to go, and as a base timestamp use the
207 * one taken at entry into vblank irq handler, so it
208 * is not affected by random delays due to lock
209 * contention on event_lock or vblank_time lock in
210 * the core.
211 */
212 *vpos = -vblank_lines;
213
214 if (stime)
215 *stime = vc4_crtc->t_vblank;
216 if (etime)
217 *etime = vc4_crtc->t_vblank;
218
219 /*
220 * If the HVS fifo is not yet full then we know for certain
221 * we are at the very beginning of vblank, as the hvs just
222 * started refilling, and the stime and etime timestamps
223 * truly correspond to start of vblank.
224 *
225 * Unfortunately there's no way to report this to upper levels
226 * and make it more useful.
227 */
228 } else {
229 /*
230 * No clue where we are inside vblank. Return a vpos of zero,
231 * which will cause calling code to just return the etime
232 * timestamp uncorrected. At least this is no worse than the
233 * standard fallback.
234 */
235 *vpos = 0;
236 }
237
238 return ret;
239 }
240
vc4_crtc_destroy(struct drm_crtc * crtc)241 static void vc4_crtc_destroy(struct drm_crtc *crtc)
242 {
243 drm_crtc_cleanup(crtc);
244 }
245
246 static void
vc4_crtc_lut_load(struct drm_crtc * crtc)247 vc4_crtc_lut_load(struct drm_crtc *crtc)
248 {
249 struct drm_device *dev = crtc->dev;
250 struct vc4_dev *vc4 = to_vc4_dev(dev);
251 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
252 u32 i;
253
254 /* The LUT memory is laid out with each HVS channel in order,
255 * each of which takes 256 writes for R, 256 for G, then 256
256 * for B.
257 */
258 HVS_WRITE(SCALER_GAMADDR,
259 SCALER_GAMADDR_AUTOINC |
260 (vc4_crtc->channel * 3 * crtc->gamma_size));
261
262 for (i = 0; i < crtc->gamma_size; i++)
263 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
264 for (i = 0; i < crtc->gamma_size; i++)
265 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
266 for (i = 0; i < crtc->gamma_size; i++)
267 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
268 }
269
270 static void
vc4_crtc_update_gamma_lut(struct drm_crtc * crtc)271 vc4_crtc_update_gamma_lut(struct drm_crtc *crtc)
272 {
273 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
274 struct drm_color_lut *lut = crtc->state->gamma_lut->data;
275 u32 length = drm_color_lut_size(crtc->state->gamma_lut);
276 u32 i;
277
278 for (i = 0; i < length; i++) {
279 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
280 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
281 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
282 }
283
284 vc4_crtc_lut_load(crtc);
285 }
286
vc4_get_fifo_full_level(u32 format)287 static u32 vc4_get_fifo_full_level(u32 format)
288 {
289 static const u32 fifo_len_bytes = 64;
290 static const u32 hvs_latency_pix = 6;
291
292 switch (format) {
293 case PV_CONTROL_FORMAT_DSIV_16:
294 case PV_CONTROL_FORMAT_DSIC_16:
295 return fifo_len_bytes - 2 * hvs_latency_pix;
296 case PV_CONTROL_FORMAT_DSIV_18:
297 return fifo_len_bytes - 14;
298 case PV_CONTROL_FORMAT_24:
299 case PV_CONTROL_FORMAT_DSIV_24:
300 default:
301 return fifo_len_bytes - 3 * hvs_latency_pix;
302 }
303 }
304
305 /*
306 * Returns the encoder attached to the CRTC.
307 *
308 * VC4 can only scan out to one encoder at a time, while the DRM core
309 * allows drivers to push pixels to more than one encoder from the
310 * same CRTC.
311 */
vc4_get_crtc_encoder(struct drm_crtc * crtc)312 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
313 {
314 struct drm_connector *connector;
315 struct drm_connector_list_iter conn_iter;
316
317 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
318 drm_for_each_connector_iter(connector, &conn_iter) {
319 if (connector->state->crtc == crtc) {
320 drm_connector_list_iter_end(&conn_iter);
321 return connector->encoder;
322 }
323 }
324 drm_connector_list_iter_end(&conn_iter);
325
326 return NULL;
327 }
328
vc4_crtc_config_pv(struct drm_crtc * crtc)329 static void vc4_crtc_config_pv(struct drm_crtc *crtc)
330 {
331 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
332 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
333 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
334 struct drm_crtc_state *state = crtc->state;
335 struct drm_display_mode *mode = &state->adjusted_mode;
336 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
337 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
338 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
339 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
340 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
341
342 /* Reset the PV fifo. */
343 CRTC_WRITE(PV_CONTROL, 0);
344 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
345 CRTC_WRITE(PV_CONTROL, 0);
346
347 CRTC_WRITE(PV_HORZA,
348 VC4_SET_FIELD((mode->htotal -
349 mode->hsync_end) * pixel_rep,
350 PV_HORZA_HBP) |
351 VC4_SET_FIELD((mode->hsync_end -
352 mode->hsync_start) * pixel_rep,
353 PV_HORZA_HSYNC));
354 CRTC_WRITE(PV_HORZB,
355 VC4_SET_FIELD((mode->hsync_start -
356 mode->hdisplay) * pixel_rep,
357 PV_HORZB_HFP) |
358 VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
359
360 CRTC_WRITE(PV_VERTA,
361 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
362 PV_VERTA_VBP) |
363 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
364 PV_VERTA_VSYNC));
365 CRTC_WRITE(PV_VERTB,
366 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
367 PV_VERTB_VFP) |
368 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
369
370 if (interlace) {
371 CRTC_WRITE(PV_VERTA_EVEN,
372 VC4_SET_FIELD(mode->crtc_vtotal -
373 mode->crtc_vsync_end - 1,
374 PV_VERTA_VBP) |
375 VC4_SET_FIELD(mode->crtc_vsync_end -
376 mode->crtc_vsync_start,
377 PV_VERTA_VSYNC));
378 CRTC_WRITE(PV_VERTB_EVEN,
379 VC4_SET_FIELD(mode->crtc_vsync_start -
380 mode->crtc_vdisplay,
381 PV_VERTB_VFP) |
382 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
383
384 /* We set up first field even mode for HDMI. VEC's
385 * NTSC mode would want first field odd instead, once
386 * we support it (to do so, set ODD_FIRST and put the
387 * delay in VSYNCD_EVEN instead).
388 */
389 CRTC_WRITE(PV_V_CONTROL,
390 PV_VCONTROL_CONTINUOUS |
391 (is_dsi ? PV_VCONTROL_DSI : 0) |
392 PV_VCONTROL_INTERLACE |
393 VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
394 PV_VCONTROL_ODD_DELAY));
395 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
396 } else {
397 CRTC_WRITE(PV_V_CONTROL,
398 PV_VCONTROL_CONTINUOUS |
399 (is_dsi ? PV_VCONTROL_DSI : 0));
400 }
401
402 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
403
404 CRTC_WRITE(PV_CONTROL,
405 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
406 VC4_SET_FIELD(vc4_get_fifo_full_level(format),
407 PV_CONTROL_FIFO_LEVEL) |
408 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
409 PV_CONTROL_CLR_AT_START |
410 PV_CONTROL_TRIGGER_UNDERFLOW |
411 PV_CONTROL_WAIT_HSTART |
412 VC4_SET_FIELD(vc4_encoder->clock_select,
413 PV_CONTROL_CLK_SELECT) |
414 PV_CONTROL_FIFO_CLR |
415 PV_CONTROL_EN);
416 }
417
vc4_crtc_mode_set_nofb(struct drm_crtc * crtc)418 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
419 {
420 struct drm_device *dev = crtc->dev;
421 struct vc4_dev *vc4 = to_vc4_dev(dev);
422 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
423 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
424 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
425 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
426 bool debug_dump_regs = false;
427
428 if (debug_dump_regs) {
429 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
430 vc4_crtc_dump_regs(vc4_crtc);
431 }
432
433 if (vc4_crtc->channel == 2) {
434 u32 dispctrl;
435 u32 dsp3_mux;
436
437 /*
438 * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
439 * FIFO X'.
440 * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
441 *
442 * DSP3 is connected to FIFO2 unless the transposer is
443 * enabled. In this case, FIFO 2 is directly accessed by the
444 * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
445 * route.
446 */
447 if (vc4_state->feed_txp)
448 dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
449 else
450 dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
451
452 dispctrl = HVS_READ(SCALER_DISPCTRL) &
453 ~SCALER_DISPCTRL_DSP3_MUX_MASK;
454 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
455 }
456
457 if (!vc4_state->feed_txp)
458 vc4_crtc_config_pv(crtc);
459
460 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
461 SCALER_DISPBKGND_AUTOHS |
462 SCALER_DISPBKGND_GAMMA |
463 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
464
465 /* Reload the LUT, since the SRAMs would have been disabled if
466 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
467 */
468 vc4_crtc_lut_load(crtc);
469
470 if (debug_dump_regs) {
471 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
472 vc4_crtc_dump_regs(vc4_crtc);
473 }
474 }
475
require_hvs_enabled(struct drm_device * dev)476 static void require_hvs_enabled(struct drm_device *dev)
477 {
478 struct vc4_dev *vc4 = to_vc4_dev(dev);
479
480 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
481 SCALER_DISPCTRL_ENABLE);
482 }
483
vc4_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)484 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
485 struct drm_crtc_state *old_state)
486 {
487 struct drm_device *dev = crtc->dev;
488 struct vc4_dev *vc4 = to_vc4_dev(dev);
489 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
490 u32 chan = vc4_crtc->channel;
491 int ret;
492 require_hvs_enabled(dev);
493
494 /* Disable vblank irq handling before crtc is disabled. */
495 drm_crtc_vblank_off(crtc);
496
497 CRTC_WRITE(PV_V_CONTROL,
498 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
499 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
500 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
501
502 if (HVS_READ(SCALER_DISPCTRLX(chan)) &
503 SCALER_DISPCTRLX_ENABLE) {
504 HVS_WRITE(SCALER_DISPCTRLX(chan),
505 SCALER_DISPCTRLX_RESET);
506
507 /* While the docs say that reset is self-clearing, it
508 * seems it doesn't actually.
509 */
510 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
511 }
512
513 /* Once we leave, the scaler should be disabled and its fifo empty. */
514
515 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
516
517 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
518 SCALER_DISPSTATX_MODE) !=
519 SCALER_DISPSTATX_MODE_DISABLED);
520
521 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
522 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
523 SCALER_DISPSTATX_EMPTY);
524
525 /*
526 * Make sure we issue a vblank event after disabling the CRTC if
527 * someone was waiting it.
528 */
529 if (crtc->state->event) {
530 unsigned long flags;
531
532 spin_lock_irqsave(&dev->event_lock, flags);
533 drm_crtc_send_vblank_event(crtc, crtc->state->event);
534 crtc->state->event = NULL;
535 spin_unlock_irqrestore(&dev->event_lock, flags);
536 }
537 }
538
vc4_crtc_txp_armed(struct drm_crtc_state * state)539 void vc4_crtc_txp_armed(struct drm_crtc_state *state)
540 {
541 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
542
543 vc4_state->txp_armed = true;
544 }
545
vc4_crtc_update_dlist(struct drm_crtc * crtc)546 static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
547 {
548 struct drm_device *dev = crtc->dev;
549 struct vc4_dev *vc4 = to_vc4_dev(dev);
550 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
551 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
552
553 if (crtc->state->event) {
554 unsigned long flags;
555
556 crtc->state->event->pipe = drm_crtc_index(crtc);
557
558 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
559
560 spin_lock_irqsave(&dev->event_lock, flags);
561
562 if (!vc4_state->feed_txp || vc4_state->txp_armed) {
563 vc4_crtc->event = crtc->state->event;
564 crtc->state->event = NULL;
565 }
566
567 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
568 vc4_state->mm.start);
569
570 spin_unlock_irqrestore(&dev->event_lock, flags);
571 } else {
572 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
573 vc4_state->mm.start);
574 }
575 }
576
vc4_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)577 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
578 struct drm_crtc_state *old_state)
579 {
580 struct drm_device *dev = crtc->dev;
581 struct vc4_dev *vc4 = to_vc4_dev(dev);
582 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
583 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
584 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
585
586 require_hvs_enabled(dev);
587
588 /* Enable vblank irq handling before crtc is started otherwise
589 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
590 */
591 drm_crtc_vblank_on(crtc);
592 vc4_crtc_update_dlist(crtc);
593
594 /* Turn on the scaler, which will wait for vstart to start
595 * compositing.
596 * When feeding the transposer, we should operate in oneshot
597 * mode.
598 */
599 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
600 VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
601 VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
602 SCALER_DISPCTRLX_ENABLE |
603 (vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
604
605 /* When feeding the transposer block the pixelvalve is unneeded and
606 * should not be enabled.
607 */
608 if (!vc4_state->feed_txp)
609 CRTC_WRITE(PV_V_CONTROL,
610 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
611 }
612
vc4_crtc_mode_valid(struct drm_crtc * crtc,const struct drm_display_mode * mode)613 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
614 const struct drm_display_mode *mode)
615 {
616 /* Do not allow doublescan modes from user space */
617 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
618 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
619 crtc->base.id);
620 return MODE_NO_DBLESCAN;
621 }
622
623 return MODE_OK;
624 }
625
vc4_crtc_atomic_check(struct drm_crtc * crtc,struct drm_crtc_state * state)626 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
627 struct drm_crtc_state *state)
628 {
629 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
630 struct drm_device *dev = crtc->dev;
631 struct vc4_dev *vc4 = to_vc4_dev(dev);
632 struct drm_plane *plane;
633 unsigned long flags;
634 const struct drm_plane_state *plane_state;
635 struct drm_connector *conn;
636 struct drm_connector_state *conn_state;
637 u32 dlist_count = 0;
638 int ret, i;
639
640 /* The pixelvalve can only feed one encoder (and encoders are
641 * 1:1 with connectors.)
642 */
643 if (hweight32(state->connector_mask) > 1)
644 return -EINVAL;
645
646 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
647 dlist_count += vc4_plane_dlist_size(plane_state);
648
649 dlist_count++; /* Account for SCALER_CTL0_END. */
650
651 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
652 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
653 dlist_count);
654 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
655 if (ret)
656 return ret;
657
658 for_each_new_connector_in_state(state->state, conn, conn_state, i) {
659 if (conn_state->crtc != crtc)
660 continue;
661
662 /* The writeback connector is implemented using the transposer
663 * block which is directly taking its data from the HVS FIFO.
664 */
665 if (conn->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) {
666 state->no_vblank = true;
667 vc4_state->feed_txp = true;
668 } else {
669 state->no_vblank = false;
670 vc4_state->feed_txp = false;
671 }
672
673 break;
674 }
675
676 return 0;
677 }
678
vc4_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_crtc_state * old_state)679 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
680 struct drm_crtc_state *old_state)
681 {
682 struct drm_device *dev = crtc->dev;
683 struct vc4_dev *vc4 = to_vc4_dev(dev);
684 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
685 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
686 struct drm_plane *plane;
687 struct vc4_plane_state *vc4_plane_state;
688 bool debug_dump_regs = false;
689 bool enable_bg_fill = false;
690 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
691 u32 __iomem *dlist_next = dlist_start;
692
693 if (debug_dump_regs) {
694 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
695 vc4_hvs_dump_state(dev);
696 }
697
698 /* Copy all the active planes' dlist contents to the hardware dlist. */
699 drm_atomic_crtc_for_each_plane(plane, crtc) {
700 /* Is this the first active plane? */
701 if (dlist_next == dlist_start) {
702 /* We need to enable background fill when a plane
703 * could be alpha blending from the background, i.e.
704 * where no other plane is underneath. It suffices to
705 * consider the first active plane here since we set
706 * needs_bg_fill such that either the first plane
707 * already needs it or all planes on top blend from
708 * the first or a lower plane.
709 */
710 vc4_plane_state = to_vc4_plane_state(plane->state);
711 enable_bg_fill = vc4_plane_state->needs_bg_fill;
712 }
713
714 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
715 }
716
717 writel(SCALER_CTL0_END, dlist_next);
718 dlist_next++;
719
720 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
721
722 if (enable_bg_fill)
723 /* This sets a black background color fill, as is the case
724 * with other DRM drivers.
725 */
726 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
727 HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
728 SCALER_DISPBKGND_FILL);
729
730 /* Only update DISPLIST if the CRTC was already running and is not
731 * being disabled.
732 * vc4_crtc_enable() takes care of updating the dlist just after
733 * re-enabling VBLANK interrupts and before enabling the engine.
734 * If the CRTC is being disabled, there's no point in updating this
735 * information.
736 */
737 if (crtc->state->active && old_state->active)
738 vc4_crtc_update_dlist(crtc);
739
740 if (crtc->state->color_mgmt_changed) {
741 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel));
742
743 if (crtc->state->gamma_lut) {
744 vc4_crtc_update_gamma_lut(crtc);
745 dispbkgndx |= SCALER_DISPBKGND_GAMMA;
746 } else {
747 /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
748 * in hardware, which is the same as a linear lut that
749 * DRM expects us to use in absence of a user lut.
750 */
751 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
752 }
753 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), dispbkgndx);
754 }
755
756 if (debug_dump_regs) {
757 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
758 vc4_hvs_dump_state(dev);
759 }
760 }
761
vc4_enable_vblank(struct drm_crtc * crtc)762 static int vc4_enable_vblank(struct drm_crtc *crtc)
763 {
764 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
765
766 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
767
768 return 0;
769 }
770
vc4_disable_vblank(struct drm_crtc * crtc)771 static void vc4_disable_vblank(struct drm_crtc *crtc)
772 {
773 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
774
775 CRTC_WRITE(PV_INTEN, 0);
776 }
777
vc4_crtc_handle_page_flip(struct vc4_crtc * vc4_crtc)778 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
779 {
780 struct drm_crtc *crtc = &vc4_crtc->base;
781 struct drm_device *dev = crtc->dev;
782 struct vc4_dev *vc4 = to_vc4_dev(dev);
783 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
784 u32 chan = vc4_crtc->channel;
785 unsigned long flags;
786
787 spin_lock_irqsave(&dev->event_lock, flags);
788 if (vc4_crtc->event &&
789 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
790 vc4_state->feed_txp)) {
791 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
792 vc4_crtc->event = NULL;
793 drm_crtc_vblank_put(crtc);
794 }
795 spin_unlock_irqrestore(&dev->event_lock, flags);
796 }
797
vc4_crtc_handle_vblank(struct vc4_crtc * crtc)798 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
799 {
800 crtc->t_vblank = ktime_get();
801 drm_crtc_handle_vblank(&crtc->base);
802 vc4_crtc_handle_page_flip(crtc);
803 }
804
vc4_crtc_irq_handler(int irq,void * data)805 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
806 {
807 struct vc4_crtc *vc4_crtc = data;
808 u32 stat = CRTC_READ(PV_INTSTAT);
809 irqreturn_t ret = IRQ_NONE;
810
811 if (stat & PV_INT_VFP_START) {
812 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
813 vc4_crtc_handle_vblank(vc4_crtc);
814 ret = IRQ_HANDLED;
815 }
816
817 return ret;
818 }
819
820 struct vc4_async_flip_state {
821 struct drm_crtc *crtc;
822 struct drm_framebuffer *fb;
823 struct drm_framebuffer *old_fb;
824 struct drm_pending_vblank_event *event;
825
826 struct vc4_seqno_cb cb;
827 };
828
829 /* Called when the V3D execution for the BO being flipped to is done, so that
830 * we can actually update the plane's address to point to it.
831 */
832 static void
vc4_async_page_flip_complete(struct vc4_seqno_cb * cb)833 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
834 {
835 struct vc4_async_flip_state *flip_state =
836 container_of(cb, struct vc4_async_flip_state, cb);
837 struct drm_crtc *crtc = flip_state->crtc;
838 struct drm_device *dev = crtc->dev;
839 struct vc4_dev *vc4 = to_vc4_dev(dev);
840 struct drm_plane *plane = crtc->primary;
841
842 vc4_plane_async_set_fb(plane, flip_state->fb);
843 if (flip_state->event) {
844 unsigned long flags;
845
846 spin_lock_irqsave(&dev->event_lock, flags);
847 drm_crtc_send_vblank_event(crtc, flip_state->event);
848 spin_unlock_irqrestore(&dev->event_lock, flags);
849 }
850
851 drm_crtc_vblank_put(crtc);
852 drm_framebuffer_put(flip_state->fb);
853
854 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
855 * when the planes are updated through the async update path.
856 * FIXME: we should move to generic async-page-flip when it's
857 * available, so that we can get rid of this hand-made cleanup_fb()
858 * logic.
859 */
860 if (flip_state->old_fb) {
861 struct drm_gem_cma_object *cma_bo;
862 struct vc4_bo *bo;
863
864 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
865 bo = to_vc4_bo(&cma_bo->base);
866 vc4_bo_dec_usecnt(bo);
867 drm_framebuffer_put(flip_state->old_fb);
868 }
869
870 kfree(flip_state);
871
872 up(&vc4->async_modeset);
873 }
874
875 /* Implements async (non-vblank-synced) page flips.
876 *
877 * The page flip ioctl needs to return immediately, so we grab the
878 * modeset semaphore on the pipe, and queue the address update for
879 * when V3D is done with the BO being flipped to.
880 */
vc4_async_page_flip(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t flags)881 static int vc4_async_page_flip(struct drm_crtc *crtc,
882 struct drm_framebuffer *fb,
883 struct drm_pending_vblank_event *event,
884 uint32_t flags)
885 {
886 struct drm_device *dev = crtc->dev;
887 struct vc4_dev *vc4 = to_vc4_dev(dev);
888 struct drm_plane *plane = crtc->primary;
889 int ret = 0;
890 struct vc4_async_flip_state *flip_state;
891 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
892 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
893
894 /* Increment the BO usecnt here, so that we never end up with an
895 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
896 * plane is later updated through the non-async path.
897 * FIXME: we should move to generic async-page-flip when it's
898 * available, so that we can get rid of this hand-made prepare_fb()
899 * logic.
900 */
901 ret = vc4_bo_inc_usecnt(bo);
902 if (ret)
903 return ret;
904
905 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
906 if (!flip_state) {
907 vc4_bo_dec_usecnt(bo);
908 return -ENOMEM;
909 }
910
911 drm_framebuffer_get(fb);
912 flip_state->fb = fb;
913 flip_state->crtc = crtc;
914 flip_state->event = event;
915
916 /* Make sure all other async modesetes have landed. */
917 ret = down_interruptible(&vc4->async_modeset);
918 if (ret) {
919 drm_framebuffer_put(fb);
920 vc4_bo_dec_usecnt(bo);
921 kfree(flip_state);
922 return ret;
923 }
924
925 /* Save the current FB before it's replaced by the new one in
926 * drm_atomic_set_fb_for_plane(). We'll need the old FB in
927 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
928 * it consistent.
929 * FIXME: we should move to generic async-page-flip when it's
930 * available, so that we can get rid of this hand-made cleanup_fb()
931 * logic.
932 */
933 flip_state->old_fb = plane->state->fb;
934 if (flip_state->old_fb)
935 drm_framebuffer_get(flip_state->old_fb);
936
937 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
938
939 /* Immediately update the plane's legacy fb pointer, so that later
940 * modeset prep sees the state that will be present when the semaphore
941 * is released.
942 */
943 drm_atomic_set_fb_for_plane(plane->state, fb);
944
945 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
946 vc4_async_page_flip_complete);
947
948 /* Driver takes ownership of state on successful async commit. */
949 return 0;
950 }
951
vc4_page_flip(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t flags,struct drm_modeset_acquire_ctx * ctx)952 static int vc4_page_flip(struct drm_crtc *crtc,
953 struct drm_framebuffer *fb,
954 struct drm_pending_vblank_event *event,
955 uint32_t flags,
956 struct drm_modeset_acquire_ctx *ctx)
957 {
958 if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
959 return vc4_async_page_flip(crtc, fb, event, flags);
960 else
961 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
962 }
963
vc4_crtc_duplicate_state(struct drm_crtc * crtc)964 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
965 {
966 struct vc4_crtc_state *vc4_state, *old_vc4_state;
967
968 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
969 if (!vc4_state)
970 return NULL;
971
972 old_vc4_state = to_vc4_crtc_state(crtc->state);
973 vc4_state->feed_txp = old_vc4_state->feed_txp;
974
975 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
976 return &vc4_state->base;
977 }
978
vc4_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)979 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
980 struct drm_crtc_state *state)
981 {
982 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
983 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
984
985 if (vc4_state->mm.allocated) {
986 unsigned long flags;
987
988 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
989 drm_mm_remove_node(&vc4_state->mm);
990 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
991
992 }
993
994 drm_atomic_helper_crtc_destroy_state(crtc, state);
995 }
996
997 static void
vc4_crtc_reset(struct drm_crtc * crtc)998 vc4_crtc_reset(struct drm_crtc *crtc)
999 {
1000 if (crtc->state)
1001 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1002
1003 crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
1004 if (crtc->state)
1005 crtc->state->crtc = crtc;
1006 }
1007
1008 static const struct drm_crtc_funcs vc4_crtc_funcs = {
1009 .set_config = drm_atomic_helper_set_config,
1010 .destroy = vc4_crtc_destroy,
1011 .page_flip = vc4_page_flip,
1012 .set_property = NULL,
1013 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
1014 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
1015 .reset = vc4_crtc_reset,
1016 .atomic_duplicate_state = vc4_crtc_duplicate_state,
1017 .atomic_destroy_state = vc4_crtc_destroy_state,
1018 .gamma_set = drm_atomic_helper_legacy_gamma_set,
1019 .enable_vblank = vc4_enable_vblank,
1020 .disable_vblank = vc4_disable_vblank,
1021 };
1022
1023 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1024 .mode_set_nofb = vc4_crtc_mode_set_nofb,
1025 .mode_valid = vc4_crtc_mode_valid,
1026 .atomic_check = vc4_crtc_atomic_check,
1027 .atomic_flush = vc4_crtc_atomic_flush,
1028 .atomic_enable = vc4_crtc_atomic_enable,
1029 .atomic_disable = vc4_crtc_atomic_disable,
1030 };
1031
1032 static const struct vc4_crtc_data pv0_data = {
1033 .hvs_channel = 0,
1034 .encoder_types = {
1035 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1036 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1037 },
1038 };
1039
1040 static const struct vc4_crtc_data pv1_data = {
1041 .hvs_channel = 2,
1042 .encoder_types = {
1043 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1044 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1045 },
1046 };
1047
1048 static const struct vc4_crtc_data pv2_data = {
1049 .hvs_channel = 1,
1050 .encoder_types = {
1051 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
1052 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1053 },
1054 };
1055
1056 static const struct of_device_id vc4_crtc_dt_match[] = {
1057 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
1058 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
1059 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
1060 {}
1061 };
1062
vc4_set_crtc_possible_masks(struct drm_device * drm,struct drm_crtc * crtc)1063 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1064 struct drm_crtc *crtc)
1065 {
1066 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1067 const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
1068 const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
1069 struct drm_encoder *encoder;
1070
1071 drm_for_each_encoder(encoder, drm) {
1072 struct vc4_encoder *vc4_encoder;
1073 int i;
1074
1075 /* HVS FIFO2 can feed the TXP IP. */
1076 if (crtc_data->hvs_channel == 2 &&
1077 encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
1078 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1079 continue;
1080 }
1081
1082 vc4_encoder = to_vc4_encoder(encoder);
1083 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
1084 if (vc4_encoder->type == encoder_types[i]) {
1085 vc4_encoder->clock_select = i;
1086 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1087 break;
1088 }
1089 }
1090 }
1091 }
1092
1093 static void
vc4_crtc_get_cob_allocation(struct vc4_crtc * vc4_crtc)1094 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
1095 {
1096 struct drm_device *drm = vc4_crtc->base.dev;
1097 struct vc4_dev *vc4 = to_vc4_dev(drm);
1098 u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
1099 /* Top/base are supposed to be 4-pixel aligned, but the
1100 * Raspberry Pi firmware fills the low bits (which are
1101 * presumably ignored).
1102 */
1103 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
1104 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
1105
1106 vc4_crtc->cob_size = top - base + 4;
1107 }
1108
vc4_crtc_bind(struct device * dev,struct device * master,void * data)1109 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1110 {
1111 struct platform_device *pdev = to_platform_device(dev);
1112 struct drm_device *drm = dev_get_drvdata(master);
1113 struct vc4_crtc *vc4_crtc;
1114 struct drm_crtc *crtc;
1115 struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
1116 const struct of_device_id *match;
1117 int ret, i;
1118
1119 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1120 if (!vc4_crtc)
1121 return -ENOMEM;
1122 crtc = &vc4_crtc->base;
1123
1124 match = of_match_device(vc4_crtc_dt_match, dev);
1125 if (!match)
1126 return -ENODEV;
1127 vc4_crtc->data = match->data;
1128
1129 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1130 if (IS_ERR(vc4_crtc->regs))
1131 return PTR_ERR(vc4_crtc->regs);
1132
1133 /* For now, we create just the primary and the legacy cursor
1134 * planes. We should be able to stack more planes on easily,
1135 * but to do that we would need to compute the bandwidth
1136 * requirement of the plane configuration, and reject ones
1137 * that will take too much.
1138 */
1139 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1140 if (IS_ERR(primary_plane)) {
1141 dev_err(dev, "failed to construct primary plane\n");
1142 ret = PTR_ERR(primary_plane);
1143 goto err;
1144 }
1145
1146 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1147 &vc4_crtc_funcs, NULL);
1148 drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
1149 vc4_crtc->channel = vc4_crtc->data->hvs_channel;
1150 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1151 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1152
1153 /* We support CTM, but only for one CRTC at a time. It's therefore
1154 * implemented as private driver state in vc4_kms, not here.
1155 */
1156 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1157
1158 /* Set up some arbitrary number of planes. We're not limited
1159 * by a set number of physical registers, just the space in
1160 * the HVS (16k) and how small an plane can be (28 bytes).
1161 * However, each plane we set up takes up some memory, and
1162 * increases the cost of looping over planes, which atomic
1163 * modesetting does quite a bit. As a result, we pick a
1164 * modest number of planes to expose, that should hopefully
1165 * still cover any sane usecase.
1166 */
1167 for (i = 0; i < 8; i++) {
1168 struct drm_plane *plane =
1169 vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1170
1171 if (IS_ERR(plane))
1172 continue;
1173
1174 plane->possible_crtcs = drm_crtc_mask(crtc);
1175 }
1176
1177 /* Set up the legacy cursor after overlay initialization,
1178 * since we overlay planes on the CRTC in the order they were
1179 * initialized.
1180 */
1181 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1182 if (!IS_ERR(cursor_plane)) {
1183 cursor_plane->possible_crtcs = drm_crtc_mask(crtc);
1184 crtc->cursor = cursor_plane;
1185 }
1186
1187 vc4_crtc_get_cob_allocation(vc4_crtc);
1188
1189 CRTC_WRITE(PV_INTEN, 0);
1190 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1191 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1192 vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1193 if (ret)
1194 goto err_destroy_planes;
1195
1196 vc4_set_crtc_possible_masks(drm, crtc);
1197
1198 for (i = 0; i < crtc->gamma_size; i++) {
1199 vc4_crtc->lut_r[i] = i;
1200 vc4_crtc->lut_g[i] = i;
1201 vc4_crtc->lut_b[i] = i;
1202 }
1203
1204 platform_set_drvdata(pdev, vc4_crtc);
1205
1206 return 0;
1207
1208 err_destroy_planes:
1209 list_for_each_entry_safe(destroy_plane, temp,
1210 &drm->mode_config.plane_list, head) {
1211 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1212 destroy_plane->funcs->destroy(destroy_plane);
1213 }
1214 err:
1215 return ret;
1216 }
1217
vc4_crtc_unbind(struct device * dev,struct device * master,void * data)1218 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1219 void *data)
1220 {
1221 struct platform_device *pdev = to_platform_device(dev);
1222 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1223
1224 vc4_crtc_destroy(&vc4_crtc->base);
1225
1226 CRTC_WRITE(PV_INTEN, 0);
1227
1228 platform_set_drvdata(pdev, NULL);
1229 }
1230
1231 static const struct component_ops vc4_crtc_ops = {
1232 .bind = vc4_crtc_bind,
1233 .unbind = vc4_crtc_unbind,
1234 };
1235
vc4_crtc_dev_probe(struct platform_device * pdev)1236 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1237 {
1238 return component_add(&pdev->dev, &vc4_crtc_ops);
1239 }
1240
vc4_crtc_dev_remove(struct platform_device * pdev)1241 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1242 {
1243 component_del(&pdev->dev, &vc4_crtc_ops);
1244 return 0;
1245 }
1246
1247 struct platform_driver vc4_crtc_driver = {
1248 .probe = vc4_crtc_dev_probe,
1249 .remove = vc4_crtc_dev_remove,
1250 .driver = {
1251 .name = "vc4_crtc",
1252 .of_match_table = vc4_crtc_dt_match,
1253 },
1254 };
1255
