1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v11_0.h"
29 #include "smu11_driver_if_vangogh.h"
30 #include "vangogh_ppt.h"
31 #include "smu_v11_5_ppsmc.h"
32 #include "smu_v11_5_pmfw.h"
33 #include "smu_cmn.h"
34 #include "soc15_common.h"
35 #include "asic_reg/gc/gc_10_3_0_offset.h"
36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h"
37 #include <asm/processor.h>
38
39 /*
40 * DO NOT use these for err/warn/info/debug messages.
41 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
42 * They are more MGPU friendly.
43 */
44 #undef pr_err
45 #undef pr_warn
46 #undef pr_info
47 #undef pr_debug
48
49 #define FEATURE_MASK(feature) (1ULL << feature)
50 #define SMC_DPM_FEATURE ( \
51 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
52 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
53 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
54 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
55 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
56 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
57 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
58 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
59 FEATURE_MASK(FEATURE_GFX_DPM_BIT))
60
61 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
62 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
63 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0),
64 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0),
65 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0),
66 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
67 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
68 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0),
69 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0),
70 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
71 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
72 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0),
73 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0),
74 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0),
75 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0),
76 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0),
77 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0),
78 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
79 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
80 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
81 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
82 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0),
83 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0),
84 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0),
85 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0),
86 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0),
87 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0),
88 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0),
89 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0),
90 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0),
91 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0),
92 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0),
93 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0),
94 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0),
95 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0),
96 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
97 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
98 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0),
99 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0),
100 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0),
101 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0),
102 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
103 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0),
104 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0),
105 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0),
106 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0),
107 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0),
108 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0),
109 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0),
110 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0),
111 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0),
112 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0),
113 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0),
114 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0),
115 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0),
116 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0),
117 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0),
118 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0),
119 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0),
120 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0),
121 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0),
122 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0),
123 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0),
124 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0),
125 MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0),
126 MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0),
127 MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0),
128 MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0),
129 };
130
131 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
132 FEA_MAP(PPT),
133 FEA_MAP(TDC),
134 FEA_MAP(THERMAL),
135 FEA_MAP(DS_GFXCLK),
136 FEA_MAP(DS_SOCCLK),
137 FEA_MAP(DS_LCLK),
138 FEA_MAP(DS_FCLK),
139 FEA_MAP(DS_MP1CLK),
140 FEA_MAP(DS_MP0CLK),
141 FEA_MAP(ATHUB_PG),
142 FEA_MAP(CCLK_DPM),
143 FEA_MAP(FAN_CONTROLLER),
144 FEA_MAP(ULV),
145 FEA_MAP(VCN_DPM),
146 FEA_MAP(LCLK_DPM),
147 FEA_MAP(SHUBCLK_DPM),
148 FEA_MAP(DCFCLK_DPM),
149 FEA_MAP(DS_DCFCLK),
150 FEA_MAP(S0I2),
151 FEA_MAP(SMU_LOW_POWER),
152 FEA_MAP(GFX_DEM),
153 FEA_MAP(PSI),
154 FEA_MAP(PROCHOT),
155 FEA_MAP(CPUOFF),
156 FEA_MAP(STAPM),
157 FEA_MAP(S0I3),
158 FEA_MAP(DF_CSTATES),
159 FEA_MAP(PERF_LIMIT),
160 FEA_MAP(CORE_DLDO),
161 FEA_MAP(RSMU_LOW_POWER),
162 FEA_MAP(SMN_LOW_POWER),
163 FEA_MAP(THM_LOW_POWER),
164 FEA_MAP(SMUIO_LOW_POWER),
165 FEA_MAP(MP1_LOW_POWER),
166 FEA_MAP(DS_VCN),
167 FEA_MAP(CPPC),
168 FEA_MAP(OS_CSTATES),
169 FEA_MAP(ISP_DPM),
170 FEA_MAP(A55_DPM),
171 FEA_MAP(CVIP_DSP_DPM),
172 FEA_MAP(MSMU_LOW_POWER),
173 FEA_MAP_REVERSE(SOCCLK),
174 FEA_MAP_REVERSE(FCLK),
175 FEA_MAP_HALF_REVERSE(GFX),
176 };
177
178 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = {
179 TAB_MAP_VALID(WATERMARKS),
180 TAB_MAP_VALID(SMU_METRICS),
181 TAB_MAP_VALID(CUSTOM_DPM),
182 TAB_MAP_VALID(DPMCLOCKS),
183 };
184
185 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
186 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
187 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
188 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
189 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
190 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
191 };
192
193 static const uint8_t vangogh_throttler_map[] = {
194 [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
195 [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
196 [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
197 [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
198 [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
199 [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT),
200 [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT),
201 [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT),
202 [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT),
203 [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT),
204 [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT),
205 };
206
vangogh_tables_init(struct smu_context * smu)207 static int vangogh_tables_init(struct smu_context *smu)
208 {
209 struct smu_table_context *smu_table = &smu->smu_table;
210 struct smu_table *tables = smu_table->tables;
211 struct amdgpu_device *adev = smu->adev;
212 uint32_t if_version;
213 uint32_t ret = 0;
214
215 ret = smu_cmn_get_smc_version(smu, &if_version, NULL);
216 if (ret) {
217 dev_err(adev->dev, "Failed to get smu if version!\n");
218 goto err0_out;
219 }
220
221 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
222 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
223 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
224 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
225 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
226 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
227 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t),
228 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
229
230 if (if_version < 0x3) {
231 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_legacy_t),
232 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
233 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_legacy_t), GFP_KERNEL);
234 } else {
235 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
236 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
237 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
238 }
239 if (!smu_table->metrics_table)
240 goto err0_out;
241 smu_table->metrics_time = 0;
242
243 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
244 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
245 if (!smu_table->gpu_metrics_table)
246 goto err1_out;
247
248 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
249 if (!smu_table->watermarks_table)
250 goto err2_out;
251
252 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
253 if (!smu_table->clocks_table)
254 goto err3_out;
255
256 return 0;
257
258 err3_out:
259 kfree(smu_table->watermarks_table);
260 err2_out:
261 kfree(smu_table->gpu_metrics_table);
262 err1_out:
263 kfree(smu_table->metrics_table);
264 err0_out:
265 return -ENOMEM;
266 }
267
vangogh_get_legacy_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)268 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu,
269 MetricsMember_t member,
270 uint32_t *value)
271 {
272 struct smu_table_context *smu_table = &smu->smu_table;
273 SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table;
274 int ret = 0;
275
276 mutex_lock(&smu->metrics_lock);
277
278 ret = smu_cmn_get_metrics_table_locked(smu,
279 NULL,
280 false);
281 if (ret) {
282 mutex_unlock(&smu->metrics_lock);
283 return ret;
284 }
285
286 switch (member) {
287 case METRICS_CURR_GFXCLK:
288 *value = metrics->GfxclkFrequency;
289 break;
290 case METRICS_AVERAGE_SOCCLK:
291 *value = metrics->SocclkFrequency;
292 break;
293 case METRICS_AVERAGE_VCLK:
294 *value = metrics->VclkFrequency;
295 break;
296 case METRICS_AVERAGE_DCLK:
297 *value = metrics->DclkFrequency;
298 break;
299 case METRICS_CURR_UCLK:
300 *value = metrics->MemclkFrequency;
301 break;
302 case METRICS_AVERAGE_GFXACTIVITY:
303 *value = metrics->GfxActivity / 100;
304 break;
305 case METRICS_AVERAGE_VCNACTIVITY:
306 *value = metrics->UvdActivity;
307 break;
308 case METRICS_AVERAGE_SOCKETPOWER:
309 *value = (metrics->CurrentSocketPower << 8) /
310 1000 ;
311 break;
312 case METRICS_TEMPERATURE_EDGE:
313 *value = metrics->GfxTemperature / 100 *
314 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
315 break;
316 case METRICS_TEMPERATURE_HOTSPOT:
317 *value = metrics->SocTemperature / 100 *
318 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
319 break;
320 case METRICS_THROTTLER_STATUS:
321 *value = metrics->ThrottlerStatus;
322 break;
323 case METRICS_VOLTAGE_VDDGFX:
324 *value = metrics->Voltage[2];
325 break;
326 case METRICS_VOLTAGE_VDDSOC:
327 *value = metrics->Voltage[1];
328 break;
329 case METRICS_AVERAGE_CPUCLK:
330 memcpy(value, &metrics->CoreFrequency[0],
331 smu->cpu_core_num * sizeof(uint16_t));
332 break;
333 default:
334 *value = UINT_MAX;
335 break;
336 }
337
338 mutex_unlock(&smu->metrics_lock);
339
340 return ret;
341 }
342
vangogh_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)343 static int vangogh_get_smu_metrics_data(struct smu_context *smu,
344 MetricsMember_t member,
345 uint32_t *value)
346 {
347 struct smu_table_context *smu_table = &smu->smu_table;
348 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
349 int ret = 0;
350
351 mutex_lock(&smu->metrics_lock);
352
353 ret = smu_cmn_get_metrics_table_locked(smu,
354 NULL,
355 false);
356 if (ret) {
357 mutex_unlock(&smu->metrics_lock);
358 return ret;
359 }
360
361 switch (member) {
362 case METRICS_CURR_GFXCLK:
363 *value = metrics->Current.GfxclkFrequency;
364 break;
365 case METRICS_AVERAGE_SOCCLK:
366 *value = metrics->Current.SocclkFrequency;
367 break;
368 case METRICS_AVERAGE_VCLK:
369 *value = metrics->Current.VclkFrequency;
370 break;
371 case METRICS_AVERAGE_DCLK:
372 *value = metrics->Current.DclkFrequency;
373 break;
374 case METRICS_CURR_UCLK:
375 *value = metrics->Current.MemclkFrequency;
376 break;
377 case METRICS_AVERAGE_GFXACTIVITY:
378 *value = metrics->Current.GfxActivity;
379 break;
380 case METRICS_AVERAGE_VCNACTIVITY:
381 *value = metrics->Current.UvdActivity;
382 break;
383 case METRICS_AVERAGE_SOCKETPOWER:
384 *value = (metrics->Current.CurrentSocketPower << 8) /
385 1000;
386 break;
387 case METRICS_TEMPERATURE_EDGE:
388 *value = metrics->Current.GfxTemperature / 100 *
389 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
390 break;
391 case METRICS_TEMPERATURE_HOTSPOT:
392 *value = metrics->Current.SocTemperature / 100 *
393 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
394 break;
395 case METRICS_THROTTLER_STATUS:
396 *value = metrics->Current.ThrottlerStatus;
397 break;
398 case METRICS_VOLTAGE_VDDGFX:
399 *value = metrics->Current.Voltage[2];
400 break;
401 case METRICS_VOLTAGE_VDDSOC:
402 *value = metrics->Current.Voltage[1];
403 break;
404 case METRICS_AVERAGE_CPUCLK:
405 memcpy(value, &metrics->Current.CoreFrequency[0],
406 smu->cpu_core_num * sizeof(uint16_t));
407 break;
408 default:
409 *value = UINT_MAX;
410 break;
411 }
412
413 mutex_unlock(&smu->metrics_lock);
414
415 return ret;
416 }
417
vangogh_common_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)418 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu,
419 MetricsMember_t member,
420 uint32_t *value)
421 {
422 struct amdgpu_device *adev = smu->adev;
423 uint32_t if_version;
424 int ret = 0;
425
426 ret = smu_cmn_get_smc_version(smu, &if_version, NULL);
427 if (ret) {
428 dev_err(adev->dev, "Failed to get smu if version!\n");
429 return ret;
430 }
431
432 if (if_version < 0x3)
433 ret = vangogh_get_legacy_smu_metrics_data(smu, member, value);
434 else
435 ret = vangogh_get_smu_metrics_data(smu, member, value);
436
437 return ret;
438 }
439
vangogh_allocate_dpm_context(struct smu_context * smu)440 static int vangogh_allocate_dpm_context(struct smu_context *smu)
441 {
442 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
443
444 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
445 GFP_KERNEL);
446 if (!smu_dpm->dpm_context)
447 return -ENOMEM;
448
449 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
450
451 return 0;
452 }
453
vangogh_init_smc_tables(struct smu_context * smu)454 static int vangogh_init_smc_tables(struct smu_context *smu)
455 {
456 int ret = 0;
457
458 ret = vangogh_tables_init(smu);
459 if (ret)
460 return ret;
461
462 ret = vangogh_allocate_dpm_context(smu);
463 if (ret)
464 return ret;
465
466 #ifdef CONFIG_X86
467 /* AMD x86 APU only */
468 smu->cpu_core_num = boot_cpu_data.x86_max_cores;
469 #else
470 smu->cpu_core_num = 4;
471 #endif
472
473 return smu_v11_0_init_smc_tables(smu);
474 }
475
vangogh_dpm_set_vcn_enable(struct smu_context * smu,bool enable)476 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
477 {
478 int ret = 0;
479
480 if (enable) {
481 /* vcn dpm on is a prerequisite for vcn power gate messages */
482 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
483 if (ret)
484 return ret;
485 } else {
486 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
487 if (ret)
488 return ret;
489 }
490
491 return ret;
492 }
493
vangogh_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)494 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
495 {
496 int ret = 0;
497
498 if (enable) {
499 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
500 if (ret)
501 return ret;
502 } else {
503 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
504 if (ret)
505 return ret;
506 }
507
508 return ret;
509 }
510
vangogh_is_dpm_running(struct smu_context * smu)511 static bool vangogh_is_dpm_running(struct smu_context *smu)
512 {
513 struct amdgpu_device *adev = smu->adev;
514 int ret = 0;
515 uint32_t feature_mask[2];
516 uint64_t feature_enabled;
517
518 /* we need to re-init after suspend so return false */
519 if (adev->in_suspend)
520 return false;
521
522 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
523
524 if (ret)
525 return false;
526
527 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
528 ((uint64_t)feature_mask[1] << 32));
529
530 return !!(feature_enabled & SMC_DPM_FEATURE);
531 }
532
vangogh_get_dpm_clk_limited(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)533 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
534 uint32_t dpm_level, uint32_t *freq)
535 {
536 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
537
538 if (!clk_table || clk_type >= SMU_CLK_COUNT)
539 return -EINVAL;
540
541 switch (clk_type) {
542 case SMU_SOCCLK:
543 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
544 return -EINVAL;
545 *freq = clk_table->SocClocks[dpm_level];
546 break;
547 case SMU_VCLK:
548 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
549 return -EINVAL;
550 *freq = clk_table->VcnClocks[dpm_level].vclk;
551 break;
552 case SMU_DCLK:
553 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
554 return -EINVAL;
555 *freq = clk_table->VcnClocks[dpm_level].dclk;
556 break;
557 case SMU_UCLK:
558 case SMU_MCLK:
559 if (dpm_level >= clk_table->NumDfPstatesEnabled)
560 return -EINVAL;
561 *freq = clk_table->DfPstateTable[dpm_level].memclk;
562
563 break;
564 case SMU_FCLK:
565 if (dpm_level >= clk_table->NumDfPstatesEnabled)
566 return -EINVAL;
567 *freq = clk_table->DfPstateTable[dpm_level].fclk;
568 break;
569 default:
570 return -EINVAL;
571 }
572
573 return 0;
574 }
575
vangogh_print_legacy_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)576 static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
577 enum smu_clk_type clk_type, char *buf)
578 {
579 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
580 SmuMetrics_legacy_t metrics;
581 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
582 int i, size = 0, ret = 0;
583 uint32_t cur_value = 0, value = 0, count = 0;
584 bool cur_value_match_level = false;
585
586 memset(&metrics, 0, sizeof(metrics));
587
588 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
589 if (ret)
590 return ret;
591
592 smu_cmn_get_sysfs_buf(&buf, &size);
593
594 switch (clk_type) {
595 case SMU_OD_SCLK:
596 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
597 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
598 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
599 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
600 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
601 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
602 }
603 break;
604 case SMU_OD_CCLK:
605 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
606 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
607 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
608 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
609 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
610 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
611 }
612 break;
613 case SMU_OD_RANGE:
614 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
615 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
616 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
617 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
618 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
619 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
620 }
621 break;
622 case SMU_SOCCLK:
623 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
624 count = clk_table->NumSocClkLevelsEnabled;
625 cur_value = metrics.SocclkFrequency;
626 break;
627 case SMU_VCLK:
628 count = clk_table->VcnClkLevelsEnabled;
629 cur_value = metrics.VclkFrequency;
630 break;
631 case SMU_DCLK:
632 count = clk_table->VcnClkLevelsEnabled;
633 cur_value = metrics.DclkFrequency;
634 break;
635 case SMU_MCLK:
636 count = clk_table->NumDfPstatesEnabled;
637 cur_value = metrics.MemclkFrequency;
638 break;
639 case SMU_FCLK:
640 count = clk_table->NumDfPstatesEnabled;
641 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
642 if (ret)
643 return ret;
644 break;
645 default:
646 break;
647 }
648
649 switch (clk_type) {
650 case SMU_SOCCLK:
651 case SMU_VCLK:
652 case SMU_DCLK:
653 case SMU_MCLK:
654 case SMU_FCLK:
655 for (i = 0; i < count; i++) {
656 ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value);
657 if (ret)
658 return ret;
659 if (!value)
660 continue;
661 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
662 cur_value == value ? "*" : "");
663 if (cur_value == value)
664 cur_value_match_level = true;
665 }
666
667 if (!cur_value_match_level)
668 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
669 break;
670 default:
671 break;
672 }
673
674 return size;
675 }
676
vangogh_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)677 static int vangogh_print_clk_levels(struct smu_context *smu,
678 enum smu_clk_type clk_type, char *buf)
679 {
680 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
681 SmuMetrics_t metrics;
682 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
683 int i, size = 0, ret = 0;
684 uint32_t cur_value = 0, value = 0, count = 0;
685 bool cur_value_match_level = false;
686
687 memset(&metrics, 0, sizeof(metrics));
688
689 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
690 if (ret)
691 return ret;
692
693 smu_cmn_get_sysfs_buf(&buf, &size);
694
695 switch (clk_type) {
696 case SMU_OD_SCLK:
697 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
698 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
699 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
700 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
701 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
702 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
703 }
704 break;
705 case SMU_OD_CCLK:
706 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
707 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
708 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
709 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
710 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
711 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
712 }
713 break;
714 case SMU_OD_RANGE:
715 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
716 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
717 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
718 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
719 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
720 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
721 }
722 break;
723 case SMU_SOCCLK:
724 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
725 count = clk_table->NumSocClkLevelsEnabled;
726 cur_value = metrics.Current.SocclkFrequency;
727 break;
728 case SMU_VCLK:
729 count = clk_table->VcnClkLevelsEnabled;
730 cur_value = metrics.Current.VclkFrequency;
731 break;
732 case SMU_DCLK:
733 count = clk_table->VcnClkLevelsEnabled;
734 cur_value = metrics.Current.DclkFrequency;
735 break;
736 case SMU_MCLK:
737 count = clk_table->NumDfPstatesEnabled;
738 cur_value = metrics.Current.MemclkFrequency;
739 break;
740 case SMU_FCLK:
741 count = clk_table->NumDfPstatesEnabled;
742 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
743 if (ret)
744 return ret;
745 break;
746 default:
747 break;
748 }
749
750 switch (clk_type) {
751 case SMU_SOCCLK:
752 case SMU_VCLK:
753 case SMU_DCLK:
754 case SMU_MCLK:
755 case SMU_FCLK:
756 for (i = 0; i < count; i++) {
757 ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value);
758 if (ret)
759 return ret;
760 if (!value)
761 continue;
762 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
763 cur_value == value ? "*" : "");
764 if (cur_value == value)
765 cur_value_match_level = true;
766 }
767
768 if (!cur_value_match_level)
769 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
770 break;
771 default:
772 break;
773 }
774
775 return size;
776 }
777
vangogh_common_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)778 static int vangogh_common_print_clk_levels(struct smu_context *smu,
779 enum smu_clk_type clk_type, char *buf)
780 {
781 struct amdgpu_device *adev = smu->adev;
782 uint32_t if_version;
783 int ret = 0;
784
785 ret = smu_cmn_get_smc_version(smu, &if_version, NULL);
786 if (ret) {
787 dev_err(adev->dev, "Failed to get smu if version!\n");
788 return ret;
789 }
790
791 if (if_version < 0x3)
792 ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf);
793 else
794 ret = vangogh_print_clk_levels(smu, clk_type, buf);
795
796 return ret;
797 }
798
vangogh_get_profiling_clk_mask(struct smu_context * smu,enum amd_dpm_forced_level level,uint32_t * vclk_mask,uint32_t * dclk_mask,uint32_t * mclk_mask,uint32_t * fclk_mask,uint32_t * soc_mask)799 static int vangogh_get_profiling_clk_mask(struct smu_context *smu,
800 enum amd_dpm_forced_level level,
801 uint32_t *vclk_mask,
802 uint32_t *dclk_mask,
803 uint32_t *mclk_mask,
804 uint32_t *fclk_mask,
805 uint32_t *soc_mask)
806 {
807 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
808
809 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
810 if (mclk_mask)
811 *mclk_mask = clk_table->NumDfPstatesEnabled - 1;
812
813 if (fclk_mask)
814 *fclk_mask = clk_table->NumDfPstatesEnabled - 1;
815
816 if (soc_mask)
817 *soc_mask = 0;
818 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
819 if (mclk_mask)
820 *mclk_mask = 0;
821
822 if (fclk_mask)
823 *fclk_mask = 0;
824
825 if (soc_mask)
826 *soc_mask = 1;
827
828 if (vclk_mask)
829 *vclk_mask = 1;
830
831 if (dclk_mask)
832 *dclk_mask = 1;
833 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) {
834 if (mclk_mask)
835 *mclk_mask = 0;
836
837 if (fclk_mask)
838 *fclk_mask = 0;
839
840 if (soc_mask)
841 *soc_mask = 1;
842
843 if (vclk_mask)
844 *vclk_mask = 1;
845
846 if (dclk_mask)
847 *dclk_mask = 1;
848 }
849
850 return 0;
851 }
852
vangogh_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)853 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
854 enum smu_clk_type clk_type)
855 {
856 enum smu_feature_mask feature_id = 0;
857
858 switch (clk_type) {
859 case SMU_MCLK:
860 case SMU_UCLK:
861 case SMU_FCLK:
862 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
863 break;
864 case SMU_GFXCLK:
865 case SMU_SCLK:
866 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
867 break;
868 case SMU_SOCCLK:
869 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
870 break;
871 case SMU_VCLK:
872 case SMU_DCLK:
873 feature_id = SMU_FEATURE_VCN_DPM_BIT;
874 break;
875 default:
876 return true;
877 }
878
879 if (!smu_cmn_feature_is_enabled(smu, feature_id))
880 return false;
881
882 return true;
883 }
884
vangogh_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)885 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu,
886 enum smu_clk_type clk_type,
887 uint32_t *min,
888 uint32_t *max)
889 {
890 int ret = 0;
891 uint32_t soc_mask;
892 uint32_t vclk_mask;
893 uint32_t dclk_mask;
894 uint32_t mclk_mask;
895 uint32_t fclk_mask;
896 uint32_t clock_limit;
897
898 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) {
899 switch (clk_type) {
900 case SMU_MCLK:
901 case SMU_UCLK:
902 clock_limit = smu->smu_table.boot_values.uclk;
903 break;
904 case SMU_FCLK:
905 clock_limit = smu->smu_table.boot_values.fclk;
906 break;
907 case SMU_GFXCLK:
908 case SMU_SCLK:
909 clock_limit = smu->smu_table.boot_values.gfxclk;
910 break;
911 case SMU_SOCCLK:
912 clock_limit = smu->smu_table.boot_values.socclk;
913 break;
914 case SMU_VCLK:
915 clock_limit = smu->smu_table.boot_values.vclk;
916 break;
917 case SMU_DCLK:
918 clock_limit = smu->smu_table.boot_values.dclk;
919 break;
920 default:
921 clock_limit = 0;
922 break;
923 }
924
925 /* clock in Mhz unit */
926 if (min)
927 *min = clock_limit / 100;
928 if (max)
929 *max = clock_limit / 100;
930
931 return 0;
932 }
933 if (max) {
934 ret = vangogh_get_profiling_clk_mask(smu,
935 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
936 &vclk_mask,
937 &dclk_mask,
938 &mclk_mask,
939 &fclk_mask,
940 &soc_mask);
941 if (ret)
942 goto failed;
943
944 switch (clk_type) {
945 case SMU_UCLK:
946 case SMU_MCLK:
947 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
948 if (ret)
949 goto failed;
950 break;
951 case SMU_SOCCLK:
952 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
953 if (ret)
954 goto failed;
955 break;
956 case SMU_FCLK:
957 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max);
958 if (ret)
959 goto failed;
960 break;
961 case SMU_VCLK:
962 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max);
963 if (ret)
964 goto failed;
965 break;
966 case SMU_DCLK:
967 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max);
968 if (ret)
969 goto failed;
970 break;
971 default:
972 ret = -EINVAL;
973 goto failed;
974 }
975 }
976 if (min) {
977 switch (clk_type) {
978 case SMU_UCLK:
979 case SMU_MCLK:
980 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min);
981 if (ret)
982 goto failed;
983 break;
984 case SMU_SOCCLK:
985 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min);
986 if (ret)
987 goto failed;
988 break;
989 case SMU_FCLK:
990 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min);
991 if (ret)
992 goto failed;
993 break;
994 case SMU_VCLK:
995 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min);
996 if (ret)
997 goto failed;
998 break;
999 case SMU_DCLK:
1000 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min);
1001 if (ret)
1002 goto failed;
1003 break;
1004 default:
1005 ret = -EINVAL;
1006 goto failed;
1007 }
1008 }
1009 failed:
1010 return ret;
1011 }
1012
vangogh_get_power_profile_mode(struct smu_context * smu,char * buf)1013 static int vangogh_get_power_profile_mode(struct smu_context *smu,
1014 char *buf)
1015 {
1016 static const char *profile_name[] = {
1017 "BOOTUP_DEFAULT",
1018 "3D_FULL_SCREEN",
1019 "POWER_SAVING",
1020 "VIDEO",
1021 "VR",
1022 "COMPUTE",
1023 "CUSTOM"};
1024 uint32_t i, size = 0;
1025 int16_t workload_type = 0;
1026
1027 if (!buf)
1028 return -EINVAL;
1029
1030 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1031 /*
1032 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1033 * Not all profile modes are supported on vangogh.
1034 */
1035 workload_type = smu_cmn_to_asic_specific_index(smu,
1036 CMN2ASIC_MAPPING_WORKLOAD,
1037 i);
1038
1039 if (workload_type < 0)
1040 continue;
1041
1042 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1043 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1044 }
1045
1046 return size;
1047 }
1048
vangogh_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1049 static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1050 {
1051 int workload_type, ret;
1052 uint32_t profile_mode = input[size];
1053
1054 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1055 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1056 return -EINVAL;
1057 }
1058
1059 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
1060 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
1061 return 0;
1062
1063 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1064 workload_type = smu_cmn_to_asic_specific_index(smu,
1065 CMN2ASIC_MAPPING_WORKLOAD,
1066 profile_mode);
1067 if (workload_type < 0) {
1068 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n",
1069 profile_mode);
1070 return -EINVAL;
1071 }
1072
1073 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
1074 1 << workload_type,
1075 NULL);
1076 if (ret) {
1077 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n",
1078 workload_type);
1079 return ret;
1080 }
1081
1082 smu->power_profile_mode = profile_mode;
1083
1084 return 0;
1085 }
1086
vangogh_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1087 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu,
1088 enum smu_clk_type clk_type,
1089 uint32_t min,
1090 uint32_t max)
1091 {
1092 int ret = 0;
1093
1094 if (!vangogh_clk_dpm_is_enabled(smu, clk_type))
1095 return 0;
1096
1097 switch (clk_type) {
1098 case SMU_GFXCLK:
1099 case SMU_SCLK:
1100 ret = smu_cmn_send_smc_msg_with_param(smu,
1101 SMU_MSG_SetHardMinGfxClk,
1102 min, NULL);
1103 if (ret)
1104 return ret;
1105
1106 ret = smu_cmn_send_smc_msg_with_param(smu,
1107 SMU_MSG_SetSoftMaxGfxClk,
1108 max, NULL);
1109 if (ret)
1110 return ret;
1111 break;
1112 case SMU_FCLK:
1113 ret = smu_cmn_send_smc_msg_with_param(smu,
1114 SMU_MSG_SetHardMinFclkByFreq,
1115 min, NULL);
1116 if (ret)
1117 return ret;
1118
1119 ret = smu_cmn_send_smc_msg_with_param(smu,
1120 SMU_MSG_SetSoftMaxFclkByFreq,
1121 max, NULL);
1122 if (ret)
1123 return ret;
1124 break;
1125 case SMU_SOCCLK:
1126 ret = smu_cmn_send_smc_msg_with_param(smu,
1127 SMU_MSG_SetHardMinSocclkByFreq,
1128 min, NULL);
1129 if (ret)
1130 return ret;
1131
1132 ret = smu_cmn_send_smc_msg_with_param(smu,
1133 SMU_MSG_SetSoftMaxSocclkByFreq,
1134 max, NULL);
1135 if (ret)
1136 return ret;
1137 break;
1138 case SMU_VCLK:
1139 ret = smu_cmn_send_smc_msg_with_param(smu,
1140 SMU_MSG_SetHardMinVcn,
1141 min << 16, NULL);
1142 if (ret)
1143 return ret;
1144 ret = smu_cmn_send_smc_msg_with_param(smu,
1145 SMU_MSG_SetSoftMaxVcn,
1146 max << 16, NULL);
1147 if (ret)
1148 return ret;
1149 break;
1150 case SMU_DCLK:
1151 ret = smu_cmn_send_smc_msg_with_param(smu,
1152 SMU_MSG_SetHardMinVcn,
1153 min, NULL);
1154 if (ret)
1155 return ret;
1156 ret = smu_cmn_send_smc_msg_with_param(smu,
1157 SMU_MSG_SetSoftMaxVcn,
1158 max, NULL);
1159 if (ret)
1160 return ret;
1161 break;
1162 default:
1163 return -EINVAL;
1164 }
1165
1166 return ret;
1167 }
1168
vangogh_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1169 static int vangogh_force_clk_levels(struct smu_context *smu,
1170 enum smu_clk_type clk_type, uint32_t mask)
1171 {
1172 uint32_t soft_min_level = 0, soft_max_level = 0;
1173 uint32_t min_freq = 0, max_freq = 0;
1174 int ret = 0 ;
1175
1176 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1177 soft_max_level = mask ? (fls(mask) - 1) : 0;
1178
1179 switch (clk_type) {
1180 case SMU_SOCCLK:
1181 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1182 soft_min_level, &min_freq);
1183 if (ret)
1184 return ret;
1185 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1186 soft_max_level, &max_freq);
1187 if (ret)
1188 return ret;
1189 ret = smu_cmn_send_smc_msg_with_param(smu,
1190 SMU_MSG_SetSoftMaxSocclkByFreq,
1191 max_freq, NULL);
1192 if (ret)
1193 return ret;
1194 ret = smu_cmn_send_smc_msg_with_param(smu,
1195 SMU_MSG_SetHardMinSocclkByFreq,
1196 min_freq, NULL);
1197 if (ret)
1198 return ret;
1199 break;
1200 case SMU_FCLK:
1201 ret = vangogh_get_dpm_clk_limited(smu,
1202 clk_type, soft_min_level, &min_freq);
1203 if (ret)
1204 return ret;
1205 ret = vangogh_get_dpm_clk_limited(smu,
1206 clk_type, soft_max_level, &max_freq);
1207 if (ret)
1208 return ret;
1209 ret = smu_cmn_send_smc_msg_with_param(smu,
1210 SMU_MSG_SetSoftMaxFclkByFreq,
1211 max_freq, NULL);
1212 if (ret)
1213 return ret;
1214 ret = smu_cmn_send_smc_msg_with_param(smu,
1215 SMU_MSG_SetHardMinFclkByFreq,
1216 min_freq, NULL);
1217 if (ret)
1218 return ret;
1219 break;
1220 case SMU_VCLK:
1221 ret = vangogh_get_dpm_clk_limited(smu,
1222 clk_type, soft_min_level, &min_freq);
1223 if (ret)
1224 return ret;
1225
1226 ret = vangogh_get_dpm_clk_limited(smu,
1227 clk_type, soft_max_level, &max_freq);
1228 if (ret)
1229 return ret;
1230
1231
1232 ret = smu_cmn_send_smc_msg_with_param(smu,
1233 SMU_MSG_SetHardMinVcn,
1234 min_freq << 16, NULL);
1235 if (ret)
1236 return ret;
1237
1238 ret = smu_cmn_send_smc_msg_with_param(smu,
1239 SMU_MSG_SetSoftMaxVcn,
1240 max_freq << 16, NULL);
1241 if (ret)
1242 return ret;
1243
1244 break;
1245 case SMU_DCLK:
1246 ret = vangogh_get_dpm_clk_limited(smu,
1247 clk_type, soft_min_level, &min_freq);
1248 if (ret)
1249 return ret;
1250
1251 ret = vangogh_get_dpm_clk_limited(smu,
1252 clk_type, soft_max_level, &max_freq);
1253 if (ret)
1254 return ret;
1255
1256 ret = smu_cmn_send_smc_msg_with_param(smu,
1257 SMU_MSG_SetHardMinVcn,
1258 min_freq, NULL);
1259 if (ret)
1260 return ret;
1261
1262 ret = smu_cmn_send_smc_msg_with_param(smu,
1263 SMU_MSG_SetSoftMaxVcn,
1264 max_freq, NULL);
1265 if (ret)
1266 return ret;
1267
1268 break;
1269 default:
1270 break;
1271 }
1272
1273 return ret;
1274 }
1275
vangogh_force_dpm_limit_value(struct smu_context * smu,bool highest)1276 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest)
1277 {
1278 int ret = 0, i = 0;
1279 uint32_t min_freq, max_freq, force_freq;
1280 enum smu_clk_type clk_type;
1281
1282 enum smu_clk_type clks[] = {
1283 SMU_SOCCLK,
1284 SMU_VCLK,
1285 SMU_DCLK,
1286 SMU_FCLK,
1287 };
1288
1289 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1290 clk_type = clks[i];
1291 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1292 if (ret)
1293 return ret;
1294
1295 force_freq = highest ? max_freq : min_freq;
1296 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
1297 if (ret)
1298 return ret;
1299 }
1300
1301 return ret;
1302 }
1303
vangogh_unforce_dpm_levels(struct smu_context * smu)1304 static int vangogh_unforce_dpm_levels(struct smu_context *smu)
1305 {
1306 int ret = 0, i = 0;
1307 uint32_t min_freq, max_freq;
1308 enum smu_clk_type clk_type;
1309
1310 struct clk_feature_map {
1311 enum smu_clk_type clk_type;
1312 uint32_t feature;
1313 } clk_feature_map[] = {
1314 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT},
1315 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
1316 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT},
1317 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT},
1318 };
1319
1320 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
1321
1322 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
1323 continue;
1324
1325 clk_type = clk_feature_map[i].clk_type;
1326
1327 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1328
1329 if (ret)
1330 return ret;
1331
1332 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1333
1334 if (ret)
1335 return ret;
1336 }
1337
1338 return ret;
1339 }
1340
vangogh_set_peak_clock_by_device(struct smu_context * smu)1341 static int vangogh_set_peak_clock_by_device(struct smu_context *smu)
1342 {
1343 int ret = 0;
1344 uint32_t socclk_freq = 0, fclk_freq = 0;
1345 uint32_t vclk_freq = 0, dclk_freq = 0;
1346
1347 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq);
1348 if (ret)
1349 return ret;
1350
1351 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq);
1352 if (ret)
1353 return ret;
1354
1355 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq);
1356 if (ret)
1357 return ret;
1358
1359 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq);
1360 if (ret)
1361 return ret;
1362
1363 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq);
1364 if (ret)
1365 return ret;
1366
1367 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq);
1368 if (ret)
1369 return ret;
1370
1371 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq);
1372 if (ret)
1373 return ret;
1374
1375 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq);
1376 if (ret)
1377 return ret;
1378
1379 return ret;
1380 }
1381
vangogh_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1382 static int vangogh_set_performance_level(struct smu_context *smu,
1383 enum amd_dpm_forced_level level)
1384 {
1385 int ret = 0;
1386 uint32_t soc_mask, mclk_mask, fclk_mask;
1387 uint32_t vclk_mask = 0, dclk_mask = 0;
1388
1389 switch (level) {
1390 case AMD_DPM_FORCED_LEVEL_HIGH:
1391 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1392 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1393
1394 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1395 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1396
1397 ret = vangogh_force_dpm_limit_value(smu, true);
1398 break;
1399 case AMD_DPM_FORCED_LEVEL_LOW:
1400 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1401 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1402
1403 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1404 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1405
1406 ret = vangogh_force_dpm_limit_value(smu, false);
1407 break;
1408 case AMD_DPM_FORCED_LEVEL_AUTO:
1409 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1410 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1411
1412 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1413 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1414
1415 ret = vangogh_unforce_dpm_levels(smu);
1416 break;
1417 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1418 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1419 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1420
1421 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1422 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1423
1424 ret = smu_cmn_send_smc_msg_with_param(smu,
1425 SMU_MSG_SetHardMinGfxClk,
1426 VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL);
1427 if (ret)
1428 return ret;
1429
1430 ret = smu_cmn_send_smc_msg_with_param(smu,
1431 SMU_MSG_SetSoftMaxGfxClk,
1432 VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL);
1433 if (ret)
1434 return ret;
1435
1436 ret = vangogh_get_profiling_clk_mask(smu, level,
1437 &vclk_mask,
1438 &dclk_mask,
1439 &mclk_mask,
1440 &fclk_mask,
1441 &soc_mask);
1442 if (ret)
1443 return ret;
1444
1445 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1446 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1447 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
1448 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask);
1449
1450 break;
1451 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1452 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1453 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1454
1455 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1456 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1457
1458 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn,
1459 VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL);
1460 if (ret)
1461 return ret;
1462
1463 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn,
1464 VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL);
1465 if (ret)
1466 return ret;
1467 break;
1468 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1469 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1470 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1471
1472 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1473 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1474
1475 ret = vangogh_get_profiling_clk_mask(smu, level,
1476 NULL,
1477 NULL,
1478 &mclk_mask,
1479 &fclk_mask,
1480 NULL);
1481 if (ret)
1482 return ret;
1483
1484 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1485 break;
1486 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1487 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1488 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1489
1490 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1491 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1492
1493 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1494 VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL);
1495 if (ret)
1496 return ret;
1497
1498 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1499 VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL);
1500 if (ret)
1501 return ret;
1502
1503 ret = vangogh_set_peak_clock_by_device(smu);
1504 break;
1505 case AMD_DPM_FORCED_LEVEL_MANUAL:
1506 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1507 default:
1508 break;
1509 }
1510 return ret;
1511 }
1512
vangogh_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1513 static int vangogh_read_sensor(struct smu_context *smu,
1514 enum amd_pp_sensors sensor,
1515 void *data, uint32_t *size)
1516 {
1517 int ret = 0;
1518
1519 if (!data || !size)
1520 return -EINVAL;
1521
1522 mutex_lock(&smu->sensor_lock);
1523 switch (sensor) {
1524 case AMDGPU_PP_SENSOR_GPU_LOAD:
1525 ret = vangogh_common_get_smu_metrics_data(smu,
1526 METRICS_AVERAGE_GFXACTIVITY,
1527 (uint32_t *)data);
1528 *size = 4;
1529 break;
1530 case AMDGPU_PP_SENSOR_GPU_POWER:
1531 ret = vangogh_common_get_smu_metrics_data(smu,
1532 METRICS_AVERAGE_SOCKETPOWER,
1533 (uint32_t *)data);
1534 *size = 4;
1535 break;
1536 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1537 ret = vangogh_common_get_smu_metrics_data(smu,
1538 METRICS_TEMPERATURE_EDGE,
1539 (uint32_t *)data);
1540 *size = 4;
1541 break;
1542 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1543 ret = vangogh_common_get_smu_metrics_data(smu,
1544 METRICS_TEMPERATURE_HOTSPOT,
1545 (uint32_t *)data);
1546 *size = 4;
1547 break;
1548 case AMDGPU_PP_SENSOR_GFX_MCLK:
1549 ret = vangogh_common_get_smu_metrics_data(smu,
1550 METRICS_CURR_UCLK,
1551 (uint32_t *)data);
1552 *(uint32_t *)data *= 100;
1553 *size = 4;
1554 break;
1555 case AMDGPU_PP_SENSOR_GFX_SCLK:
1556 ret = vangogh_common_get_smu_metrics_data(smu,
1557 METRICS_CURR_GFXCLK,
1558 (uint32_t *)data);
1559 *(uint32_t *)data *= 100;
1560 *size = 4;
1561 break;
1562 case AMDGPU_PP_SENSOR_VDDGFX:
1563 ret = vangogh_common_get_smu_metrics_data(smu,
1564 METRICS_VOLTAGE_VDDGFX,
1565 (uint32_t *)data);
1566 *size = 4;
1567 break;
1568 case AMDGPU_PP_SENSOR_VDDNB:
1569 ret = vangogh_common_get_smu_metrics_data(smu,
1570 METRICS_VOLTAGE_VDDSOC,
1571 (uint32_t *)data);
1572 *size = 4;
1573 break;
1574 case AMDGPU_PP_SENSOR_CPU_CLK:
1575 ret = vangogh_common_get_smu_metrics_data(smu,
1576 METRICS_AVERAGE_CPUCLK,
1577 (uint32_t *)data);
1578 *size = smu->cpu_core_num * sizeof(uint16_t);
1579 break;
1580 default:
1581 ret = -EOPNOTSUPP;
1582 break;
1583 }
1584 mutex_unlock(&smu->sensor_lock);
1585
1586 return ret;
1587 }
1588
vangogh_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1589 static int vangogh_set_watermarks_table(struct smu_context *smu,
1590 struct pp_smu_wm_range_sets *clock_ranges)
1591 {
1592 int i;
1593 int ret = 0;
1594 Watermarks_t *table = smu->smu_table.watermarks_table;
1595
1596 if (!table || !clock_ranges)
1597 return -EINVAL;
1598
1599 if (clock_ranges) {
1600 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1601 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1602 return -EINVAL;
1603
1604 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1605 table->WatermarkRow[WM_DCFCLK][i].MinClock =
1606 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1607 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1608 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1609 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1610 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1611 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1612 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1613
1614 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1615 clock_ranges->reader_wm_sets[i].wm_inst;
1616 }
1617
1618 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1619 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1620 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1621 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1622 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1623 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1624 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1625 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1626 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1627
1628 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1629 clock_ranges->writer_wm_sets[i].wm_inst;
1630 }
1631
1632 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1633 }
1634
1635 /* pass data to smu controller */
1636 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1637 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1638 ret = smu_cmn_write_watermarks_table(smu);
1639 if (ret) {
1640 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1641 return ret;
1642 }
1643 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1644 }
1645
1646 return 0;
1647 }
1648
vangogh_get_legacy_gpu_metrics(struct smu_context * smu,void ** table)1649 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,
1650 void **table)
1651 {
1652 struct smu_table_context *smu_table = &smu->smu_table;
1653 struct gpu_metrics_v2_2 *gpu_metrics =
1654 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1655 SmuMetrics_legacy_t metrics;
1656 int ret = 0;
1657
1658 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1659 if (ret)
1660 return ret;
1661
1662 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1663
1664 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1665 gpu_metrics->temperature_soc = metrics.SocTemperature;
1666 memcpy(&gpu_metrics->temperature_core[0],
1667 &metrics.CoreTemperature[0],
1668 sizeof(uint16_t) * 4);
1669 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1670
1671 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
1672 gpu_metrics->average_mm_activity = metrics.UvdActivity;
1673
1674 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1675 gpu_metrics->average_cpu_power = metrics.Power[0];
1676 gpu_metrics->average_soc_power = metrics.Power[1];
1677 gpu_metrics->average_gfx_power = metrics.Power[2];
1678 memcpy(&gpu_metrics->average_core_power[0],
1679 &metrics.CorePower[0],
1680 sizeof(uint16_t) * 4);
1681
1682 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
1683 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
1684 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
1685 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
1686 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
1687 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
1688
1689 memcpy(&gpu_metrics->current_coreclk[0],
1690 &metrics.CoreFrequency[0],
1691 sizeof(uint16_t) * 4);
1692 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1693
1694 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1695 gpu_metrics->indep_throttle_status =
1696 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1697 vangogh_throttler_map);
1698
1699 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1700
1701 *table = (void *)gpu_metrics;
1702
1703 return sizeof(struct gpu_metrics_v2_2);
1704 }
1705
vangogh_get_gpu_metrics(struct smu_context * smu,void ** table)1706 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
1707 void **table)
1708 {
1709 struct smu_table_context *smu_table = &smu->smu_table;
1710 struct gpu_metrics_v2_2 *gpu_metrics =
1711 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1712 SmuMetrics_t metrics;
1713 int ret = 0;
1714
1715 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1716 if (ret)
1717 return ret;
1718
1719 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1720
1721 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1722 gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1723 memcpy(&gpu_metrics->temperature_core[0],
1724 &metrics.Current.CoreTemperature[0],
1725 sizeof(uint16_t) * 4);
1726 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1727
1728 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
1729 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1730
1731 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
1732 gpu_metrics->average_cpu_power = metrics.Current.Power[0];
1733 gpu_metrics->average_soc_power = metrics.Current.Power[1];
1734 gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1735 memcpy(&gpu_metrics->average_core_power[0],
1736 &metrics.Average.CorePower[0],
1737 sizeof(uint16_t) * 4);
1738
1739 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1740 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1741 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1742 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1743 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1744 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1745
1746 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1747 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1748 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1749 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1750 gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1751 gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1752
1753 memcpy(&gpu_metrics->current_coreclk[0],
1754 &metrics.Current.CoreFrequency[0],
1755 sizeof(uint16_t) * 4);
1756 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1757
1758 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1759 gpu_metrics->indep_throttle_status =
1760 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1761 vangogh_throttler_map);
1762
1763 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1764
1765 *table = (void *)gpu_metrics;
1766
1767 return sizeof(struct gpu_metrics_v2_2);
1768 }
1769
vangogh_common_get_gpu_metrics(struct smu_context * smu,void ** table)1770 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu,
1771 void **table)
1772 {
1773 struct amdgpu_device *adev = smu->adev;
1774 uint32_t if_version;
1775 int ret = 0;
1776
1777 ret = smu_cmn_get_smc_version(smu, &if_version, NULL);
1778 if (ret) {
1779 dev_err(adev->dev, "Failed to get smu if version!\n");
1780 return ret;
1781 }
1782
1783 if (if_version < 0x3)
1784 ret = vangogh_get_legacy_gpu_metrics(smu, table);
1785 else
1786 ret = vangogh_get_gpu_metrics(smu, table);
1787
1788 return ret;
1789 }
1790
vangogh_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1791 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1792 long input[], uint32_t size)
1793 {
1794 int ret = 0;
1795 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1796
1797 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
1798 dev_warn(smu->adev->dev,
1799 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
1800 return -EINVAL;
1801 }
1802
1803 switch (type) {
1804 case PP_OD_EDIT_CCLK_VDDC_TABLE:
1805 if (size != 3) {
1806 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
1807 return -EINVAL;
1808 }
1809 if (input[0] >= smu->cpu_core_num) {
1810 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
1811 smu->cpu_core_num);
1812 }
1813 smu->cpu_core_id_select = input[0];
1814 if (input[1] == 0) {
1815 if (input[2] < smu->cpu_default_soft_min_freq) {
1816 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1817 input[2], smu->cpu_default_soft_min_freq);
1818 return -EINVAL;
1819 }
1820 smu->cpu_actual_soft_min_freq = input[2];
1821 } else if (input[1] == 1) {
1822 if (input[2] > smu->cpu_default_soft_max_freq) {
1823 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1824 input[2], smu->cpu_default_soft_max_freq);
1825 return -EINVAL;
1826 }
1827 smu->cpu_actual_soft_max_freq = input[2];
1828 } else {
1829 return -EINVAL;
1830 }
1831 break;
1832 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1833 if (size != 2) {
1834 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1835 return -EINVAL;
1836 }
1837
1838 if (input[0] == 0) {
1839 if (input[1] < smu->gfx_default_hard_min_freq) {
1840 dev_warn(smu->adev->dev,
1841 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1842 input[1], smu->gfx_default_hard_min_freq);
1843 return -EINVAL;
1844 }
1845 smu->gfx_actual_hard_min_freq = input[1];
1846 } else if (input[0] == 1) {
1847 if (input[1] > smu->gfx_default_soft_max_freq) {
1848 dev_warn(smu->adev->dev,
1849 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1850 input[1], smu->gfx_default_soft_max_freq);
1851 return -EINVAL;
1852 }
1853 smu->gfx_actual_soft_max_freq = input[1];
1854 } else {
1855 return -EINVAL;
1856 }
1857 break;
1858 case PP_OD_RESTORE_DEFAULT_TABLE:
1859 if (size != 0) {
1860 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1861 return -EINVAL;
1862 } else {
1863 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1864 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1865 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1866 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1867 }
1868 break;
1869 case PP_OD_COMMIT_DPM_TABLE:
1870 if (size != 0) {
1871 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1872 return -EINVAL;
1873 } else {
1874 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
1875 dev_err(smu->adev->dev,
1876 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
1877 smu->gfx_actual_hard_min_freq,
1878 smu->gfx_actual_soft_max_freq);
1879 return -EINVAL;
1880 }
1881
1882 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1883 smu->gfx_actual_hard_min_freq, NULL);
1884 if (ret) {
1885 dev_err(smu->adev->dev, "Set hard min sclk failed!");
1886 return ret;
1887 }
1888
1889 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1890 smu->gfx_actual_soft_max_freq, NULL);
1891 if (ret) {
1892 dev_err(smu->adev->dev, "Set soft max sclk failed!");
1893 return ret;
1894 }
1895
1896 if (smu->adev->pm.fw_version < 0x43f1b00) {
1897 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n");
1898 break;
1899 }
1900
1901 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
1902 ((smu->cpu_core_id_select << 20)
1903 | smu->cpu_actual_soft_min_freq),
1904 NULL);
1905 if (ret) {
1906 dev_err(smu->adev->dev, "Set hard min cclk failed!");
1907 return ret;
1908 }
1909
1910 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
1911 ((smu->cpu_core_id_select << 20)
1912 | smu->cpu_actual_soft_max_freq),
1913 NULL);
1914 if (ret) {
1915 dev_err(smu->adev->dev, "Set soft max cclk failed!");
1916 return ret;
1917 }
1918 }
1919 break;
1920 default:
1921 return -ENOSYS;
1922 }
1923
1924 return ret;
1925 }
1926
vangogh_set_default_dpm_tables(struct smu_context * smu)1927 static int vangogh_set_default_dpm_tables(struct smu_context *smu)
1928 {
1929 struct smu_table_context *smu_table = &smu->smu_table;
1930
1931 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
1932 }
1933
vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)1934 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1935 {
1936 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1937
1938 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1939 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1940 smu->gfx_actual_hard_min_freq = 0;
1941 smu->gfx_actual_soft_max_freq = 0;
1942
1943 smu->cpu_default_soft_min_freq = 1400;
1944 smu->cpu_default_soft_max_freq = 3500;
1945 smu->cpu_actual_soft_min_freq = 0;
1946 smu->cpu_actual_soft_max_freq = 0;
1947
1948 return 0;
1949 }
1950
vangogh_get_dpm_clock_table(struct smu_context * smu,struct dpm_clocks * clock_table)1951 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
1952 {
1953 DpmClocks_t *table = smu->smu_table.clocks_table;
1954 int i;
1955
1956 if (!clock_table || !table)
1957 return -EINVAL;
1958
1959 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
1960 clock_table->SocClocks[i].Freq = table->SocClocks[i];
1961 clock_table->SocClocks[i].Vol = table->SocVoltage[i];
1962 }
1963
1964 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
1965 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk;
1966 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage;
1967 }
1968
1969 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
1970 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk;
1971 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage;
1972 }
1973
1974 return 0;
1975 }
1976
1977
vangogh_system_features_control(struct smu_context * smu,bool en)1978 static int vangogh_system_features_control(struct smu_context *smu, bool en)
1979 {
1980 struct amdgpu_device *adev = smu->adev;
1981 struct smu_feature *feature = &smu->smu_feature;
1982 uint32_t feature_mask[2];
1983 int ret = 0;
1984
1985 if (adev->pm.fw_version >= 0x43f1700 && !en)
1986 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
1987 RLC_STATUS_OFF, NULL);
1988
1989 bitmap_zero(feature->enabled, feature->feature_num);
1990 bitmap_zero(feature->supported, feature->feature_num);
1991
1992 if (!en)
1993 return ret;
1994
1995 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
1996 if (ret)
1997 return ret;
1998
1999 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
2000 feature->feature_num);
2001 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
2002 feature->feature_num);
2003
2004 return 0;
2005 }
2006
vangogh_post_smu_init(struct smu_context * smu)2007 static int vangogh_post_smu_init(struct smu_context *smu)
2008 {
2009 struct amdgpu_device *adev = smu->adev;
2010 uint32_t tmp;
2011 int ret = 0;
2012 uint8_t aon_bits = 0;
2013 /* Two CUs in one WGP */
2014 uint32_t req_active_wgps = adev->gfx.cu_info.number/2;
2015 uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
2016 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2017
2018 /* allow message will be sent after enable message on Vangogh*/
2019 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
2020 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2021 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
2022 if (ret) {
2023 dev_err(adev->dev, "Failed to Enable GfxOff!\n");
2024 return ret;
2025 }
2026 } else {
2027 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2028 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n");
2029 }
2030
2031 /* if all CUs are active, no need to power off any WGPs */
2032 if (total_cu == adev->gfx.cu_info.number)
2033 return 0;
2034
2035 /*
2036 * Calculate the total bits number of always on WGPs for all SA/SEs in
2037 * RLC_PG_ALWAYS_ON_WGP_MASK.
2038 */
2039 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK));
2040 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK;
2041
2042 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2043
2044 /* Do not request any WGPs less than set in the AON_WGP_MASK */
2045 if (aon_bits > req_active_wgps) {
2046 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n");
2047 return 0;
2048 } else {
2049 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL);
2050 }
2051 }
2052
vangogh_mode_reset(struct smu_context * smu,int type)2053 static int vangogh_mode_reset(struct smu_context *smu, int type)
2054 {
2055 int ret = 0, index = 0;
2056
2057 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2058 SMU_MSG_GfxDeviceDriverReset);
2059 if (index < 0)
2060 return index == -EACCES ? 0 : index;
2061
2062 mutex_lock(&smu->message_lock);
2063
2064 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
2065
2066 mutex_unlock(&smu->message_lock);
2067
2068 mdelay(10);
2069
2070 return ret;
2071 }
2072
vangogh_mode2_reset(struct smu_context * smu)2073 static int vangogh_mode2_reset(struct smu_context *smu)
2074 {
2075 return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
2076 }
2077
vangogh_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit)2078 static int vangogh_get_power_limit(struct smu_context *smu,
2079 uint32_t *current_power_limit,
2080 uint32_t *default_power_limit,
2081 uint32_t *max_power_limit)
2082 {
2083 struct smu_11_5_power_context *power_context =
2084 smu->smu_power.power_context;
2085 uint32_t ppt_limit;
2086 int ret = 0;
2087
2088 if (smu->adev->pm.fw_version < 0x43f1e00)
2089 return ret;
2090
2091 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit);
2092 if (ret) {
2093 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n");
2094 return ret;
2095 }
2096 /* convert from milliwatt to watt */
2097 if (current_power_limit)
2098 *current_power_limit = ppt_limit / 1000;
2099 if (default_power_limit)
2100 *default_power_limit = ppt_limit / 1000;
2101 if (max_power_limit)
2102 *max_power_limit = 29;
2103
2104 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit);
2105 if (ret) {
2106 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n");
2107 return ret;
2108 }
2109 /* convert from milliwatt to watt */
2110 power_context->current_fast_ppt_limit =
2111 power_context->default_fast_ppt_limit = ppt_limit / 1000;
2112 power_context->max_fast_ppt_limit = 30;
2113
2114 return ret;
2115 }
2116
vangogh_get_ppt_limit(struct smu_context * smu,uint32_t * ppt_limit,enum smu_ppt_limit_type type,enum smu_ppt_limit_level level)2117 static int vangogh_get_ppt_limit(struct smu_context *smu,
2118 uint32_t *ppt_limit,
2119 enum smu_ppt_limit_type type,
2120 enum smu_ppt_limit_level level)
2121 {
2122 struct smu_11_5_power_context *power_context =
2123 smu->smu_power.power_context;
2124
2125 if (!power_context)
2126 return -EOPNOTSUPP;
2127
2128 if (type == SMU_FAST_PPT_LIMIT) {
2129 switch (level) {
2130 case SMU_PPT_LIMIT_MAX:
2131 *ppt_limit = power_context->max_fast_ppt_limit;
2132 break;
2133 case SMU_PPT_LIMIT_CURRENT:
2134 *ppt_limit = power_context->current_fast_ppt_limit;
2135 break;
2136 case SMU_PPT_LIMIT_DEFAULT:
2137 *ppt_limit = power_context->default_fast_ppt_limit;
2138 break;
2139 default:
2140 break;
2141 }
2142 }
2143
2144 return 0;
2145 }
2146
vangogh_set_power_limit(struct smu_context * smu,uint32_t ppt_limit)2147 static int vangogh_set_power_limit(struct smu_context *smu, uint32_t ppt_limit)
2148 {
2149 struct smu_11_5_power_context *power_context =
2150 smu->smu_power.power_context;
2151 uint32_t limit_type = ppt_limit >> 24;
2152 int ret = 0;
2153
2154 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
2155 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
2156 return -EOPNOTSUPP;
2157 }
2158
2159 switch (limit_type) {
2160 case SMU_DEFAULT_PPT_LIMIT:
2161 ret = smu_cmn_send_smc_msg_with_param(smu,
2162 SMU_MSG_SetSlowPPTLimit,
2163 ppt_limit * 1000, /* convert from watt to milliwatt */
2164 NULL);
2165 if (ret)
2166 return ret;
2167
2168 smu->current_power_limit = ppt_limit;
2169 break;
2170 case SMU_FAST_PPT_LIMIT:
2171 ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24);
2172 if (ppt_limit > power_context->max_fast_ppt_limit) {
2173 dev_err(smu->adev->dev,
2174 "New power limit (%d) is over the max allowed %d\n",
2175 ppt_limit, power_context->max_fast_ppt_limit);
2176 return ret;
2177 }
2178
2179 ret = smu_cmn_send_smc_msg_with_param(smu,
2180 SMU_MSG_SetFastPPTLimit,
2181 ppt_limit * 1000, /* convert from watt to milliwatt */
2182 NULL);
2183 if (ret)
2184 return ret;
2185
2186 power_context->current_fast_ppt_limit = ppt_limit;
2187 break;
2188 default:
2189 return -EINVAL;
2190 }
2191
2192 return ret;
2193 }
2194
2195 static const struct pptable_funcs vangogh_ppt_funcs = {
2196
2197 .check_fw_status = smu_v11_0_check_fw_status,
2198 .check_fw_version = smu_v11_0_check_fw_version,
2199 .init_smc_tables = vangogh_init_smc_tables,
2200 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2201 .init_power = smu_v11_0_init_power,
2202 .fini_power = smu_v11_0_fini_power,
2203 .register_irq_handler = smu_v11_0_register_irq_handler,
2204 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2205 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2206 .send_smc_msg = smu_cmn_send_smc_msg,
2207 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable,
2208 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
2209 .is_dpm_running = vangogh_is_dpm_running,
2210 .read_sensor = vangogh_read_sensor,
2211 .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask,
2212 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2213 .set_watermarks_table = vangogh_set_watermarks_table,
2214 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2215 .interrupt_work = smu_v11_0_interrupt_work,
2216 .get_gpu_metrics = vangogh_common_get_gpu_metrics,
2217 .od_edit_dpm_table = vangogh_od_edit_dpm_table,
2218 .print_clk_levels = vangogh_common_print_clk_levels,
2219 .set_default_dpm_table = vangogh_set_default_dpm_tables,
2220 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,
2221 .system_features_control = vangogh_system_features_control,
2222 .feature_is_enabled = smu_cmn_feature_is_enabled,
2223 .set_power_profile_mode = vangogh_set_power_profile_mode,
2224 .get_power_profile_mode = vangogh_get_power_profile_mode,
2225 .get_dpm_clock_table = vangogh_get_dpm_clock_table,
2226 .force_clk_levels = vangogh_force_clk_levels,
2227 .set_performance_level = vangogh_set_performance_level,
2228 .post_init = vangogh_post_smu_init,
2229 .mode2_reset = vangogh_mode2_reset,
2230 .gfx_off_control = smu_v11_0_gfx_off_control,
2231 .get_ppt_limit = vangogh_get_ppt_limit,
2232 .get_power_limit = vangogh_get_power_limit,
2233 .set_power_limit = vangogh_set_power_limit,
2234 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2235 };
2236
vangogh_set_ppt_funcs(struct smu_context * smu)2237 void vangogh_set_ppt_funcs(struct smu_context *smu)
2238 {
2239 smu->ppt_funcs = &vangogh_ppt_funcs;
2240 smu->message_map = vangogh_message_map;
2241 smu->feature_map = vangogh_feature_mask_map;
2242 smu->table_map = vangogh_table_map;
2243 smu->workload_map = vangogh_workload_map;
2244 smu->is_apu = true;
2245 }
2246
