1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_TIMING_GENERATOR_DCN10_H__ 27 #define __DC_TIMING_GENERATOR_DCN10_H__ 28 29 #include "timing_generator.h" 30 31 #define DCN10TG_FROM_TG(tg)\ 32 container_of(tg, struct optc, base) 33 34 #define TG_COMMON_REG_LIST_DCN(inst) \ 35 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\ 36 SRI(OTG_VUPDATE_PARAM, OTG, inst),\ 37 SRI(OTG_VREADY_PARAM, OTG, inst),\ 38 SRI(OTG_BLANK_CONTROL, OTG, inst),\ 39 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\ 40 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\ 41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\ 42 SRI(OTG_H_TOTAL, OTG, inst),\ 43 SRI(OTG_H_BLANK_START_END, OTG, inst),\ 44 SRI(OTG_H_SYNC_A, OTG, inst),\ 45 SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\ 46 SRI(OTG_H_TIMING_CNTL, OTG, inst),\ 47 SRI(OTG_V_TOTAL, OTG, inst),\ 48 SRI(OTG_V_BLANK_START_END, OTG, inst),\ 49 SRI(OTG_V_SYNC_A, OTG, inst),\ 50 SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\ 51 SRI(OTG_INTERLACE_CONTROL, OTG, inst),\ 52 SRI(OTG_CONTROL, OTG, inst),\ 53 SRI(OTG_STEREO_CONTROL, OTG, inst),\ 54 SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\ 55 SRI(OTG_STEREO_STATUS, OTG, inst),\ 56 SRI(OTG_V_TOTAL_MAX, OTG, inst),\ 57 SRI(OTG_V_TOTAL_MIN, OTG, inst),\ 58 SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\ 59 SRI(OTG_TRIGA_CNTL, OTG, inst),\ 60 SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\ 61 SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\ 62 SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\ 63 SRI(OTG_STATUS, OTG, inst),\ 64 SRI(OTG_STATUS_POSITION, OTG, inst),\ 65 SRI(OTG_NOM_VERT_POSITION, OTG, inst),\ 66 SRI(OTG_BLACK_COLOR, OTG, inst),\ 67 SRI(OTG_CLOCK_CONTROL, OTG, inst),\ 68 SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\ 69 SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\ 70 SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\ 71 SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\ 72 SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\ 73 SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\ 74 SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ 75 SRI(CONTROL, VTG, inst),\ 76 SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ 77 SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\ 78 SRI(OTG_GSL_CONTROL, OTG, inst),\ 79 SRI(OTG_CRC_CNTL, OTG, inst),\ 80 SRI(OTG_CRC0_DATA_RG, OTG, inst),\ 81 SRI(OTG_CRC0_DATA_B, OTG, inst),\ 82 SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\ 83 SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\ 84 SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\ 85 SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst) 86 87 #define TG_COMMON_REG_LIST_DCN1_0(inst) \ 88 TG_COMMON_REG_LIST_DCN(inst),\ 89 SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\ 90 SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\ 91 SRI(OTG_TEST_PATTERN_COLOR, OTG, inst) 92 93 94 struct dcn_optc_registers { 95 uint32_t OTG_GLOBAL_CONTROL1; 96 uint32_t OTG_GLOBAL_CONTROL2; 97 uint32_t OTG_VERT_SYNC_CONTROL; 98 uint32_t OTG_MASTER_UPDATE_MODE; 99 uint32_t OTG_GSL_CONTROL; 100 uint32_t OTG_VSTARTUP_PARAM; 101 uint32_t OTG_VUPDATE_PARAM; 102 uint32_t OTG_VREADY_PARAM; 103 uint32_t OTG_BLANK_CONTROL; 104 uint32_t OTG_MASTER_UPDATE_LOCK; 105 uint32_t OTG_GLOBAL_CONTROL0; 106 uint32_t OTG_DOUBLE_BUFFER_CONTROL; 107 uint32_t OTG_H_TOTAL; 108 uint32_t OTG_H_BLANK_START_END; 109 uint32_t OTG_H_SYNC_A; 110 uint32_t OTG_H_SYNC_A_CNTL; 111 uint32_t OTG_H_TIMING_CNTL; 112 uint32_t OTG_V_TOTAL; 113 uint32_t OTG_V_BLANK_START_END; 114 uint32_t OTG_V_SYNC_A; 115 uint32_t OTG_V_SYNC_A_CNTL; 116 uint32_t OTG_INTERLACE_CONTROL; 117 uint32_t OTG_CONTROL; 118 uint32_t OTG_STEREO_CONTROL; 119 uint32_t OTG_3D_STRUCTURE_CONTROL; 120 uint32_t OTG_STEREO_STATUS; 121 uint32_t OTG_V_TOTAL_MAX; 122 uint32_t OTG_V_TOTAL_MIN; 123 uint32_t OTG_V_TOTAL_CONTROL; 124 uint32_t OTG_TRIGA_CNTL; 125 uint32_t OTG_FORCE_COUNT_NOW_CNTL; 126 uint32_t OTG_STATIC_SCREEN_CONTROL; 127 uint32_t OTG_STATUS_FRAME_COUNT; 128 uint32_t OTG_STATUS; 129 uint32_t OTG_STATUS_POSITION; 130 uint32_t OTG_NOM_VERT_POSITION; 131 uint32_t OTG_BLACK_COLOR; 132 uint32_t OTG_TEST_PATTERN_PARAMETERS; 133 uint32_t OTG_TEST_PATTERN_CONTROL; 134 uint32_t OTG_TEST_PATTERN_COLOR; 135 uint32_t OTG_CLOCK_CONTROL; 136 uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL; 137 uint32_t OTG_VERTICAL_INTERRUPT0_POSITION; 138 uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL; 139 uint32_t OTG_VERTICAL_INTERRUPT2_POSITION; 140 uint32_t OPTC_INPUT_CLOCK_CONTROL; 141 uint32_t OPTC_DATA_SOURCE_SELECT; 142 uint32_t OPTC_MEMORY_CONFIG; 143 uint32_t OPTC_INPUT_GLOBAL_CONTROL; 144 uint32_t CONTROL; 145 uint32_t OTG_GSL_WINDOW_X; 146 uint32_t OTG_GSL_WINDOW_Y; 147 uint32_t OTG_VUPDATE_KEEPOUT; 148 uint32_t OTG_CRC_CNTL; 149 uint32_t OTG_CRC0_DATA_RG; 150 uint32_t OTG_CRC0_DATA_B; 151 uint32_t OTG_CRC0_WINDOWA_X_CONTROL; 152 uint32_t OTG_CRC0_WINDOWA_Y_CONTROL; 153 uint32_t OTG_CRC0_WINDOWB_X_CONTROL; 154 uint32_t OTG_CRC0_WINDOWB_Y_CONTROL; 155 }; 156 157 #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ 158 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ 159 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ 160 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ 161 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\ 162 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\ 163 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\ 164 SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\ 165 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ 166 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\ 167 SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ 168 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ 169 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\ 170 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ 171 SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\ 172 SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\ 173 SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\ 174 SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\ 175 SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\ 176 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\ 177 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\ 178 SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\ 179 SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\ 180 SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\ 181 SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\ 182 SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\ 183 SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\ 184 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\ 185 SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ 186 SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ 187 SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ 188 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ 189 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ 190 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ 191 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\ 192 SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ 193 SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ 194 SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\ 195 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\ 196 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ 197 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ 198 SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ 199 SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ 200 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ 201 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ 202 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ 203 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\ 204 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ 205 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ 206 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ 207 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ 208 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\ 209 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ 210 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ 211 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ 212 SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ 213 SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ 214 SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ 215 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\ 216 SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\ 217 SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\ 218 SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\ 219 SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\ 220 SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\ 221 SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\ 222 SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\ 223 SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ 224 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ 225 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ 226 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\ 227 SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\ 228 SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\ 229 SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\ 230 SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\ 231 SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\ 232 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ 233 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ 234 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ 235 SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ 236 SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ 237 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ 238 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ 239 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ 240 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ 241 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ 242 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ 243 SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\ 244 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ 245 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ 246 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ 247 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ 248 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ 249 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\ 250 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ 251 SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ 252 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ 253 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ 254 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ 255 SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ 256 SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\ 257 SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\ 258 SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\ 259 SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\ 260 SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ 261 SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ 262 SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ 263 SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh) 264 265 266 #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ 267 TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ 268 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\ 269 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\ 270 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\ 271 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\ 272 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\ 273 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\ 274 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\ 275 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\ 276 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\ 277 SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\ 278 SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\ 279 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh) 280 281 #define TG_REG_FIELD_LIST_DCN1_0(type) \ 282 type VSTARTUP_START;\ 283 type VUPDATE_OFFSET;\ 284 type VUPDATE_WIDTH;\ 285 type VREADY_OFFSET;\ 286 type OTG_BLANK_DATA_EN;\ 287 type OTG_BLANK_DE_MODE;\ 288 type OTG_CURRENT_BLANK_STATE;\ 289 type OTG_MASTER_UPDATE_LOCK;\ 290 type UPDATE_LOCK_STATUS;\ 291 type OTG_UPDATE_PENDING;\ 292 type OTG_MASTER_UPDATE_LOCK_SEL;\ 293 type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\ 294 type OTG_H_TOTAL;\ 295 type OTG_H_BLANK_START;\ 296 type OTG_H_BLANK_END;\ 297 type OTG_H_SYNC_A_START;\ 298 type OTG_H_SYNC_A_END;\ 299 type OTG_H_SYNC_A_POL;\ 300 type OTG_H_TIMING_DIV_BY2;\ 301 type OTG_V_TOTAL;\ 302 type OTG_V_BLANK_START;\ 303 type OTG_V_BLANK_END;\ 304 type OTG_V_SYNC_A_START;\ 305 type OTG_V_SYNC_A_END;\ 306 type OTG_V_SYNC_A_POL;\ 307 type OTG_INTERLACE_ENABLE;\ 308 type OTG_MASTER_EN;\ 309 type OTG_START_POINT_CNTL;\ 310 type OTG_DISABLE_POINT_CNTL;\ 311 type OTG_FIELD_NUMBER_CNTL;\ 312 type OTG_STEREO_EN;\ 313 type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\ 314 type OTG_STEREO_SYNC_OUTPUT_POLARITY;\ 315 type OTG_STEREO_EYE_FLAG_POLARITY;\ 316 type OTG_STEREO_CURRENT_EYE;\ 317 type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\ 318 type OTG_3D_STRUCTURE_EN;\ 319 type OTG_3D_STRUCTURE_V_UPDATE_MODE;\ 320 type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\ 321 type OTG_V_TOTAL_MAX;\ 322 type OTG_V_TOTAL_MIN;\ 323 type OTG_V_TOTAL_MIN_SEL;\ 324 type OTG_V_TOTAL_MAX_SEL;\ 325 type OTG_FORCE_LOCK_ON_EVENT;\ 326 type OTG_SET_V_TOTAL_MIN_MASK_EN;\ 327 type OTG_SET_V_TOTAL_MIN_MASK;\ 328 type OTG_FORCE_COUNT_NOW_CLEAR;\ 329 type OTG_FORCE_COUNT_NOW_MODE;\ 330 type OTG_FORCE_COUNT_NOW_OCCURRED;\ 331 type OTG_TRIGA_SOURCE_SELECT;\ 332 type OTG_TRIGA_SOURCE_PIPE_SELECT;\ 333 type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\ 334 type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\ 335 type OTG_STATIC_SCREEN_EVENT_MASK;\ 336 type OTG_STATIC_SCREEN_FRAME_COUNT;\ 337 type OTG_FRAME_COUNT;\ 338 type OTG_V_BLANK;\ 339 type OTG_V_ACTIVE_DISP;\ 340 type OTG_HORZ_COUNT;\ 341 type OTG_VERT_COUNT;\ 342 type OTG_VERT_COUNT_NOM;\ 343 type OTG_BLACK_COLOR_B_CB;\ 344 type OTG_BLACK_COLOR_G_Y;\ 345 type OTG_BLACK_COLOR_R_CR;\ 346 type OTG_TEST_PATTERN_INC0;\ 347 type OTG_TEST_PATTERN_INC1;\ 348 type OTG_TEST_PATTERN_VRES;\ 349 type OTG_TEST_PATTERN_HRES;\ 350 type OTG_TEST_PATTERN_RAMP0_OFFSET;\ 351 type OTG_TEST_PATTERN_EN;\ 352 type OTG_TEST_PATTERN_MODE;\ 353 type OTG_TEST_PATTERN_DYNAMIC_RANGE;\ 354 type OTG_TEST_PATTERN_COLOR_FORMAT;\ 355 type OTG_TEST_PATTERN_MASK;\ 356 type OTG_TEST_PATTERN_DATA;\ 357 type OTG_BUSY;\ 358 type OTG_CLOCK_EN;\ 359 type OTG_CLOCK_ON;\ 360 type OTG_CLOCK_GATE_DIS;\ 361 type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\ 362 type OTG_VERTICAL_INTERRUPT0_LINE_START;\ 363 type OTG_VERTICAL_INTERRUPT0_LINE_END;\ 364 type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\ 365 type OTG_VERTICAL_INTERRUPT2_LINE_START;\ 366 type OPTC_INPUT_CLK_EN;\ 367 type OPTC_INPUT_CLK_ON;\ 368 type OPTC_INPUT_CLK_GATE_DIS;\ 369 type OPTC_UNDERFLOW_OCCURRED_STATUS;\ 370 type OPTC_UNDERFLOW_CLEAR;\ 371 type OPTC_SRC_SEL;\ 372 type VTG0_ENABLE;\ 373 type VTG0_FP2;\ 374 type VTG0_VCOUNT_INIT;\ 375 type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\ 376 type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\ 377 type OTG_AUTO_FORCE_VSYNC_MODE;\ 378 type MASTER_UPDATE_INTERLACED_MODE;\ 379 type OTG_GSL0_EN;\ 380 type OTG_GSL1_EN;\ 381 type OTG_GSL2_EN;\ 382 type OTG_GSL_MASTER_EN;\ 383 type OTG_GSL_FORCE_DELAY;\ 384 type OTG_GSL_CHECK_ALL_FIELDS;\ 385 type OTG_GSL_WINDOW_START_X;\ 386 type OTG_GSL_WINDOW_END_X;\ 387 type OTG_GSL_WINDOW_START_Y;\ 388 type OTG_GSL_WINDOW_END_Y;\ 389 type OTG_RANGE_TIMING_DBUF_UPDATE_MODE;\ 390 type OTG_GSL_MASTER_MODE;\ 391 type OTG_MASTER_UPDATE_LOCK_GSL_EN;\ 392 type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET;\ 393 type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET;\ 394 type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN;\ 395 type OTG_CRC_CONT_EN;\ 396 type OTG_CRC0_SELECT;\ 397 type OTG_CRC_EN;\ 398 type CRC0_R_CR;\ 399 type CRC0_G_Y;\ 400 type CRC0_B_CB;\ 401 type OTG_CRC0_WINDOWA_X_START;\ 402 type OTG_CRC0_WINDOWA_X_END;\ 403 type OTG_CRC0_WINDOWA_Y_START;\ 404 type OTG_CRC0_WINDOWA_Y_END;\ 405 type OTG_CRC0_WINDOWB_X_START;\ 406 type OTG_CRC0_WINDOWB_X_END;\ 407 type OTG_CRC0_WINDOWB_Y_START;\ 408 type OTG_CRC0_WINDOWB_Y_END; 409 410 411 #define TG_REG_FIELD_LIST(type) \ 412 TG_REG_FIELD_LIST_DCN1_0(type) 413 414 415 struct dcn_optc_shift { 416 TG_REG_FIELD_LIST(uint8_t) 417 }; 418 419 struct dcn_optc_mask { 420 TG_REG_FIELD_LIST(uint32_t) 421 }; 422 423 struct optc { 424 struct timing_generator base; 425 426 const struct dcn_optc_registers *tg_regs; 427 const struct dcn_optc_shift *tg_shift; 428 const struct dcn_optc_mask *tg_mask; 429 430 enum controller_id controller_id; 431 432 uint32_t max_h_total; 433 uint32_t max_v_total; 434 435 uint32_t min_h_blank; 436 437 uint32_t min_h_sync_width; 438 uint32_t min_v_sync_width; 439 uint32_t min_v_blank; 440 uint32_t min_v_blank_interlace; 441 }; 442 443 void dcn10_timing_generator_init(struct optc *optc); 444 445 struct dcn_otg_state { 446 uint32_t v_blank_start; 447 uint32_t v_blank_end; 448 uint32_t v_sync_a_pol; 449 uint32_t v_total; 450 uint32_t v_total_max; 451 uint32_t v_total_min; 452 uint32_t v_total_min_sel; 453 uint32_t v_total_max_sel; 454 uint32_t v_sync_a_start; 455 uint32_t v_sync_a_end; 456 uint32_t h_blank_start; 457 uint32_t h_blank_end; 458 uint32_t h_sync_a_start; 459 uint32_t h_sync_a_end; 460 uint32_t h_sync_a_pol; 461 uint32_t h_total; 462 uint32_t underflow_occurred_status; 463 uint32_t otg_enabled; 464 }; 465 466 void optc1_read_otg_state(struct optc *optc1, 467 struct dcn_otg_state *s); 468 469 bool optc1_validate_timing( 470 struct timing_generator *optc, 471 const struct dc_crtc_timing *timing); 472 473 void optc1_program_timing( 474 struct timing_generator *optc, 475 const struct dc_crtc_timing *dc_crtc_timing, 476 bool use_vbios); 477 478 void optc1_program_vline_interrupt(struct timing_generator *optc, 479 const struct dc_crtc_timing *dc_crtc_timing, 480 unsigned long long vsync_delta); 481 482 void optc1_program_global_sync( 483 struct timing_generator *optc); 484 485 bool optc1_disable_crtc(struct timing_generator *optc); 486 487 bool optc1_is_counter_moving(struct timing_generator *optc); 488 489 void optc1_get_position(struct timing_generator *optc, 490 struct crtc_position *position); 491 492 uint32_t optc1_get_vblank_counter(struct timing_generator *optc); 493 494 void optc1_get_crtc_scanoutpos( 495 struct timing_generator *optc, 496 uint32_t *v_blank_start, 497 uint32_t *v_blank_end, 498 uint32_t *h_position, 499 uint32_t *v_position); 500 501 void optc1_set_early_control( 502 struct timing_generator *optc, 503 uint32_t early_cntl); 504 505 void optc1_wait_for_state(struct timing_generator *optc, 506 enum crtc_state state); 507 508 void optc1_set_blank(struct timing_generator *optc, 509 bool enable_blanking); 510 511 bool optc1_is_blanked(struct timing_generator *optc); 512 513 void optc1_program_blank_color( 514 struct timing_generator *optc, 515 const struct tg_color *black_color); 516 517 bool optc1_did_triggered_reset_occur( 518 struct timing_generator *optc); 519 520 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst); 521 522 void optc1_disable_reset_trigger(struct timing_generator *optc); 523 524 void optc1_lock(struct timing_generator *optc); 525 526 void optc1_unlock(struct timing_generator *optc); 527 528 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable); 529 530 void optc1_set_drr( 531 struct timing_generator *optc, 532 const struct drr_params *params); 533 534 void optc1_set_static_screen_control( 535 struct timing_generator *optc, 536 uint32_t value); 537 538 void optc1_program_stereo(struct timing_generator *optc, 539 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); 540 541 bool optc1_is_stereo_left_eye(struct timing_generator *optc); 542 543 void optc1_clear_optc_underflow(struct timing_generator *optc); 544 545 void optc1_tg_init(struct timing_generator *optc); 546 547 bool optc1_is_tg_enabled(struct timing_generator *optc); 548 549 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc); 550 551 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable); 552 553 bool optc1_get_otg_active_size(struct timing_generator *optc, 554 uint32_t *otg_active_width, 555 uint32_t *otg_active_height); 556 557 void optc1_enable_crtc_reset( 558 struct timing_generator *optc, 559 int source_tg_inst, 560 struct crtc_trigger_info *crtc_tp); 561 562 bool optc1_configure_crc(struct timing_generator *optc, 563 const struct crc_params *params); 564 565 bool optc1_get_crc(struct timing_generator *optc, 566 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); 567 568 #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */ 569
