1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König <christian.koenig@amd.com>
23 */
24
25 #include <linux/firmware.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_uvd.h"
29 #include "cikd.h"
30
31 #include "uvd/uvd_4_2_d.h"
32 #include "uvd/uvd_4_2_sh_mask.h"
33
34 #include "oss/oss_2_0_d.h"
35 #include "oss/oss_2_0_sh_mask.h"
36
37 #include "bif/bif_4_1_d.h"
38
39 #include "smu/smu_7_0_1_d.h"
40 #include "smu/smu_7_0_1_sh_mask.h"
41
42 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev);
43 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
44 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
45 static int uvd_v4_2_start(struct amdgpu_device *adev);
46 static void uvd_v4_2_stop(struct amdgpu_device *adev);
47 static int uvd_v4_2_set_clockgating_state(void *handle,
48 enum amd_clockgating_state state);
49 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
50 bool sw_mode);
51 /**
52 * uvd_v4_2_ring_get_rptr - get read pointer
53 *
54 * @ring: amdgpu_ring pointer
55 *
56 * Returns the current hardware read pointer
57 */
uvd_v4_2_ring_get_rptr(struct amdgpu_ring * ring)58 static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring)
59 {
60 struct amdgpu_device *adev = ring->adev;
61
62 return RREG32(mmUVD_RBC_RB_RPTR);
63 }
64
65 /**
66 * uvd_v4_2_ring_get_wptr - get write pointer
67 *
68 * @ring: amdgpu_ring pointer
69 *
70 * Returns the current hardware write pointer
71 */
uvd_v4_2_ring_get_wptr(struct amdgpu_ring * ring)72 static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring)
73 {
74 struct amdgpu_device *adev = ring->adev;
75
76 return RREG32(mmUVD_RBC_RB_WPTR);
77 }
78
79 /**
80 * uvd_v4_2_ring_set_wptr - set write pointer
81 *
82 * @ring: amdgpu_ring pointer
83 *
84 * Commits the write pointer to the hardware
85 */
uvd_v4_2_ring_set_wptr(struct amdgpu_ring * ring)86 static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring)
87 {
88 struct amdgpu_device *adev = ring->adev;
89
90 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
91 }
92
uvd_v4_2_early_init(void * handle)93 static int uvd_v4_2_early_init(void *handle)
94 {
95 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
96 adev->uvd.num_uvd_inst = 1;
97
98 uvd_v4_2_set_ring_funcs(adev);
99 uvd_v4_2_set_irq_funcs(adev);
100
101 return 0;
102 }
103
uvd_v4_2_sw_init(void * handle)104 static int uvd_v4_2_sw_init(void *handle)
105 {
106 struct amdgpu_ring *ring;
107 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
108 int r;
109
110 /* UVD TRAP */
111 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
112 if (r)
113 return r;
114
115 r = amdgpu_uvd_sw_init(adev);
116 if (r)
117 return r;
118
119 ring = &adev->uvd.inst->ring;
120 sprintf(ring->name, "uvd");
121 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
122 AMDGPU_RING_PRIO_DEFAULT, NULL);
123 if (r)
124 return r;
125
126 r = amdgpu_uvd_resume(adev);
127 if (r)
128 return r;
129
130 r = amdgpu_uvd_entity_init(adev);
131
132 return r;
133 }
134
uvd_v4_2_sw_fini(void * handle)135 static int uvd_v4_2_sw_fini(void *handle)
136 {
137 int r;
138 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
139
140 r = amdgpu_uvd_suspend(adev);
141 if (r)
142 return r;
143
144 return amdgpu_uvd_sw_fini(adev);
145 }
146
147 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
148 bool enable);
149 /**
150 * uvd_v4_2_hw_init - start and test UVD block
151 *
152 * @handle: handle used to pass amdgpu_device pointer
153 *
154 * Initialize the hardware, boot up the VCPU and do some testing
155 */
uvd_v4_2_hw_init(void * handle)156 static int uvd_v4_2_hw_init(void *handle)
157 {
158 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
159 struct amdgpu_ring *ring = &adev->uvd.inst->ring;
160 uint32_t tmp;
161 int r;
162
163 uvd_v4_2_enable_mgcg(adev, true);
164 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
165
166 r = amdgpu_ring_test_helper(ring);
167 if (r)
168 goto done;
169
170 r = amdgpu_ring_alloc(ring, 10);
171 if (r) {
172 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
173 goto done;
174 }
175
176 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
177 amdgpu_ring_write(ring, tmp);
178 amdgpu_ring_write(ring, 0xFFFFF);
179
180 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
181 amdgpu_ring_write(ring, tmp);
182 amdgpu_ring_write(ring, 0xFFFFF);
183
184 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
185 amdgpu_ring_write(ring, tmp);
186 amdgpu_ring_write(ring, 0xFFFFF);
187
188 /* Clear timeout status bits */
189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
190 amdgpu_ring_write(ring, 0x8);
191
192 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
193 amdgpu_ring_write(ring, 3);
194
195 amdgpu_ring_commit(ring);
196
197 done:
198 if (!r)
199 DRM_INFO("UVD initialized successfully.\n");
200
201 return r;
202 }
203
204 /**
205 * uvd_v4_2_hw_fini - stop the hardware block
206 *
207 * @handle: handle used to pass amdgpu_device pointer
208 *
209 * Stop the UVD block, mark ring as not ready any more
210 */
uvd_v4_2_hw_fini(void * handle)211 static int uvd_v4_2_hw_fini(void *handle)
212 {
213 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
214
215 /*
216 * Proper cleanups before halting the HW engine:
217 * - cancel the delayed idle work
218 * - enable powergating
219 * - enable clockgating
220 * - disable dpm
221 *
222 * TODO: to align with the VCN implementation, move the
223 * jobs for clockgating/powergating/dpm setting to
224 * ->set_powergating_state().
225 */
226 cancel_delayed_work_sync(&adev->uvd.idle_work);
227
228 if (adev->pm.dpm_enabled) {
229 amdgpu_dpm_enable_uvd(adev, false);
230 } else {
231 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
232 /* shutdown the UVD block */
233 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
234 AMD_PG_STATE_GATE);
235 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
236 AMD_CG_STATE_GATE);
237 }
238
239 if (RREG32(mmUVD_STATUS) != 0)
240 uvd_v4_2_stop(adev);
241
242 return 0;
243 }
244
uvd_v4_2_suspend(void * handle)245 static int uvd_v4_2_suspend(void *handle)
246 {
247 int r;
248 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
249
250 r = uvd_v4_2_hw_fini(adev);
251 if (r)
252 return r;
253
254 return amdgpu_uvd_suspend(adev);
255 }
256
uvd_v4_2_resume(void * handle)257 static int uvd_v4_2_resume(void *handle)
258 {
259 int r;
260 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
261
262 r = amdgpu_uvd_resume(adev);
263 if (r)
264 return r;
265
266 return uvd_v4_2_hw_init(adev);
267 }
268
269 /**
270 * uvd_v4_2_start - start UVD block
271 *
272 * @adev: amdgpu_device pointer
273 *
274 * Setup and start the UVD block
275 */
uvd_v4_2_start(struct amdgpu_device * adev)276 static int uvd_v4_2_start(struct amdgpu_device *adev)
277 {
278 struct amdgpu_ring *ring = &adev->uvd.inst->ring;
279 uint32_t rb_bufsz;
280 int i, j, r;
281 u32 tmp;
282 /* disable byte swapping */
283 u32 lmi_swap_cntl = 0;
284 u32 mp_swap_cntl = 0;
285
286 /* set uvd busy */
287 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));
288
289 uvd_v4_2_set_dcm(adev, true);
290 WREG32(mmUVD_CGC_GATE, 0);
291
292 /* take UVD block out of reset */
293 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
294 mdelay(5);
295
296 /* enable VCPU clock */
297 WREG32(mmUVD_VCPU_CNTL, 1 << 9);
298
299 /* disable interupt */
300 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
301
302 #ifdef __BIG_ENDIAN
303 /* swap (8 in 32) RB and IB */
304 lmi_swap_cntl = 0xa;
305 mp_swap_cntl = 0;
306 #endif
307 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
308 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
309 /* initialize UVD memory controller */
310 WREG32(mmUVD_LMI_CTRL, 0x203108);
311
312 tmp = RREG32(mmUVD_MPC_CNTL);
313 WREG32(mmUVD_MPC_CNTL, tmp | 0x10);
314
315 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
316 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
317 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
318 WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
319 WREG32(mmUVD_MPC_SET_ALU, 0);
320 WREG32(mmUVD_MPC_SET_MUX, 0x88);
321
322 uvd_v4_2_mc_resume(adev);
323
324 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL);
325 WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10));
326
327 /* enable UMC */
328 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
329
330 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
331
332 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
333
334 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
335
336 mdelay(10);
337
338 for (i = 0; i < 10; ++i) {
339 uint32_t status;
340 for (j = 0; j < 100; ++j) {
341 status = RREG32(mmUVD_STATUS);
342 if (status & 2)
343 break;
344 mdelay(10);
345 }
346 r = 0;
347 if (status & 2)
348 break;
349
350 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
351 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
352 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
353 mdelay(10);
354 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
355 mdelay(10);
356 r = -1;
357 }
358
359 if (r) {
360 DRM_ERROR("UVD not responding, giving up!!!\n");
361 return r;
362 }
363
364 /* enable interupt */
365 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
366
367 WREG32_P(mmUVD_STATUS, 0, ~(1<<2));
368
369 /* force RBC into idle state */
370 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
371
372 /* Set the write pointer delay */
373 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
374
375 /* program the 4GB memory segment for rptr and ring buffer */
376 WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
377 (0x7 << 16) | (0x1 << 31));
378
379 /* Initialize the ring buffer's read and write pointers */
380 WREG32(mmUVD_RBC_RB_RPTR, 0x0);
381
382 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
383 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
384
385 /* set the ring address */
386 WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
387
388 /* Set ring buffer size */
389 rb_bufsz = order_base_2(ring->ring_size);
390 rb_bufsz = (0x1 << 8) | rb_bufsz;
391 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
392
393 return 0;
394 }
395
396 /**
397 * uvd_v4_2_stop - stop UVD block
398 *
399 * @adev: amdgpu_device pointer
400 *
401 * stop the UVD block
402 */
uvd_v4_2_stop(struct amdgpu_device * adev)403 static void uvd_v4_2_stop(struct amdgpu_device *adev)
404 {
405 uint32_t i, j;
406 uint32_t status;
407
408 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
409
410 for (i = 0; i < 10; ++i) {
411 for (j = 0; j < 100; ++j) {
412 status = RREG32(mmUVD_STATUS);
413 if (status & 2)
414 break;
415 mdelay(1);
416 }
417 if (status & 2)
418 break;
419 }
420
421 for (i = 0; i < 10; ++i) {
422 for (j = 0; j < 100; ++j) {
423 status = RREG32(mmUVD_LMI_STATUS);
424 if (status & 0xf)
425 break;
426 mdelay(1);
427 }
428 if (status & 0xf)
429 break;
430 }
431
432 /* Stall UMC and register bus before resetting VCPU */
433 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
434
435 for (i = 0; i < 10; ++i) {
436 for (j = 0; j < 100; ++j) {
437 status = RREG32(mmUVD_LMI_STATUS);
438 if (status & 0x240)
439 break;
440 mdelay(1);
441 }
442 if (status & 0x240)
443 break;
444 }
445
446 WREG32_P(0x3D49, 0, ~(1 << 2));
447
448 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));
449
450 /* put LMI, VCPU, RBC etc... into reset */
451 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
452 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
453 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
454
455 WREG32(mmUVD_STATUS, 0);
456
457 uvd_v4_2_set_dcm(adev, false);
458 }
459
460 /**
461 * uvd_v4_2_ring_emit_fence - emit an fence & trap command
462 *
463 * @ring: amdgpu_ring pointer
464 * @addr: address
465 * @seq: sequence number
466 * @flags: fence related flags
467 *
468 * Write a fence and a trap command to the ring.
469 */
uvd_v4_2_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)470 static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
471 unsigned flags)
472 {
473 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
474
475 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
476 amdgpu_ring_write(ring, seq);
477 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
478 amdgpu_ring_write(ring, addr & 0xffffffff);
479 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
480 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
481 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
482 amdgpu_ring_write(ring, 0);
483
484 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
485 amdgpu_ring_write(ring, 0);
486 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
487 amdgpu_ring_write(ring, 0);
488 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
489 amdgpu_ring_write(ring, 2);
490 }
491
492 /**
493 * uvd_v4_2_ring_test_ring - register write test
494 *
495 * @ring: amdgpu_ring pointer
496 *
497 * Test if we can successfully write to the context register
498 */
uvd_v4_2_ring_test_ring(struct amdgpu_ring * ring)499 static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)
500 {
501 struct amdgpu_device *adev = ring->adev;
502 uint32_t tmp = 0;
503 unsigned i;
504 int r;
505
506 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
507 r = amdgpu_ring_alloc(ring, 3);
508 if (r)
509 return r;
510
511 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
512 amdgpu_ring_write(ring, 0xDEADBEEF);
513 amdgpu_ring_commit(ring);
514 for (i = 0; i < adev->usec_timeout; i++) {
515 tmp = RREG32(mmUVD_CONTEXT_ID);
516 if (tmp == 0xDEADBEEF)
517 break;
518 udelay(1);
519 }
520
521 if (i >= adev->usec_timeout)
522 r = -ETIMEDOUT;
523
524 return r;
525 }
526
527 /**
528 * uvd_v4_2_ring_emit_ib - execute indirect buffer
529 *
530 * @ring: amdgpu_ring pointer
531 * @job: iob associated with the indirect buffer
532 * @ib: indirect buffer to execute
533 * @flags: flags associated with the indirect buffer
534 *
535 * Write ring commands to execute the indirect buffer
536 */
uvd_v4_2_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)537 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
538 struct amdgpu_job *job,
539 struct amdgpu_ib *ib,
540 uint32_t flags)
541 {
542 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
543 amdgpu_ring_write(ring, ib->gpu_addr);
544 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
545 amdgpu_ring_write(ring, ib->length_dw);
546 }
547
uvd_v4_2_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)548 static void uvd_v4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
549 {
550 int i;
551
552 WARN_ON(ring->wptr % 2 || count % 2);
553
554 for (i = 0; i < count / 2; i++) {
555 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
556 amdgpu_ring_write(ring, 0);
557 }
558 }
559
560 /**
561 * uvd_v4_2_mc_resume - memory controller programming
562 *
563 * @adev: amdgpu_device pointer
564 *
565 * Let the UVD memory controller know it's offsets
566 */
uvd_v4_2_mc_resume(struct amdgpu_device * adev)567 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
568 {
569 uint64_t addr;
570 uint32_t size;
571
572 /* program the VCPU memory controller bits 0-27 */
573 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
574 size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3;
575 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
576 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
577
578 addr += size;
579 size = AMDGPU_UVD_HEAP_SIZE >> 3;
580 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
581 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
582
583 addr += size;
584 size = (AMDGPU_UVD_STACK_SIZE +
585 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3;
586 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
587 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
588
589 /* bits 28-31 */
590 addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF;
591 WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
592
593 /* bits 32-39 */
594 addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF;
595 WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
596
597 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
598 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
599 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
600 }
601
uvd_v4_2_enable_mgcg(struct amdgpu_device * adev,bool enable)602 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
603 bool enable)
604 {
605 u32 orig, data;
606
607 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
608 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
609 data |= 0xfff;
610 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
611
612 orig = data = RREG32(mmUVD_CGC_CTRL);
613 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
614 if (orig != data)
615 WREG32(mmUVD_CGC_CTRL, data);
616 } else {
617 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
618 data &= ~0xfff;
619 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
620
621 orig = data = RREG32(mmUVD_CGC_CTRL);
622 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
623 if (orig != data)
624 WREG32(mmUVD_CGC_CTRL, data);
625 }
626 }
627
uvd_v4_2_set_dcm(struct amdgpu_device * adev,bool sw_mode)628 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
629 bool sw_mode)
630 {
631 u32 tmp, tmp2;
632
633 WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
634
635 tmp = RREG32(mmUVD_CGC_CTRL);
636 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
637 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
638 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) |
639 (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT);
640
641 if (sw_mode) {
642 tmp &= ~0x7ffff800;
643 tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
644 UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK |
645 (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT);
646 } else {
647 tmp |= 0x7ffff800;
648 tmp2 = 0;
649 }
650
651 WREG32(mmUVD_CGC_CTRL, tmp);
652 WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);
653 }
654
uvd_v4_2_is_idle(void * handle)655 static bool uvd_v4_2_is_idle(void *handle)
656 {
657 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
658
659 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
660 }
661
uvd_v4_2_wait_for_idle(void * handle)662 static int uvd_v4_2_wait_for_idle(void *handle)
663 {
664 unsigned i;
665 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
666
667 for (i = 0; i < adev->usec_timeout; i++) {
668 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
669 return 0;
670 }
671 return -ETIMEDOUT;
672 }
673
uvd_v4_2_soft_reset(void * handle)674 static int uvd_v4_2_soft_reset(void *handle)
675 {
676 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
677
678 uvd_v4_2_stop(adev);
679
680 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
681 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
682 mdelay(5);
683
684 return uvd_v4_2_start(adev);
685 }
686
uvd_v4_2_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)687 static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev,
688 struct amdgpu_irq_src *source,
689 unsigned type,
690 enum amdgpu_interrupt_state state)
691 {
692 // TODO
693 return 0;
694 }
695
uvd_v4_2_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)696 static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
697 struct amdgpu_irq_src *source,
698 struct amdgpu_iv_entry *entry)
699 {
700 DRM_DEBUG("IH: UVD TRAP\n");
701 amdgpu_fence_process(&adev->uvd.inst->ring);
702 return 0;
703 }
704
uvd_v4_2_set_clockgating_state(void * handle,enum amd_clockgating_state state)705 static int uvd_v4_2_set_clockgating_state(void *handle,
706 enum amd_clockgating_state state)
707 {
708 return 0;
709 }
710
uvd_v4_2_set_powergating_state(void * handle,enum amd_powergating_state state)711 static int uvd_v4_2_set_powergating_state(void *handle,
712 enum amd_powergating_state state)
713 {
714 /* This doesn't actually powergate the UVD block.
715 * That's done in the dpm code via the SMC. This
716 * just re-inits the block as necessary. The actual
717 * gating still happens in the dpm code. We should
718 * revisit this when there is a cleaner line between
719 * the smc and the hw blocks
720 */
721 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
722
723 if (state == AMD_PG_STATE_GATE) {
724 uvd_v4_2_stop(adev);
725 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) {
726 if (!(RREG32_SMC(ixCURRENT_PG_STATUS) &
727 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK)) {
728 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
729 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK |
730 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));
731 mdelay(20);
732 }
733 }
734 return 0;
735 } else {
736 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) {
737 if (RREG32_SMC(ixCURRENT_PG_STATUS) &
738 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
739 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
740 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK |
741 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));
742 mdelay(30);
743 }
744 }
745 return uvd_v4_2_start(adev);
746 }
747 }
748
749 static const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
750 .name = "uvd_v4_2",
751 .early_init = uvd_v4_2_early_init,
752 .late_init = NULL,
753 .sw_init = uvd_v4_2_sw_init,
754 .sw_fini = uvd_v4_2_sw_fini,
755 .hw_init = uvd_v4_2_hw_init,
756 .hw_fini = uvd_v4_2_hw_fini,
757 .suspend = uvd_v4_2_suspend,
758 .resume = uvd_v4_2_resume,
759 .is_idle = uvd_v4_2_is_idle,
760 .wait_for_idle = uvd_v4_2_wait_for_idle,
761 .soft_reset = uvd_v4_2_soft_reset,
762 .set_clockgating_state = uvd_v4_2_set_clockgating_state,
763 .set_powergating_state = uvd_v4_2_set_powergating_state,
764 };
765
766 static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
767 .type = AMDGPU_RING_TYPE_UVD,
768 .align_mask = 0xf,
769 .support_64bit_ptrs = false,
770 .no_user_fence = true,
771 .get_rptr = uvd_v4_2_ring_get_rptr,
772 .get_wptr = uvd_v4_2_ring_get_wptr,
773 .set_wptr = uvd_v4_2_ring_set_wptr,
774 .parse_cs = amdgpu_uvd_ring_parse_cs,
775 .emit_frame_size =
776 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */
777 .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */
778 .emit_ib = uvd_v4_2_ring_emit_ib,
779 .emit_fence = uvd_v4_2_ring_emit_fence,
780 .test_ring = uvd_v4_2_ring_test_ring,
781 .test_ib = amdgpu_uvd_ring_test_ib,
782 .insert_nop = uvd_v4_2_ring_insert_nop,
783 .pad_ib = amdgpu_ring_generic_pad_ib,
784 .begin_use = amdgpu_uvd_ring_begin_use,
785 .end_use = amdgpu_uvd_ring_end_use,
786 };
787
uvd_v4_2_set_ring_funcs(struct amdgpu_device * adev)788 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev)
789 {
790 adev->uvd.inst->ring.funcs = &uvd_v4_2_ring_funcs;
791 }
792
793 static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = {
794 .set = uvd_v4_2_set_interrupt_state,
795 .process = uvd_v4_2_process_interrupt,
796 };
797
uvd_v4_2_set_irq_funcs(struct amdgpu_device * adev)798 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev)
799 {
800 adev->uvd.inst->irq.num_types = 1;
801 adev->uvd.inst->irq.funcs = &uvd_v4_2_irq_funcs;
802 }
803
804 const struct amdgpu_ip_block_version uvd_v4_2_ip_block =
805 {
806 .type = AMD_IP_BLOCK_TYPE_UVD,
807 .major = 4,
808 .minor = 2,
809 .rev = 0,
810 .funcs = &uvd_v4_2_ip_funcs,
811 };
812
