1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
9 */
10 #include <linux/crash_dump.h>
11 #include <linux/cpuhotplug.h>
12 #include <linux/cpumask.h>
13 #include <linux/proc_fs.h>
14 #include <linux/memory.h>
15 #include <linux/export.h>
16 #include <linux/pci.h>
17
18 #include <asm/e820/api.h>
19 #include <asm/uv/uv_mmrs.h>
20 #include <asm/uv/uv_hub.h>
21 #include <asm/uv/bios.h>
22 #include <asm/uv/uv.h>
23 #include <asm/apic.h>
24
25 static DEFINE_PER_CPU(int, x2apic_extra_bits);
26
27 static enum uv_system_type uv_system_type;
28 static bool uv_hubless_system;
29 static u64 gru_start_paddr, gru_end_paddr;
30 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
31 static u64 gru_dist_lmask, gru_dist_umask;
32 static union uvh_apicid uvh_apicid;
33
34 /* Information derived from CPUID: */
35 static struct {
36 unsigned int apicid_shift;
37 unsigned int apicid_mask;
38 unsigned int socketid_shift; /* aka pnode_shift for UV1/2/3 */
39 unsigned int pnode_mask;
40 unsigned int gpa_shift;
41 unsigned int gnode_shift;
42 } uv_cpuid;
43
44 int uv_min_hub_revision_id;
45 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
46
47 unsigned int uv_apicid_hibits;
48 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
49
50 static struct apic apic_x2apic_uv_x;
51 static struct uv_hub_info_s uv_hub_info_node0;
52
53 /* Set this to use hardware error handler instead of kernel panic: */
54 static int disable_uv_undefined_panic = 1;
55
uv_undefined(char * str)56 unsigned long uv_undefined(char *str)
57 {
58 if (likely(!disable_uv_undefined_panic))
59 panic("UV: error: undefined MMR: %s\n", str);
60 else
61 pr_crit("UV: error: undefined MMR: %s\n", str);
62
63 /* Cause a machine fault: */
64 return ~0ul;
65 }
66 EXPORT_SYMBOL(uv_undefined);
67
uv_early_read_mmr(unsigned long addr)68 static unsigned long __init uv_early_read_mmr(unsigned long addr)
69 {
70 unsigned long val, *mmr;
71
72 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
73 val = *mmr;
74 early_iounmap(mmr, sizeof(*mmr));
75
76 return val;
77 }
78
is_GRU_range(u64 start,u64 end)79 static inline bool is_GRU_range(u64 start, u64 end)
80 {
81 if (gru_dist_base) {
82 u64 su = start & gru_dist_umask; /* Upper (incl pnode) bits */
83 u64 sl = start & gru_dist_lmask; /* Base offset bits */
84 u64 eu = end & gru_dist_umask;
85 u64 el = end & gru_dist_lmask;
86
87 /* Must reside completely within a single GRU range: */
88 return (sl == gru_dist_base && el == gru_dist_base &&
89 su >= gru_first_node_paddr &&
90 su <= gru_last_node_paddr &&
91 eu == su);
92 } else {
93 return start >= gru_start_paddr && end <= gru_end_paddr;
94 }
95 }
96
uv_is_untracked_pat_range(u64 start,u64 end)97 static bool uv_is_untracked_pat_range(u64 start, u64 end)
98 {
99 return is_ISA_range(start, end) || is_GRU_range(start, end);
100 }
101
early_get_pnodeid(void)102 static int __init early_get_pnodeid(void)
103 {
104 union uvh_node_id_u node_id;
105 union uvh_rh_gam_config_mmr_u m_n_config;
106 int pnode;
107
108 /* Currently, all blades have same revision number */
109 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
110 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
111 uv_min_hub_revision_id = node_id.s.revision;
112
113 switch (node_id.s.part_number) {
114 case UV2_HUB_PART_NUMBER:
115 case UV2_HUB_PART_NUMBER_X:
116 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
117 break;
118 case UV3_HUB_PART_NUMBER:
119 case UV3_HUB_PART_NUMBER_X:
120 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
121 break;
122
123 /* Update: UV4A has only a modified revision to indicate HUB fixes */
124 case UV4_HUB_PART_NUMBER:
125 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
126 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
127 break;
128 }
129
130 uv_hub_info->hub_revision = uv_min_hub_revision_id;
131 uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
132 pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
133 uv_cpuid.gpa_shift = 46; /* Default unless changed */
134
135 pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
136 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
137 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
138 return pnode;
139 }
140
uv_tsc_check_sync(void)141 static void __init uv_tsc_check_sync(void)
142 {
143 u64 mmr;
144 int sync_state;
145 int mmr_shift;
146 char *state;
147 bool valid;
148
149 /* Accommodate different UV arch BIOSes */
150 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
151 mmr_shift =
152 is_uv1_hub() ? 0 :
153 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
154 if (mmr_shift)
155 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
156 else
157 sync_state = 0;
158
159 switch (sync_state) {
160 case UVH_TSC_SYNC_VALID:
161 state = "in sync";
162 valid = true;
163 break;
164
165 case UVH_TSC_SYNC_INVALID:
166 state = "unstable";
167 valid = false;
168 break;
169 default:
170 state = "unknown: assuming valid";
171 valid = true;
172 break;
173 }
174 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
175
176 /* Mark flag that says TSC != 0 is valid for socket 0 */
177 if (valid)
178 mark_tsc_async_resets("UV BIOS");
179 else
180 mark_tsc_unstable("UV BIOS");
181 }
182
183 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
184
185 #define SMT_LEVEL 0 /* Leaf 0xb SMT level */
186 #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */
187 #define SMT_TYPE 1
188 #define CORE_TYPE 2
189 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
190 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
191
set_x2apic_bits(void)192 static void set_x2apic_bits(void)
193 {
194 unsigned int eax, ebx, ecx, edx, sub_index;
195 unsigned int sid_shift;
196
197 cpuid(0, &eax, &ebx, &ecx, &edx);
198 if (eax < 0xb) {
199 pr_info("UV: CPU does not have CPUID.11\n");
200 return;
201 }
202
203 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
204 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
205 pr_info("UV: CPUID.11 not implemented\n");
206 return;
207 }
208
209 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
210 sub_index = 1;
211 do {
212 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
213 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
214 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
215 break;
216 }
217 sub_index++;
218 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
219
220 uv_cpuid.apicid_shift = 0;
221 uv_cpuid.apicid_mask = (~(-1 << sid_shift));
222 uv_cpuid.socketid_shift = sid_shift;
223 }
224
early_get_apic_socketid_shift(void)225 static void __init early_get_apic_socketid_shift(void)
226 {
227 if (is_uv2_hub() || is_uv3_hub())
228 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
229
230 set_x2apic_bits();
231
232 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
233 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
234 }
235
236 /*
237 * Add an extra bit as dictated by bios to the destination apicid of
238 * interrupts potentially passing through the UV HUB. This prevents
239 * a deadlock between interrupts and IO port operations.
240 */
uv_set_apicid_hibit(void)241 static void __init uv_set_apicid_hibit(void)
242 {
243 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
244
245 if (is_uv1_hub()) {
246 apicid_mask.v = uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
247 uv_apicid_hibits = apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
248 }
249 }
250
uv_acpi_madt_oem_check(char * oem_id,char * oem_table_id)251 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
252 {
253 int pnodeid;
254 int uv_apic;
255
256 if (strncmp(oem_id, "SGI", 3) != 0) {
257 if (strncmp(oem_id, "NSGI", 4) == 0) {
258 uv_hubless_system = true;
259 pr_info("UV: OEM IDs %s/%s, HUBLESS\n",
260 oem_id, oem_table_id);
261 }
262 return 0;
263 }
264
265 if (numa_off) {
266 pr_err("UV: NUMA is off, disabling UV support\n");
267 return 0;
268 }
269
270 /* Set up early hub type field in uv_hub_info for Node 0 */
271 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
272
273 /*
274 * Determine UV arch type.
275 * SGI: UV100/1000
276 * SGI2: UV2000/3000
277 * SGI3: UV300 (truncated to 4 chars because of different varieties)
278 * SGI4: UV400 (truncated to 4 chars because of different varieties)
279 */
280 uv_hub_info->hub_revision =
281 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
282 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
283 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
284 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
285
286 if (uv_hub_info->hub_revision == 0)
287 goto badbios;
288
289 pnodeid = early_get_pnodeid();
290 early_get_apic_socketid_shift();
291
292 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
293 x86_platform.nmi_init = uv_nmi_init;
294
295 if (!strcmp(oem_table_id, "UVX")) {
296 /* This is the most common hardware variant: */
297 uv_system_type = UV_X2APIC;
298 uv_apic = 0;
299
300 } else if (!strcmp(oem_table_id, "UVH")) {
301 /* Only UV1 systems: */
302 uv_system_type = UV_NON_UNIQUE_APIC;
303 x86_platform.legacy.warm_reset = 0;
304 __this_cpu_write(x2apic_extra_bits, pnodeid << uvh_apicid.s.pnode_shift);
305 uv_set_apicid_hibit();
306 uv_apic = 1;
307
308 } else if (!strcmp(oem_table_id, "UVL")) {
309 /* Only used for very small systems: */
310 uv_system_type = UV_LEGACY_APIC;
311 uv_apic = 0;
312
313 } else {
314 goto badbios;
315 }
316
317 pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", oem_id, oem_table_id, uv_system_type, uv_min_hub_revision_id, uv_apic);
318 uv_tsc_check_sync();
319
320 return uv_apic;
321
322 badbios:
323 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
324 pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
325 BUG();
326 }
327
get_uv_system_type(void)328 enum uv_system_type get_uv_system_type(void)
329 {
330 return uv_system_type;
331 }
332
is_uv_system(void)333 int is_uv_system(void)
334 {
335 return uv_system_type != UV_NONE;
336 }
337 EXPORT_SYMBOL_GPL(is_uv_system);
338
is_uv_hubless(void)339 int is_uv_hubless(void)
340 {
341 return uv_hubless_system;
342 }
343 EXPORT_SYMBOL_GPL(is_uv_hubless);
344
345 void **__uv_hub_info_list;
346 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
347
348 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
349 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
350
351 short uv_possible_blades;
352 EXPORT_SYMBOL_GPL(uv_possible_blades);
353
354 unsigned long sn_rtc_cycles_per_second;
355 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
356
357 /* The following values are used for the per node hub info struct */
358 static __initdata unsigned short *_node_to_pnode;
359 static __initdata unsigned short _min_socket, _max_socket;
360 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
361 static __initdata struct uv_gam_range_entry *uv_gre_table;
362 static __initdata struct uv_gam_parameters *uv_gp_table;
363 static __initdata unsigned short *_socket_to_node;
364 static __initdata unsigned short *_socket_to_pnode;
365 static __initdata unsigned short *_pnode_to_socket;
366
367 static __initdata struct uv_gam_range_s *_gr_table;
368
369 #define SOCK_EMPTY ((unsigned short)~0)
370
uv_hub_info_version(void)371 extern int uv_hub_info_version(void)
372 {
373 return UV_HUB_INFO_VERSION;
374 }
375 EXPORT_SYMBOL(uv_hub_info_version);
376
377 /* Default UV memory block size is 2GB */
378 static unsigned long mem_block_size __initdata = (2UL << 30);
379
380 /* Kernel parameter to specify UV mem block size */
parse_mem_block_size(char * ptr)381 static int __init parse_mem_block_size(char *ptr)
382 {
383 unsigned long size = memparse(ptr, NULL);
384
385 /* Size will be rounded down by set_block_size() below */
386 mem_block_size = size;
387 return 0;
388 }
389 early_param("uv_memblksize", parse_mem_block_size);
390
adj_blksize(u32 lgre)391 static __init int adj_blksize(u32 lgre)
392 {
393 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
394 unsigned long size;
395
396 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
397 if (IS_ALIGNED(base, size))
398 break;
399
400 if (size >= mem_block_size)
401 return 0;
402
403 mem_block_size = size;
404 return 1;
405 }
406
set_block_size(void)407 static __init void set_block_size(void)
408 {
409 unsigned int order = ffs(mem_block_size);
410
411 if (order) {
412 /* adjust for ffs return of 1..64 */
413 set_memory_block_size_order(order - 1);
414 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
415 } else {
416 /* bad or zero value, default to 1UL << 31 (2GB) */
417 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
418 set_memory_block_size_order(31);
419 }
420 }
421
422 /* Build GAM range lookup table: */
build_uv_gr_table(void)423 static __init void build_uv_gr_table(void)
424 {
425 struct uv_gam_range_entry *gre = uv_gre_table;
426 struct uv_gam_range_s *grt;
427 unsigned long last_limit = 0, ram_limit = 0;
428 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
429
430 if (!gre)
431 return;
432
433 bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
434 grt = kzalloc(bytes, GFP_KERNEL);
435 BUG_ON(!grt);
436 _gr_table = grt;
437
438 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
439 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
440 if (!ram_limit) {
441 /* Mark hole between RAM/non-RAM: */
442 ram_limit = last_limit;
443 last_limit = gre->limit;
444 lsid++;
445 continue;
446 }
447 last_limit = gre->limit;
448 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
449 continue;
450 }
451 if (_max_socket < gre->sockid) {
452 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
453 continue;
454 }
455 sid = gre->sockid - _min_socket;
456 if (lsid < sid) {
457 /* New range: */
458 grt = &_gr_table[indx];
459 grt->base = lindx;
460 grt->nasid = gre->nasid;
461 grt->limit = last_limit = gre->limit;
462 lsid = sid;
463 lindx = indx++;
464 continue;
465 }
466 /* Update range: */
467 if (lsid == sid && !ram_limit) {
468 /* .. if contiguous: */
469 if (grt->limit == last_limit) {
470 grt->limit = last_limit = gre->limit;
471 continue;
472 }
473 }
474 /* Non-contiguous RAM range: */
475 if (!ram_limit) {
476 grt++;
477 grt->base = lindx;
478 grt->nasid = gre->nasid;
479 grt->limit = last_limit = gre->limit;
480 continue;
481 }
482 /* Non-contiguous/non-RAM: */
483 grt++;
484 /* base is this entry */
485 grt->base = grt - _gr_table;
486 grt->nasid = gre->nasid;
487 grt->limit = last_limit = gre->limit;
488 lsid++;
489 }
490
491 /* Shorten table if possible */
492 grt++;
493 i = grt - _gr_table;
494 if (i < _gr_table_len) {
495 void *ret;
496
497 bytes = i * sizeof(struct uv_gam_range_s);
498 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
499 if (ret) {
500 _gr_table = ret;
501 _gr_table_len = i;
502 }
503 }
504
505 /* Display resultant GAM range table: */
506 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
507 unsigned long start, end;
508 int gb = grt->base;
509
510 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
511 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
512
513 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
514 }
515 }
516
uv_wakeup_secondary(int phys_apicid,unsigned long start_rip)517 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
518 {
519 unsigned long val;
520 int pnode;
521
522 pnode = uv_apicid_to_pnode(phys_apicid);
523 phys_apicid |= uv_apicid_hibits;
524
525 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
526 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
527 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
528 APIC_DM_INIT;
529
530 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
531
532 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
533 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
534 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
535 APIC_DM_STARTUP;
536
537 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
538
539 return 0;
540 }
541
uv_send_IPI_one(int cpu,int vector)542 static void uv_send_IPI_one(int cpu, int vector)
543 {
544 unsigned long apicid;
545 int pnode;
546
547 apicid = per_cpu(x86_cpu_to_apicid, cpu);
548 pnode = uv_apicid_to_pnode(apicid);
549 uv_hub_send_ipi(pnode, apicid, vector);
550 }
551
uv_send_IPI_mask(const struct cpumask * mask,int vector)552 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
553 {
554 unsigned int cpu;
555
556 for_each_cpu(cpu, mask)
557 uv_send_IPI_one(cpu, vector);
558 }
559
uv_send_IPI_mask_allbutself(const struct cpumask * mask,int vector)560 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
561 {
562 unsigned int this_cpu = smp_processor_id();
563 unsigned int cpu;
564
565 for_each_cpu(cpu, mask) {
566 if (cpu != this_cpu)
567 uv_send_IPI_one(cpu, vector);
568 }
569 }
570
uv_send_IPI_allbutself(int vector)571 static void uv_send_IPI_allbutself(int vector)
572 {
573 unsigned int this_cpu = smp_processor_id();
574 unsigned int cpu;
575
576 for_each_online_cpu(cpu) {
577 if (cpu != this_cpu)
578 uv_send_IPI_one(cpu, vector);
579 }
580 }
581
uv_send_IPI_all(int vector)582 static void uv_send_IPI_all(int vector)
583 {
584 uv_send_IPI_mask(cpu_online_mask, vector);
585 }
586
uv_apic_id_valid(u32 apicid)587 static int uv_apic_id_valid(u32 apicid)
588 {
589 return 1;
590 }
591
uv_apic_id_registered(void)592 static int uv_apic_id_registered(void)
593 {
594 return 1;
595 }
596
uv_init_apic_ldr(void)597 static void uv_init_apic_ldr(void)
598 {
599 }
600
apic_uv_calc_apicid(unsigned int cpu)601 static u32 apic_uv_calc_apicid(unsigned int cpu)
602 {
603 return apic_default_calc_apicid(cpu) | uv_apicid_hibits;
604 }
605
x2apic_get_apic_id(unsigned long x)606 static unsigned int x2apic_get_apic_id(unsigned long x)
607 {
608 unsigned int id;
609
610 WARN_ON(preemptible() && num_online_cpus() > 1);
611 id = x | __this_cpu_read(x2apic_extra_bits);
612
613 return id;
614 }
615
set_apic_id(unsigned int id)616 static u32 set_apic_id(unsigned int id)
617 {
618 /* CHECKME: Do we need to mask out the xapic extra bits? */
619 return id;
620 }
621
uv_read_apic_id(void)622 static unsigned int uv_read_apic_id(void)
623 {
624 return x2apic_get_apic_id(apic_read(APIC_ID));
625 }
626
uv_phys_pkg_id(int initial_apicid,int index_msb)627 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
628 {
629 return uv_read_apic_id() >> index_msb;
630 }
631
uv_send_IPI_self(int vector)632 static void uv_send_IPI_self(int vector)
633 {
634 apic_write(APIC_SELF_IPI, vector);
635 }
636
uv_probe(void)637 static int uv_probe(void)
638 {
639 return apic == &apic_x2apic_uv_x;
640 }
641
642 static struct apic apic_x2apic_uv_x __ro_after_init = {
643
644 .name = "UV large system",
645 .probe = uv_probe,
646 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
647 .apic_id_valid = uv_apic_id_valid,
648 .apic_id_registered = uv_apic_id_registered,
649
650 .irq_delivery_mode = dest_Fixed,
651 .irq_dest_mode = 0, /* Physical */
652
653 .disable_esr = 0,
654 .dest_logical = APIC_DEST_LOGICAL,
655 .check_apicid_used = NULL,
656
657 .init_apic_ldr = uv_init_apic_ldr,
658
659 .ioapic_phys_id_map = NULL,
660 .setup_apic_routing = NULL,
661 .cpu_present_to_apicid = default_cpu_present_to_apicid,
662 .apicid_to_cpu_present = NULL,
663 .check_phys_apicid_present = default_check_phys_apicid_present,
664 .phys_pkg_id = uv_phys_pkg_id,
665
666 .get_apic_id = x2apic_get_apic_id,
667 .set_apic_id = set_apic_id,
668
669 .calc_dest_apicid = apic_uv_calc_apicid,
670
671 .send_IPI = uv_send_IPI_one,
672 .send_IPI_mask = uv_send_IPI_mask,
673 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
674 .send_IPI_allbutself = uv_send_IPI_allbutself,
675 .send_IPI_all = uv_send_IPI_all,
676 .send_IPI_self = uv_send_IPI_self,
677
678 .wakeup_secondary_cpu = uv_wakeup_secondary,
679 .inquire_remote_apic = NULL,
680
681 .read = native_apic_msr_read,
682 .write = native_apic_msr_write,
683 .eoi_write = native_apic_msr_eoi_write,
684 .icr_read = native_x2apic_icr_read,
685 .icr_write = native_x2apic_icr_write,
686 .wait_icr_idle = native_x2apic_wait_icr_idle,
687 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
688 };
689
set_x2apic_extra_bits(int pnode)690 static void set_x2apic_extra_bits(int pnode)
691 {
692 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
693 }
694
695 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
696 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
697
get_lowmem_redirect(unsigned long * base,unsigned long * size)698 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
699 {
700 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
701 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
702 unsigned long m_redirect;
703 unsigned long m_overlay;
704 int i;
705
706 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
707 switch (i) {
708 case 0:
709 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
710 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
711 break;
712 case 1:
713 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
714 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
715 break;
716 case 2:
717 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
718 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
719 break;
720 }
721 alias.v = uv_read_local_mmr(m_overlay);
722 if (alias.s.enable && alias.s.base == 0) {
723 *size = (1UL << alias.s.m_alias);
724 redirect.v = uv_read_local_mmr(m_redirect);
725 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
726 return;
727 }
728 }
729 *base = *size = 0;
730 }
731
732 enum map_type {map_wb, map_uc};
733
map_high(char * id,unsigned long base,int pshift,int bshift,int max_pnode,enum map_type map_type)734 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
735 {
736 unsigned long bytes, paddr;
737
738 paddr = base << pshift;
739 bytes = (1UL << bshift) * (max_pnode + 1);
740 if (!paddr) {
741 pr_info("UV: Map %s_HI base address NULL\n", id);
742 return;
743 }
744 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
745 if (map_type == map_uc)
746 init_extra_mapping_uc(paddr, bytes);
747 else
748 init_extra_mapping_wb(paddr, bytes);
749 }
750
map_gru_distributed(unsigned long c)751 static __init void map_gru_distributed(unsigned long c)
752 {
753 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
754 u64 paddr;
755 unsigned long bytes;
756 int nid;
757
758 gru.v = c;
759
760 /* Only base bits 42:28 relevant in dist mode */
761 gru_dist_base = gru.v & 0x000007fff0000000UL;
762 if (!gru_dist_base) {
763 pr_info("UV: Map GRU_DIST base address NULL\n");
764 return;
765 }
766
767 bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
768 gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
769 gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
770 gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
771
772 for_each_online_node(nid) {
773 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
774 gru_dist_base;
775 init_extra_mapping_wb(paddr, bytes);
776 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
777 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
778 }
779
780 /* Save upper (63:M) bits of address only for is_GRU_range */
781 gru_first_node_paddr &= gru_dist_umask;
782 gru_last_node_paddr &= gru_dist_umask;
783
784 pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n", gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
785 }
786
map_gru_high(int max_pnode)787 static __init void map_gru_high(int max_pnode)
788 {
789 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
790 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
791 unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
792 unsigned long base;
793
794 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
795 if (!gru.s.enable) {
796 pr_info("UV: GRU disabled\n");
797 return;
798 }
799
800 /* Only UV3 has distributed GRU mode */
801 if (is_uv3_hub() && gru.s3.mode) {
802 map_gru_distributed(gru.v);
803 return;
804 }
805
806 base = (gru.v & mask) >> shift;
807 map_high("GRU", base, shift, shift, max_pnode, map_wb);
808 gru_start_paddr = ((u64)base << shift);
809 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
810 }
811
map_mmr_high(int max_pnode)812 static __init void map_mmr_high(int max_pnode)
813 {
814 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
815 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
816
817 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
818 if (mmr.s.enable)
819 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
820 else
821 pr_info("UV: MMR disabled\n");
822 }
823
824 /* UV3/4 have identical MMIOH overlay configs, UV4A is slightly different */
map_mmioh_high_uv34(int index,int min_pnode,int max_pnode)825 static __init void map_mmioh_high_uv34(int index, int min_pnode, int max_pnode)
826 {
827 unsigned long overlay;
828 unsigned long mmr;
829 unsigned long base;
830 unsigned long nasid_mask;
831 unsigned long m_overlay;
832 int i, n, shift, m_io, max_io;
833 int nasid, lnasid, fi, li;
834 char *id;
835
836 if (index == 0) {
837 id = "MMIOH0";
838 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR;
839 overlay = uv_read_local_mmr(m_overlay);
840 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK;
841 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR;
842 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK)
843 >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
844 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
845 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
846 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK;
847 } else {
848 id = "MMIOH1";
849 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR;
850 overlay = uv_read_local_mmr(m_overlay);
851 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK;
852 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR;
853 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK)
854 >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
855 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
856 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH;
857 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK;
858 }
859 pr_info("UV: %s overlay 0x%lx base:0x%lx m_io:%d\n", id, overlay, base, m_io);
860 if (!(overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK)) {
861 pr_info("UV: %s disabled\n", id);
862 return;
863 }
864
865 /* Convert to NASID: */
866 min_pnode *= 2;
867 max_pnode *= 2;
868 max_io = lnasid = fi = li = -1;
869
870 for (i = 0; i < n; i++) {
871 unsigned long m_redirect = mmr + i * 8;
872 unsigned long redirect = uv_read_local_mmr(m_redirect);
873
874 nasid = redirect & nasid_mask;
875 if (i == 0)
876 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
877 id, redirect, m_redirect, nasid);
878
879 /* Invalid NASID: */
880 if (nasid < min_pnode || max_pnode < nasid)
881 nasid = -1;
882
883 if (nasid == lnasid) {
884 li = i;
885 /* Last entry check: */
886 if (i != n-1)
887 continue;
888 }
889
890 /* Check if we have a cached (or last) redirect to print: */
891 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
892 unsigned long addr1, addr2;
893 int f, l;
894
895 if (lnasid == -1) {
896 f = l = i;
897 lnasid = nasid;
898 } else {
899 f = fi;
900 l = li;
901 }
902 addr1 = (base << shift) + f * (1ULL << m_io);
903 addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
904 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2);
905 if (max_io < l)
906 max_io = l;
907 }
908 fi = li = i;
909 lnasid = nasid;
910 }
911
912 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io);
913
914 if (max_io >= 0)
915 map_high(id, base, shift, m_io, max_io, map_uc);
916 }
917
map_mmioh_high(int min_pnode,int max_pnode)918 static __init void map_mmioh_high(int min_pnode, int max_pnode)
919 {
920 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
921 unsigned long mmr, base;
922 int shift, enable, m_io, n_io;
923
924 if (is_uv3_hub() || is_uv4_hub()) {
925 /* Map both MMIOH regions: */
926 map_mmioh_high_uv34(0, min_pnode, max_pnode);
927 map_mmioh_high_uv34(1, min_pnode, max_pnode);
928 return;
929 }
930
931 if (is_uv1_hub()) {
932 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
933 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
934 mmioh.v = uv_read_local_mmr(mmr);
935 enable = !!mmioh.s1.enable;
936 base = mmioh.s1.base;
937 m_io = mmioh.s1.m_io;
938 n_io = mmioh.s1.n_io;
939 } else if (is_uv2_hub()) {
940 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
941 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
942 mmioh.v = uv_read_local_mmr(mmr);
943 enable = !!mmioh.s2.enable;
944 base = mmioh.s2.base;
945 m_io = mmioh.s2.m_io;
946 n_io = mmioh.s2.n_io;
947 } else {
948 return;
949 }
950
951 if (enable) {
952 max_pnode &= (1 << n_io) - 1;
953 pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", base, shift, m_io, n_io, max_pnode);
954 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
955 } else {
956 pr_info("UV: MMIOH disabled\n");
957 }
958 }
959
map_low_mmrs(void)960 static __init void map_low_mmrs(void)
961 {
962 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
963 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
964 }
965
uv_rtc_init(void)966 static __init void uv_rtc_init(void)
967 {
968 long status;
969 u64 ticks_per_sec;
970
971 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
972
973 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
974 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
975
976 /* BIOS gives wrong value for clock frequency, so guess: */
977 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
978 } else {
979 sn_rtc_cycles_per_second = ticks_per_sec;
980 }
981 }
982
983 /*
984 * percpu heartbeat timer
985 */
uv_heartbeat(struct timer_list * timer)986 static void uv_heartbeat(struct timer_list *timer)
987 {
988 unsigned char bits = uv_scir_info->state;
989
990 /* Flip heartbeat bit: */
991 bits ^= SCIR_CPU_HEARTBEAT;
992
993 /* Is this CPU idle? */
994 if (idle_cpu(raw_smp_processor_id()))
995 bits &= ~SCIR_CPU_ACTIVITY;
996 else
997 bits |= SCIR_CPU_ACTIVITY;
998
999 /* Update system controller interface reg: */
1000 uv_set_scir_bits(bits);
1001
1002 /* Enable next timer period: */
1003 mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
1004 }
1005
uv_heartbeat_enable(unsigned int cpu)1006 static int uv_heartbeat_enable(unsigned int cpu)
1007 {
1008 while (!uv_cpu_scir_info(cpu)->enabled) {
1009 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
1010
1011 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
1012 timer_setup(timer, uv_heartbeat, TIMER_PINNED);
1013 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
1014 add_timer_on(timer, cpu);
1015 uv_cpu_scir_info(cpu)->enabled = 1;
1016
1017 /* Also ensure that boot CPU is enabled: */
1018 cpu = 0;
1019 }
1020 return 0;
1021 }
1022
1023 #ifdef CONFIG_HOTPLUG_CPU
uv_heartbeat_disable(unsigned int cpu)1024 static int uv_heartbeat_disable(unsigned int cpu)
1025 {
1026 if (uv_cpu_scir_info(cpu)->enabled) {
1027 uv_cpu_scir_info(cpu)->enabled = 0;
1028 del_timer(&uv_cpu_scir_info(cpu)->timer);
1029 }
1030 uv_set_cpu_scir_bits(cpu, 0xff);
1031 return 0;
1032 }
1033
uv_scir_register_cpu_notifier(void)1034 static __init void uv_scir_register_cpu_notifier(void)
1035 {
1036 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/x2apic-uvx:online",
1037 uv_heartbeat_enable, uv_heartbeat_disable);
1038 }
1039
1040 #else /* !CONFIG_HOTPLUG_CPU */
1041
uv_scir_register_cpu_notifier(void)1042 static __init void uv_scir_register_cpu_notifier(void)
1043 {
1044 }
1045
uv_init_heartbeat(void)1046 static __init int uv_init_heartbeat(void)
1047 {
1048 int cpu;
1049
1050 if (is_uv_system()) {
1051 for_each_online_cpu(cpu)
1052 uv_heartbeat_enable(cpu);
1053 }
1054
1055 return 0;
1056 }
1057
1058 late_initcall(uv_init_heartbeat);
1059
1060 #endif /* !CONFIG_HOTPLUG_CPU */
1061
1062 /* Direct Legacy VGA I/O traffic to designated IOH */
uv_set_vga_state(struct pci_dev * pdev,bool decode,unsigned int command_bits,u32 flags)1063 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
1064 {
1065 int domain, bus, rc;
1066
1067 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1068 return 0;
1069
1070 if ((command_bits & PCI_COMMAND_IO) == 0)
1071 return 0;
1072
1073 domain = pci_domain_nr(pdev->bus);
1074 bus = pdev->bus->number;
1075
1076 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1077
1078 return rc;
1079 }
1080
1081 /*
1082 * Called on each CPU to initialize the per_cpu UV data area.
1083 * FIXME: hotplug not supported yet
1084 */
uv_cpu_init(void)1085 void uv_cpu_init(void)
1086 {
1087 /* CPU 0 initialization will be done via uv_system_init. */
1088 if (smp_processor_id() == 0)
1089 return;
1090
1091 uv_hub_info->nr_online_cpus++;
1092
1093 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
1094 set_x2apic_extra_bits(uv_hub_info->pnode);
1095 }
1096
1097 struct mn {
1098 unsigned char m_val;
1099 unsigned char n_val;
1100 unsigned char m_shift;
1101 unsigned char n_lshift;
1102 };
1103
get_mn(struct mn * mnp)1104 static void get_mn(struct mn *mnp)
1105 {
1106 union uvh_rh_gam_config_mmr_u m_n_config;
1107 union uv3h_gr0_gam_gr_config_u m_gr_config;
1108
1109 /* Make sure the whole structure is well initialized: */
1110 memset(mnp, 0, sizeof(*mnp));
1111
1112 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
1113 mnp->n_val = m_n_config.s.n_skt;
1114
1115 if (is_uv4_hub()) {
1116 mnp->m_val = 0;
1117 mnp->n_lshift = 0;
1118 } else if (is_uv3_hub()) {
1119 mnp->m_val = m_n_config.s3.m_skt;
1120 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
1121 mnp->n_lshift = m_gr_config.s3.m_skt;
1122 } else if (is_uv2_hub()) {
1123 mnp->m_val = m_n_config.s2.m_skt;
1124 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1125 } else if (is_uv1_hub()) {
1126 mnp->m_val = m_n_config.s1.m_skt;
1127 mnp->n_lshift = mnp->m_val;
1128 }
1129 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1130 }
1131
uv_init_hub_info(struct uv_hub_info_s * hi)1132 static void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1133 {
1134 union uvh_node_id_u node_id;
1135 struct mn mn;
1136
1137 get_mn(&mn);
1138 hi->gpa_mask = mn.m_val ?
1139 (1UL << (mn.m_val + mn.n_val)) - 1 :
1140 (1UL << uv_cpuid.gpa_shift) - 1;
1141
1142 hi->m_val = mn.m_val;
1143 hi->n_val = mn.n_val;
1144 hi->m_shift = mn.m_shift;
1145 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
1146 hi->hub_revision = uv_hub_info->hub_revision;
1147 hi->pnode_mask = uv_cpuid.pnode_mask;
1148 hi->min_pnode = _min_pnode;
1149 hi->min_socket = _min_socket;
1150 hi->pnode_to_socket = _pnode_to_socket;
1151 hi->socket_to_node = _socket_to_node;
1152 hi->socket_to_pnode = _socket_to_pnode;
1153 hi->gr_table_len = _gr_table_len;
1154 hi->gr_table = _gr_table;
1155
1156 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
1157 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1158 hi->gnode_extra = (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1159 if (mn.m_val)
1160 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1161
1162 if (uv_gp_table) {
1163 hi->global_mmr_base = uv_gp_table->mmr_base;
1164 hi->global_mmr_shift = uv_gp_table->mmr_shift;
1165 hi->global_gru_base = uv_gp_table->gru_base;
1166 hi->global_gru_shift = uv_gp_table->gru_shift;
1167 hi->gpa_shift = uv_gp_table->gpa_shift;
1168 hi->gpa_mask = (1UL << hi->gpa_shift) - 1;
1169 } else {
1170 hi->global_mmr_base = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & ~UV_MMR_ENABLE;
1171 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1172 }
1173
1174 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1175
1176 hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1177
1178 /* Show system specific info: */
1179 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1180 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1181 pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift, hi->global_gru_base, hi->global_gru_shift);
1182 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1183 }
1184
decode_gam_params(unsigned long ptr)1185 static void __init decode_gam_params(unsigned long ptr)
1186 {
1187 uv_gp_table = (struct uv_gam_parameters *)ptr;
1188
1189 pr_info("UV: GAM Params...\n");
1190 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1191 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1192 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1193 uv_gp_table->gpa_shift);
1194 }
1195
decode_gam_rng_tbl(unsigned long ptr)1196 static void __init decode_gam_rng_tbl(unsigned long ptr)
1197 {
1198 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1199 unsigned long lgre = 0;
1200 int index = 0;
1201 int sock_min = 999999, pnode_min = 99999;
1202 int sock_max = -1, pnode_max = -1;
1203
1204 uv_gre_table = gre;
1205 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1206 unsigned long size = ((unsigned long)(gre->limit - lgre)
1207 << UV_GAM_RANGE_SHFT);
1208 int order = 0;
1209 char suffix[] = " KMGTPE";
1210 int flag = ' ';
1211
1212 while (size > 9999 && order < sizeof(suffix)) {
1213 size /= 1024;
1214 order++;
1215 }
1216
1217 /* adjust max block size to current range start */
1218 if (gre->type == 1 || gre->type == 2)
1219 if (adj_blksize(lgre))
1220 flag = '*';
1221
1222 if (!index) {
1223 pr_info("UV: GAM Range Table...\n");
1224 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1225 }
1226 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n",
1227 index++,
1228 (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1229 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1230 flag, size, suffix[order],
1231 gre->type, gre->nasid, gre->sockid, gre->pnode);
1232
1233 /* update to next range start */
1234 lgre = gre->limit;
1235 if (sock_min > gre->sockid)
1236 sock_min = gre->sockid;
1237 if (sock_max < gre->sockid)
1238 sock_max = gre->sockid;
1239 if (pnode_min > gre->pnode)
1240 pnode_min = gre->pnode;
1241 if (pnode_max < gre->pnode)
1242 pnode_max = gre->pnode;
1243 }
1244 _min_socket = sock_min;
1245 _max_socket = sock_max;
1246 _min_pnode = pnode_min;
1247 _max_pnode = pnode_max;
1248 _gr_table_len = index;
1249
1250 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1251 }
1252
decode_uv_systab(void)1253 static int __init decode_uv_systab(void)
1254 {
1255 struct uv_systab *st;
1256 int i;
1257
1258 if (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)
1259 return 0; /* No extended UVsystab required */
1260
1261 st = uv_systab;
1262 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1263 int rev = st ? st->revision : 0;
1264
1265 pr_err("UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", rev, UV_SYSTAB_VERSION_UV4_LATEST);
1266 pr_err("UV: Cannot support UV operations, switching to generic PC\n");
1267 uv_system_type = UV_NONE;
1268
1269 return -EINVAL;
1270 }
1271
1272 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1273 unsigned long ptr = st->entry[i].offset;
1274
1275 if (!ptr)
1276 continue;
1277
1278 ptr = ptr + (unsigned long)st;
1279
1280 switch (st->entry[i].type) {
1281 case UV_SYSTAB_TYPE_GAM_PARAMS:
1282 decode_gam_params(ptr);
1283 break;
1284
1285 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1286 decode_gam_rng_tbl(ptr);
1287 break;
1288 }
1289 }
1290 return 0;
1291 }
1292
1293 /*
1294 * Set up physical blade translations from UVH_NODE_PRESENT_TABLE
1295 * .. NB: UVH_NODE_PRESENT_TABLE is going away,
1296 * .. being replaced by GAM Range Table
1297 */
boot_init_possible_blades(struct uv_hub_info_s * hub_info)1298 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1299 {
1300 int i, uv_pb = 0;
1301
1302 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1303 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1304 unsigned long np;
1305
1306 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1307 if (np)
1308 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1309
1310 uv_pb += hweight64(np);
1311 }
1312 if (uv_possible_blades != uv_pb)
1313 uv_possible_blades = uv_pb;
1314 }
1315
build_socket_tables(void)1316 static void __init build_socket_tables(void)
1317 {
1318 struct uv_gam_range_entry *gre = uv_gre_table;
1319 int num, nump;
1320 int cpu, i, lnid;
1321 int minsock = _min_socket;
1322 int maxsock = _max_socket;
1323 int minpnode = _min_pnode;
1324 int maxpnode = _max_pnode;
1325 size_t bytes;
1326
1327 if (!gre) {
1328 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
1329 pr_info("UV: No UVsystab socket table, ignoring\n");
1330 return;
1331 }
1332 pr_crit("UV: Error: UVsystab address translations not available!\n");
1333 BUG();
1334 }
1335
1336 /* Build socket id -> node id, pnode */
1337 num = maxsock - minsock + 1;
1338 bytes = num * sizeof(_socket_to_node[0]);
1339 _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1340 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1341
1342 nump = maxpnode - minpnode + 1;
1343 bytes = nump * sizeof(_pnode_to_socket[0]);
1344 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1345 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1346
1347 for (i = 0; i < num; i++)
1348 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1349
1350 for (i = 0; i < nump; i++)
1351 _pnode_to_socket[i] = SOCK_EMPTY;
1352
1353 /* Fill in pnode/node/addr conversion list values: */
1354 pr_info("UV: GAM Building socket/pnode conversion tables\n");
1355 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1356 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1357 continue;
1358 i = gre->sockid - minsock;
1359 /* Duplicate: */
1360 if (_socket_to_pnode[i] != SOCK_EMPTY)
1361 continue;
1362 _socket_to_pnode[i] = gre->pnode;
1363
1364 i = gre->pnode - minpnode;
1365 _pnode_to_socket[i] = gre->sockid;
1366
1367 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1368 gre->sockid, gre->type, gre->nasid,
1369 _socket_to_pnode[gre->sockid - minsock],
1370 _pnode_to_socket[gre->pnode - minpnode]);
1371 }
1372
1373 /* Set socket -> node values: */
1374 lnid = NUMA_NO_NODE;
1375 for_each_present_cpu(cpu) {
1376 int nid = cpu_to_node(cpu);
1377 int apicid, sockid;
1378
1379 if (lnid == nid)
1380 continue;
1381 lnid = nid;
1382 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1383 sockid = apicid >> uv_cpuid.socketid_shift;
1384 _socket_to_node[sockid - minsock] = nid;
1385 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1386 sockid, apicid, nid);
1387 }
1388
1389 /* Set up physical blade to pnode translation from GAM Range Table: */
1390 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1391 _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1392 BUG_ON(!_node_to_pnode);
1393
1394 for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1395 unsigned short sockid;
1396
1397 for (sockid = minsock; sockid <= maxsock; sockid++) {
1398 if (lnid == _socket_to_node[sockid - minsock]) {
1399 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1400 break;
1401 }
1402 }
1403 if (sockid > maxsock) {
1404 pr_err("UV: socket for node %d not found!\n", lnid);
1405 BUG();
1406 }
1407 }
1408
1409 /*
1410 * If socket id == pnode or socket id == node for all nodes,
1411 * system runs faster by removing corresponding conversion table.
1412 */
1413 pr_info("UV: Checking socket->node/pnode for identity maps\n");
1414 if (minsock == 0) {
1415 for (i = 0; i < num; i++)
1416 if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1417 break;
1418 if (i >= num) {
1419 kfree(_socket_to_node);
1420 _socket_to_node = NULL;
1421 pr_info("UV: 1:1 socket_to_node table removed\n");
1422 }
1423 }
1424 if (minsock == minpnode) {
1425 for (i = 0; i < num; i++)
1426 if (_socket_to_pnode[i] != SOCK_EMPTY &&
1427 _socket_to_pnode[i] != i + minpnode)
1428 break;
1429 if (i >= num) {
1430 kfree(_socket_to_pnode);
1431 _socket_to_pnode = NULL;
1432 pr_info("UV: 1:1 socket_to_pnode table removed\n");
1433 }
1434 }
1435 }
1436
uv_system_init_hub(void)1437 static void __init uv_system_init_hub(void)
1438 {
1439 struct uv_hub_info_s hub_info = {0};
1440 int bytes, cpu, nodeid;
1441 unsigned short min_pnode = 9999, max_pnode = 0;
1442 char *hub = is_uv4_hub() ? "UV400" :
1443 is_uv3_hub() ? "UV300" :
1444 is_uv2_hub() ? "UV2000/3000" :
1445 is_uv1_hub() ? "UV100/1000" : NULL;
1446
1447 if (!hub) {
1448 pr_err("UV: Unknown/unsupported UV hub\n");
1449 return;
1450 }
1451 pr_info("UV: Found %s hub\n", hub);
1452
1453 map_low_mmrs();
1454
1455 /* Get uv_systab for decoding: */
1456 uv_bios_init();
1457
1458 /* If there's an UVsystab problem then abort UV init: */
1459 if (decode_uv_systab() < 0)
1460 return;
1461
1462 build_socket_tables();
1463 build_uv_gr_table();
1464 set_block_size();
1465 uv_init_hub_info(&hub_info);
1466 uv_possible_blades = num_possible_nodes();
1467 if (!_node_to_pnode)
1468 boot_init_possible_blades(&hub_info);
1469
1470 /* uv_num_possible_blades() is really the hub count: */
1471 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1472
1473 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1474 hub_info.coherency_domain_number = sn_coherency_id;
1475 uv_rtc_init();
1476
1477 bytes = sizeof(void *) * uv_num_possible_blades();
1478 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1479 BUG_ON(!__uv_hub_info_list);
1480
1481 bytes = sizeof(struct uv_hub_info_s);
1482 for_each_node(nodeid) {
1483 struct uv_hub_info_s *new_hub;
1484
1485 if (__uv_hub_info_list[nodeid]) {
1486 pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1487 BUG();
1488 }
1489
1490 /* Allocate new per hub info list */
1491 new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1492 BUG_ON(!new_hub);
1493 __uv_hub_info_list[nodeid] = new_hub;
1494 new_hub = uv_hub_info_list(nodeid);
1495 BUG_ON(!new_hub);
1496 *new_hub = hub_info;
1497
1498 /* Use information from GAM table if available: */
1499 if (_node_to_pnode)
1500 new_hub->pnode = _node_to_pnode[nodeid];
1501 else /* Or fill in during CPU loop: */
1502 new_hub->pnode = 0xffff;
1503
1504 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1505 new_hub->memory_nid = NUMA_NO_NODE;
1506 new_hub->nr_possible_cpus = 0;
1507 new_hub->nr_online_cpus = 0;
1508 }
1509
1510 /* Initialize per CPU info: */
1511 for_each_possible_cpu(cpu) {
1512 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1513 int numa_node_id;
1514 unsigned short pnode;
1515
1516 nodeid = cpu_to_node(cpu);
1517 numa_node_id = numa_cpu_node(cpu);
1518 pnode = uv_apicid_to_pnode(apicid);
1519
1520 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1521 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1522 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE)
1523 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1524
1525 /* Init memoryless node: */
1526 if (nodeid != numa_node_id &&
1527 uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1528 uv_hub_info_list(numa_node_id)->pnode = pnode;
1529 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1530 uv_cpu_hub_info(cpu)->pnode = pnode;
1531
1532 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
1533 }
1534
1535 for_each_node(nodeid) {
1536 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1537
1538 /* Add pnode info for pre-GAM list nodes without CPUs: */
1539 if (pnode == 0xffff) {
1540 unsigned long paddr;
1541
1542 paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1543 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1544 uv_hub_info_list(nodeid)->pnode = pnode;
1545 }
1546 min_pnode = min(pnode, min_pnode);
1547 max_pnode = max(pnode, max_pnode);
1548 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1549 nodeid,
1550 uv_hub_info_list(nodeid)->pnode,
1551 uv_hub_info_list(nodeid)->nr_possible_cpus);
1552 }
1553
1554 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1555 map_gru_high(max_pnode);
1556 map_mmr_high(max_pnode);
1557 map_mmioh_high(min_pnode, max_pnode);
1558
1559 uv_nmi_setup();
1560 uv_cpu_init();
1561 uv_scir_register_cpu_notifier();
1562 proc_mkdir("sgi_uv", NULL);
1563
1564 /* Register Legacy VGA I/O redirection handler: */
1565 pci_register_set_vga_state(uv_set_vga_state);
1566
1567 /*
1568 * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
1569 * EFI is not enabled in the kdump kernel:
1570 */
1571 if (is_kdump_kernel())
1572 reboot_type = BOOT_ACPI;
1573 }
1574
1575 /*
1576 * There is a small amount of UV specific code needed to initialize a
1577 * UV system that does not have a "UV HUB" (referred to as "hubless").
1578 */
uv_system_init(void)1579 void __init uv_system_init(void)
1580 {
1581 if (likely(!is_uv_system() && !is_uv_hubless()))
1582 return;
1583
1584 if (is_uv_system())
1585 uv_system_init_hub();
1586 else
1587 uv_nmi_setup_hubless();
1588 }
1589
1590 apic_driver(apic_x2apic_uv_x);
1591
