1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 4 * 5 * Register definitions taken from original Realtek rtl8723au driver 6 */ 7 8 #include <asm/byteorder.h> 9 10 #define RTL8XXXU_DEBUG_REG_WRITE 0x01 11 #define RTL8XXXU_DEBUG_REG_READ 0x02 12 #define RTL8XXXU_DEBUG_RFREG_WRITE 0x04 13 #define RTL8XXXU_DEBUG_RFREG_READ 0x08 14 #define RTL8XXXU_DEBUG_CHANNEL 0x10 15 #define RTL8XXXU_DEBUG_TX 0x20 16 #define RTL8XXXU_DEBUG_TX_DUMP 0x40 17 #define RTL8XXXU_DEBUG_RX 0x80 18 #define RTL8XXXU_DEBUG_RX_DUMP 0x100 19 #define RTL8XXXU_DEBUG_USB 0x200 20 #define RTL8XXXU_DEBUG_KEY 0x400 21 #define RTL8XXXU_DEBUG_H2C 0x800 22 #define RTL8XXXU_DEBUG_ACTION 0x1000 23 #define RTL8XXXU_DEBUG_EFUSE 0x2000 24 #define RTL8XXXU_DEBUG_INTERRUPT 0x4000 25 26 #define RTW_USB_CONTROL_MSG_TIMEOUT 500 27 #define RTL8XXXU_MAX_REG_POLL 500 28 #define USB_INTR_CONTENT_LENGTH 56 29 30 #define RTL8XXXU_OUT_ENDPOINTS 4 31 32 #define REALTEK_USB_READ 0xc0 33 #define REALTEK_USB_WRITE 0x40 34 #define REALTEK_USB_CMD_REQ 0x05 35 #define REALTEK_USB_CMD_IDX 0x00 36 37 #define TX_TOTAL_PAGE_NUM 0xf8 38 #define TX_TOTAL_PAGE_NUM_8192E 0xf3 39 #define TX_TOTAL_PAGE_NUM_8723B 0xf7 40 /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */ 41 #define TX_PAGE_NUM_PUBQ 0xe7 42 #define TX_PAGE_NUM_HI_PQ 0x0c 43 #define TX_PAGE_NUM_LO_PQ 0x02 44 #define TX_PAGE_NUM_NORM_PQ 0x02 45 46 #define TX_PAGE_NUM_PUBQ_8192E 0xe7 47 #define TX_PAGE_NUM_HI_PQ_8192E 0x08 48 #define TX_PAGE_NUM_LO_PQ_8192E 0x0c 49 #define TX_PAGE_NUM_NORM_PQ_8192E 0x00 50 51 #define TX_PAGE_NUM_PUBQ_8723B 0xe7 52 #define TX_PAGE_NUM_HI_PQ_8723B 0x0c 53 #define TX_PAGE_NUM_LO_PQ_8723B 0x02 54 #define TX_PAGE_NUM_NORM_PQ_8723B 0x02 55 56 #define RTL_FW_PAGE_SIZE 4096 57 #define RTL8XXXU_FIRMWARE_POLL_MAX 1000 58 59 #define RTL8723A_CHANNEL_GROUPS 3 60 #define RTL8723A_MAX_RF_PATHS 2 61 #define RTL8723B_CHANNEL_GROUPS 6 62 #define RTL8723B_TX_COUNT 4 63 #define RTL8723B_MAX_RF_PATHS 4 64 #define RTL8XXXU_MAX_CHANNEL_GROUPS 6 65 #define RF6052_MAX_TX_PWR 0x3f 66 67 #define EFUSE_MAP_LEN 512 68 #define EFUSE_MAX_SECTION_8723A 64 69 #define EFUSE_REAL_CONTENT_LEN_8723A 512 70 #define EFUSE_BT_MAP_LEN_8723A 1024 71 #define EFUSE_MAX_WORD_UNIT 4 72 73 enum rtl8xxxu_rtl_chip { 74 RTL8192S = 0x81920, 75 RTL8191S = 0x81910, 76 RTL8192C = 0x8192c, 77 RTL8191C = 0x8191c, 78 RTL8188C = 0x8188c, 79 RTL8188R = 0x81889, 80 RTL8192D = 0x8192d, 81 RTL8723A = 0x8723a, 82 RTL8188E = 0x8188e, 83 RTL8812 = 0x88120, 84 RTL8821 = 0x88210, 85 RTL8192E = 0x8192e, 86 RTL8191E = 0x8191e, 87 RTL8723B = 0x8723b, 88 RTL8814A = 0x8814a, 89 RTL8881A = 0x8881a, 90 RTL8821B = 0x8821b, 91 RTL8822B = 0x8822b, 92 RTL8703B = 0x8703b, 93 RTL8195A = 0x8195a, 94 RTL8188F = 0x8188f 95 }; 96 97 enum rtl8xxxu_rx_type { 98 RX_TYPE_DATA_PKT = 0, 99 RX_TYPE_C2H = 1, 100 RX_TYPE_ERROR = -1 101 }; 102 103 struct rtl8xxxu_rxdesc16 { 104 #ifdef __LITTLE_ENDIAN 105 u32 pktlen:14; 106 u32 crc32:1; 107 u32 icverr:1; 108 u32 drvinfo_sz:4; 109 u32 security:3; 110 u32 qos:1; 111 u32 shift:2; 112 u32 phy_stats:1; 113 u32 swdec:1; 114 u32 ls:1; 115 u32 fs:1; 116 u32 eor:1; 117 u32 own:1; 118 119 u32 macid:5; 120 u32 tid:4; 121 u32 hwrsvd:4; 122 u32 amsdu:1; 123 u32 paggr:1; 124 u32 faggr:1; 125 u32 a1fit:4; 126 u32 a2fit:4; 127 u32 pam:1; 128 u32 pwr:1; 129 u32 md:1; 130 u32 mf:1; 131 u32 type:2; 132 u32 mc:1; 133 u32 bc:1; 134 135 u32 seq:12; 136 u32 frag:4; 137 u32 pkt_cnt:8; 138 u32 reserved:6; 139 u32 nextind:1; 140 u32 reserved0:1; 141 142 u32 rxmcs:6; 143 u32 rxht:1; 144 u32 gf:1; 145 u32 splcp:1; 146 u32 bw:1; 147 u32 htc:1; 148 u32 eosp:1; 149 u32 bssidfit:2; 150 u32 reserved1:16; 151 u32 unicastwake:1; 152 u32 magicwake:1; 153 154 u32 pattern0match:1; 155 u32 pattern1match:1; 156 u32 pattern2match:1; 157 u32 pattern3match:1; 158 u32 pattern4match:1; 159 u32 pattern5match:1; 160 u32 pattern6match:1; 161 u32 pattern7match:1; 162 u32 pattern8match:1; 163 u32 pattern9match:1; 164 u32 patternamatch:1; 165 u32 patternbmatch:1; 166 u32 patterncmatch:1; 167 u32 reserved2:19; 168 #else 169 u32 own:1; 170 u32 eor:1; 171 u32 fs:1; 172 u32 ls:1; 173 u32 swdec:1; 174 u32 phy_stats:1; 175 u32 shift:2; 176 u32 qos:1; 177 u32 security:3; 178 u32 drvinfo_sz:4; 179 u32 icverr:1; 180 u32 crc32:1; 181 u32 pktlen:14; 182 183 u32 bc:1; 184 u32 mc:1; 185 u32 type:2; 186 u32 mf:1; 187 u32 md:1; 188 u32 pwr:1; 189 u32 pam:1; 190 u32 a2fit:4; 191 u32 a1fit:4; 192 u32 faggr:1; 193 u32 paggr:1; 194 u32 amsdu:1; 195 u32 hwrsvd:4; 196 u32 tid:4; 197 u32 macid:5; 198 199 u32 reserved0:1; 200 u32 nextind:1; 201 u32 reserved:6; 202 u32 pkt_cnt:8; 203 u32 frag:4; 204 u32 seq:12; 205 206 u32 magicwake:1; 207 u32 unicastwake:1; 208 u32 reserved1:16; 209 u32 bssidfit:2; 210 u32 eosp:1; 211 u32 htc:1; 212 u32 bw:1; 213 u32 splcp:1; 214 u32 gf:1; 215 u32 rxht:1; 216 u32 rxmcs:6; 217 218 u32 reserved2:19; 219 u32 patterncmatch:1; 220 u32 patternbmatch:1; 221 u32 patternamatch:1; 222 u32 pattern9match:1; 223 u32 pattern8match:1; 224 u32 pattern7match:1; 225 u32 pattern6match:1; 226 u32 pattern5match:1; 227 u32 pattern4match:1; 228 u32 pattern3match:1; 229 u32 pattern2match:1; 230 u32 pattern1match:1; 231 u32 pattern0match:1; 232 #endif 233 u32 tsfl; 234 #if 0 235 u32 bassn:12; 236 u32 bavld:1; 237 u32 reserved3:19; 238 #endif 239 }; 240 241 struct rtl8xxxu_rxdesc24 { 242 #ifdef __LITTLE_ENDIAN 243 u32 pktlen:14; 244 u32 crc32:1; 245 u32 icverr:1; 246 u32 drvinfo_sz:4; 247 u32 security:3; 248 u32 qos:1; 249 u32 shift:2; 250 u32 phy_stats:1; 251 u32 swdec:1; 252 u32 ls:1; 253 u32 fs:1; 254 u32 eor:1; 255 u32 own:1; 256 257 u32 macid:7; 258 u32 dummy1_0:1; 259 u32 tid:4; 260 u32 dummy1_1:1; 261 u32 amsdu:1; 262 u32 rxid_match:1; 263 u32 paggr:1; 264 u32 a1fit:4; /* 16 */ 265 u32 chkerr:1; 266 u32 ipver:1; 267 u32 tcpudp:1; 268 u32 chkvld:1; 269 u32 pam:1; 270 u32 pwr:1; 271 u32 more_data:1; 272 u32 more_frag:1; 273 u32 type:2; 274 u32 mc:1; 275 u32 bc:1; 276 277 u32 seq:12; 278 u32 frag:4; 279 u32 rx_is_qos:1; /* 16 */ 280 u32 dummy2_0:1; 281 u32 wlanhd_iv_len:6; 282 u32 dummy2_1:4; 283 u32 rpt_sel:1; 284 u32 dummy2_2:3; 285 286 u32 rxmcs:7; 287 u32 dummy3_0:3; 288 u32 htc:1; 289 u32 eosp:1; 290 u32 bssidfit:2; 291 u32 dummy3_1:2; 292 u32 usb_agg_pktnum:8; /* 16 */ 293 u32 dummy3_2:5; 294 u32 pattern_match:1; 295 u32 unicast_match:1; 296 u32 magic_match:1; 297 298 u32 splcp:1; 299 u32 ldcp:1; 300 u32 stbc:1; 301 u32 dummy4_0:1; 302 u32 bw:2; 303 u32 dummy4_1:26; 304 #else 305 u32 own:1; 306 u32 eor:1; 307 u32 fs:1; 308 u32 ls:1; 309 u32 swdec:1; 310 u32 phy_stats:1; 311 u32 shift:2; 312 u32 qos:1; 313 u32 security:3; 314 u32 drvinfo_sz:4; 315 u32 icverr:1; 316 u32 crc32:1; 317 u32 pktlen:14; 318 319 u32 bc:1; 320 u32 mc:1; 321 u32 type:2; 322 u32 mf:1; 323 u32 md:1; 324 u32 pwr:1; 325 u32 pam:1; 326 u32 a2fit:4; 327 u32 a1fit:4; 328 u32 faggr:1; 329 u32 paggr:1; 330 u32 amsdu:1; 331 u32 hwrsvd:4; 332 u32 tid:4; 333 u32 macid:5; 334 335 u32 dummy2_2:3; 336 u32 rpt_sel:1; 337 u32 dummy2_1:4; 338 u32 wlanhd_iv_len:6; 339 u32 dummy2_0:1; 340 u32 rx_is_qos:1; 341 u32 frag:4; /* 16 */ 342 u32 seq:12; 343 344 u32 magic_match:1; 345 u32 unicast_match:1; 346 u32 pattern_match:1; 347 u32 dummy3_2:5; 348 u32 usb_agg_pktnum:8; 349 u32 dummy3_1:2; /* 16 */ 350 u32 bssidfit:2; 351 u32 eosp:1; 352 u32 htc:1; 353 u32 dummy3_0:3; 354 u32 rxmcs:7; 355 356 u32 dumm4_1:26; 357 u32 bw:2; 358 u32 dummy4_0:1; 359 u32 stbc:1; 360 u32 ldcp:1; 361 u32 splcp:1; 362 #endif 363 u32 tsfl; 364 }; 365 366 struct rtl8xxxu_txdesc32 { 367 __le16 pkt_size; 368 u8 pkt_offset; 369 u8 txdw0; 370 __le32 txdw1; 371 __le32 txdw2; 372 __le32 txdw3; 373 __le32 txdw4; 374 __le32 txdw5; 375 __le32 txdw6; 376 __le16 csum; 377 __le16 txdw7; 378 }; 379 380 struct rtl8xxxu_txdesc40 { 381 __le16 pkt_size; 382 u8 pkt_offset; 383 u8 txdw0; 384 __le32 txdw1; 385 __le32 txdw2; 386 __le32 txdw3; 387 __le32 txdw4; 388 __le32 txdw5; 389 __le32 txdw6; 390 __le16 csum; 391 __le16 txdw7; 392 __le32 txdw8; 393 __le32 txdw9; 394 }; 395 396 /* CCK Rates, TxHT = 0 */ 397 #define DESC_RATE_1M 0x00 398 #define DESC_RATE_2M 0x01 399 #define DESC_RATE_5_5M 0x02 400 #define DESC_RATE_11M 0x03 401 402 /* OFDM Rates, TxHT = 0 */ 403 #define DESC_RATE_6M 0x04 404 #define DESC_RATE_9M 0x05 405 #define DESC_RATE_12M 0x06 406 #define DESC_RATE_18M 0x07 407 #define DESC_RATE_24M 0x08 408 #define DESC_RATE_36M 0x09 409 #define DESC_RATE_48M 0x0a 410 #define DESC_RATE_54M 0x0b 411 412 /* MCS Rates, TxHT = 1 */ 413 #define DESC_RATE_MCS0 0x0c 414 #define DESC_RATE_MCS1 0x0d 415 #define DESC_RATE_MCS2 0x0e 416 #define DESC_RATE_MCS3 0x0f 417 #define DESC_RATE_MCS4 0x10 418 #define DESC_RATE_MCS5 0x11 419 #define DESC_RATE_MCS6 0x12 420 #define DESC_RATE_MCS7 0x13 421 #define DESC_RATE_MCS8 0x14 422 #define DESC_RATE_MCS9 0x15 423 #define DESC_RATE_MCS10 0x16 424 #define DESC_RATE_MCS11 0x17 425 #define DESC_RATE_MCS12 0x18 426 #define DESC_RATE_MCS13 0x19 427 #define DESC_RATE_MCS14 0x1a 428 #define DESC_RATE_MCS15 0x1b 429 #define DESC_RATE_MCS15_SG 0x1c 430 #define DESC_RATE_MCS32 0x20 431 432 #define TXDESC_OFFSET_SZ 0 433 #define TXDESC_OFFSET_SHT 16 434 #if 0 435 #define TXDESC_BMC BIT(24) 436 #define TXDESC_LSG BIT(26) 437 #define TXDESC_FSG BIT(27) 438 #define TXDESC_OWN BIT(31) 439 #else 440 #define TXDESC_BROADMULTICAST BIT(0) 441 #define TXDESC_HTC BIT(1) 442 #define TXDESC_LAST_SEGMENT BIT(2) 443 #define TXDESC_FIRST_SEGMENT BIT(3) 444 #define TXDESC_LINIP BIT(4) 445 #define TXDESC_NO_ACM BIT(5) 446 #define TXDESC_GF BIT(6) 447 #define TXDESC_OWN BIT(7) 448 #endif 449 450 /* Word 1 */ 451 /* 452 * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are 453 * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid. 454 */ 455 #define TXDESC_PKT_OFFSET_SZ 0 456 #define TXDESC32_AGG_ENABLE BIT(5) 457 #define TXDESC32_AGG_BREAK BIT(6) 458 #define TXDESC40_MACID_SHIFT 0 459 #define TXDESC40_MACID_MASK 0x00f0 460 #define TXDESC_QUEUE_SHIFT 8 461 #define TXDESC_QUEUE_MASK 0x1f00 462 #define TXDESC_QUEUE_BK 0x2 463 #define TXDESC_QUEUE_BE 0x0 464 #define TXDESC_QUEUE_VI 0x5 465 #define TXDESC_QUEUE_VO 0x7 466 #define TXDESC_QUEUE_BEACON 0x10 467 #define TXDESC_QUEUE_HIGH 0x11 468 #define TXDESC_QUEUE_MGNT 0x12 469 #define TXDESC_QUEUE_CMD 0x13 470 #define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1) 471 #define TXDESC40_RDG_NAV_EXT BIT(13) 472 #define TXDESC40_LSIG_TXOP_ENABLE BIT(14) 473 #define TXDESC40_PIFS BIT(15) 474 475 #define DESC_RATE_ID_SHIFT 16 476 #define DESC_RATE_ID_MASK 0xf 477 #define TXDESC_NAVUSEHDR BIT(20) 478 #define TXDESC_SEC_RC4 0x00400000 479 #define TXDESC_SEC_AES 0x00c00000 480 #define TXDESC_PKT_OFFSET_SHIFT 26 481 #define TXDESC_AGG_EN BIT(29) 482 #define TXDESC_HWPC BIT(31) 483 484 /* Word 2 */ 485 #define TXDESC40_PAID_SHIFT 0 486 #define TXDESC40_PAID_MASK 0x1ff 487 #define TXDESC40_CCA_RTS_SHIFT 10 488 #define TXDESC40_CCA_RTS_MASK 0xc00 489 #define TXDESC40_AGG_ENABLE BIT(12) 490 #define TXDESC40_RDG_ENABLE BIT(13) 491 #define TXDESC40_AGG_BREAK BIT(16) 492 #define TXDESC40_MORE_FRAG BIT(17) 493 #define TXDESC40_RAW BIT(18) 494 #define TXDESC32_ACK_REPORT BIT(19) 495 #define TXDESC40_SPE_RPT BIT(19) 496 #define TXDESC_AMPDU_DENSITY_SHIFT 20 497 #define TXDESC40_BT_INT BIT(23) 498 #define TXDESC40_GID_SHIFT 24 499 500 /* Word 3 */ 501 #define TXDESC40_USE_DRIVER_RATE BIT(8) 502 #define TXDESC40_CTS_SELF_ENABLE BIT(11) 503 #define TXDESC40_RTS_CTS_ENABLE BIT(12) 504 #define TXDESC40_HW_RTS_ENABLE BIT(13) 505 #define TXDESC32_SEQ_SHIFT 16 506 #define TXDESC32_SEQ_MASK 0x0fff0000 507 508 /* Word 4 */ 509 #define TXDESC32_RTS_RATE_SHIFT 0 510 #define TXDESC32_RTS_RATE_MASK 0x3f 511 #define TXDESC32_QOS BIT(6) 512 #define TXDESC32_HW_SEQ_ENABLE BIT(7) 513 #define TXDESC32_USE_DRIVER_RATE BIT(8) 514 #define TXDESC_DISABLE_DATA_FB BIT(10) 515 #define TXDESC32_CTS_SELF_ENABLE BIT(11) 516 #define TXDESC32_RTS_CTS_ENABLE BIT(12) 517 #define TXDESC32_HW_RTS_ENABLE BIT(13) 518 #define TXDESC_PRIME_CH_OFF_LOWER BIT(20) 519 #define TXDESC_PRIME_CH_OFF_UPPER BIT(21) 520 #define TXDESC32_SHORT_PREAMBLE BIT(24) 521 #define TXDESC_DATA_BW BIT(25) 522 #define TXDESC_RTS_DATA_BW BIT(27) 523 #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28) 524 #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29) 525 #define TXDESC40_DATA_RATE_FB_SHIFT 8 526 #define TXDESC40_DATA_RATE_FB_MASK 0x00001f00 527 #define TXDESC40_RETRY_LIMIT_ENABLE BIT(17) 528 #define TXDESC40_RETRY_LIMIT_SHIFT 18 529 #define TXDESC40_RETRY_LIMIT_MASK 0x00fc0000 530 #define TXDESC40_RTS_RATE_SHIFT 24 531 #define TXDESC40_RTS_RATE_MASK 0x3f000000 532 533 /* Word 5 */ 534 #define TXDESC40_SHORT_PREAMBLE BIT(4) 535 #define TXDESC32_SHORT_GI BIT(6) 536 #define TXDESC_CCX_TAG BIT(7) 537 #define TXDESC32_RETRY_LIMIT_ENABLE BIT(17) 538 #define TXDESC32_RETRY_LIMIT_SHIFT 18 539 #define TXDESC32_RETRY_LIMIT_MASK 0x00fc0000 540 541 /* Word 6 */ 542 #define TXDESC_MAX_AGG_SHIFT 11 543 544 /* Word 8 */ 545 #define TXDESC40_HW_SEQ_ENABLE BIT(15) 546 547 /* Word 9 */ 548 #define TXDESC40_SEQ_SHIFT 12 549 #define TXDESC40_SEQ_MASK 0x00fff000 550 551 struct phy_rx_agc_info { 552 #ifdef __LITTLE_ENDIAN 553 u8 gain:7, trsw:1; 554 #else 555 u8 trsw:1, gain:7; 556 #endif 557 }; 558 559 struct rtl8723au_phy_stats { 560 struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS]; 561 u8 ch_corr[RTL8723A_MAX_RF_PATHS]; 562 u8 cck_sig_qual_ofdm_pwdb_all; 563 u8 cck_agc_rpt_ofdm_cfosho_a; 564 u8 cck_rpt_b_ofdm_cfosho_b; 565 u8 reserved_1; 566 u8 noise_power_db_msb; 567 u8 path_cfotail[RTL8723A_MAX_RF_PATHS]; 568 u8 pcts_mask[RTL8723A_MAX_RF_PATHS]; 569 s8 stream_rxevm[RTL8723A_MAX_RF_PATHS]; 570 u8 path_rxsnr[RTL8723A_MAX_RF_PATHS]; 571 u8 noise_power_db_lsb; 572 u8 reserved_2[3]; 573 u8 stream_csi[RTL8723A_MAX_RF_PATHS]; 574 u8 stream_target_csi[RTL8723A_MAX_RF_PATHS]; 575 s8 sig_evm; 576 u8 reserved_3; 577 578 #ifdef __LITTLE_ENDIAN 579 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 580 u8 sgi_en:1; 581 u8 rxsc:2; 582 u8 idle_long:1; 583 u8 r_ant_train_en:1; 584 u8 antenna_select_b:1; 585 u8 antenna_select:1; 586 #else /* _BIG_ENDIAN_ */ 587 u8 antenna_select:1; 588 u8 antenna_select_b:1; 589 u8 r_ant_train_en:1; 590 u8 idle_long:1; 591 u8 rxsc:2; 592 u8 sgi_en:1; 593 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 594 #endif 595 }; 596 597 /* 598 * Regs to backup 599 */ 600 #define RTL8XXXU_ADDA_REGS 16 601 #define RTL8XXXU_MAC_REGS 4 602 #define RTL8XXXU_BB_REGS 9 603 604 struct rtl8xxxu_firmware_header { 605 __le16 signature; /* 92C0: test chip; 92C, 606 88C0: test chip; 607 88C1: MP A-cut; 608 92C1: MP A-cut */ 609 u8 category; /* AP/NIC and USB/PCI */ 610 u8 function; 611 612 __le16 major_version; /* FW Version */ 613 u8 minor_version; /* FW Subversion, default 0x00 */ 614 u8 reserved1; 615 616 u8 month; /* Release time Month field */ 617 u8 date; /* Release time Date field */ 618 u8 hour; /* Release time Hour field */ 619 u8 minute; /* Release time Minute field */ 620 621 __le16 ramcodesize; /* Size of RAM code */ 622 u16 reserved2; 623 624 __le32 svn_idx; /* SVN entry index */ 625 u32 reserved3; 626 627 u32 reserved4; 628 u32 reserved5; 629 630 u8 data[]; 631 }; 632 633 /* 634 * 8723au/8192cu/8188ru required base power index offset tables. 635 */ 636 struct rtl8xxxu_power_base { 637 u32 reg_0e00; 638 u32 reg_0e04; 639 u32 reg_0e08; 640 u32 reg_086c; 641 642 u32 reg_0e10; 643 u32 reg_0e14; 644 u32 reg_0e18; 645 u32 reg_0e1c; 646 647 u32 reg_0830; 648 u32 reg_0834; 649 u32 reg_0838; 650 u32 reg_086c_2; 651 652 u32 reg_083c; 653 u32 reg_0848; 654 u32 reg_084c; 655 u32 reg_0868; 656 }; 657 658 /* 659 * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14 660 */ 661 struct rtl8723au_idx { 662 #ifdef __LITTLE_ENDIAN 663 int a:4; 664 int b:4; 665 #else 666 int b:4; 667 int a:4; 668 #endif 669 } __attribute__((packed)); 670 671 struct rtl8723au_efuse { 672 __le16 rtl_id; 673 u8 res0[0xe]; 674 u8 cck_tx_power_index_A[3]; /* 0x10 */ 675 u8 cck_tx_power_index_B[3]; 676 u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */ 677 u8 ht40_1s_tx_power_index_B[3]; 678 /* 679 * The following entries are half-bytes split as: 680 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 681 */ 682 struct rtl8723au_idx ht20_tx_power_index_diff[3]; 683 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 684 struct rtl8723au_idx ht40_max_power_offset[3]; 685 struct rtl8723au_idx ht20_max_power_offset[3]; 686 u8 channel_plan; /* 0x28 */ 687 u8 tssi_a; 688 u8 thermal_meter; 689 u8 rf_regulatory; 690 u8 rf_option_2; 691 u8 rf_option_3; 692 u8 rf_option_4; 693 u8 res7; 694 u8 version /* 0x30 */; 695 u8 customer_id_major; 696 u8 customer_id_minor; 697 u8 xtal_k; 698 u8 chipset; /* 0x34 */ 699 u8 res8[0x82]; 700 u8 vid; /* 0xb7 */ 701 u8 res9; 702 u8 pid; /* 0xb9 */ 703 u8 res10[0x0c]; 704 u8 mac_addr[ETH_ALEN]; /* 0xc6 */ 705 u8 res11[2]; 706 u8 vendor_name[7]; 707 u8 res12[2]; 708 u8 device_name[0x29]; /* 0xd7 */ 709 }; 710 711 struct rtl8192cu_efuse { 712 __le16 rtl_id; 713 __le16 hpon; 714 u8 res0[2]; 715 __le16 clk; 716 __le16 testr; 717 __le16 vid; 718 __le16 did; 719 __le16 svid; 720 __le16 smid; /* 0x10 */ 721 u8 res1[4]; 722 u8 mac_addr[ETH_ALEN]; /* 0x16 */ 723 u8 res2[2]; 724 u8 vendor_name[7]; 725 u8 res3[3]; 726 u8 device_name[0x14]; /* 0x28 */ 727 u8 res4[0x1e]; /* 0x3c */ 728 u8 cck_tx_power_index_A[3]; /* 0x5a */ 729 u8 cck_tx_power_index_B[3]; 730 u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */ 731 u8 ht40_1s_tx_power_index_B[3]; 732 /* 733 * The following entries are half-bytes split as: 734 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 735 */ 736 struct rtl8723au_idx ht40_2s_tx_power_index_diff[3]; 737 struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */ 738 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 739 struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */ 740 struct rtl8723au_idx ht20_max_power_offset[3]; 741 u8 channel_plan; /* 0x75 */ 742 u8 tssi_a; 743 u8 tssi_b; 744 u8 thermal_meter; /* xtal_k */ /* 0x78 */ 745 u8 rf_regulatory; 746 u8 rf_option_2; 747 u8 rf_option_3; 748 u8 rf_option_4; 749 u8 res5[1]; /* 0x7d */ 750 u8 version; 751 u8 customer_id; 752 }; 753 754 struct rtl8723bu_pwr_idx { 755 #ifdef __LITTLE_ENDIAN 756 int ht20:4; 757 int ht40:4; 758 int ofdm:4; 759 int cck:4; 760 #else 761 int cck:4; 762 int ofdm:4; 763 int ht40:4; 764 int ht20:4; 765 #endif 766 } __attribute__((packed)); 767 768 struct rtl8723bu_efuse_tx_power { 769 u8 cck_base[6]; 770 u8 ht40_base[5]; 771 struct rtl8723au_idx ht20_ofdm_1s_diff; 772 struct rtl8723bu_pwr_idx pwr_diff[3]; 773 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 774 }; 775 776 struct rtl8723bu_efuse { 777 __le16 rtl_id; 778 u8 res0[0x0e]; 779 struct rtl8723bu_efuse_tx_power tx_power_index_A; /* 0x10 */ 780 struct rtl8723bu_efuse_tx_power tx_power_index_B; /* 0x3a */ 781 struct rtl8723bu_efuse_tx_power tx_power_index_C; /* 0x64 */ 782 struct rtl8723bu_efuse_tx_power tx_power_index_D; /* 0x8e */ 783 u8 channel_plan; /* 0xb8 */ 784 u8 xtal_k; 785 u8 thermal_meter; 786 u8 iqk_lck; 787 u8 pa_type; /* 0xbc */ 788 u8 lna_type_2g; /* 0xbd */ 789 u8 res2[3]; 790 u8 rf_board_option; 791 u8 rf_feature_option; 792 u8 rf_bt_setting; 793 u8 eeprom_version; 794 u8 eeprom_customer_id; 795 u8 res3[2]; 796 u8 tx_pwr_calibrate_rate; 797 u8 rf_antenna_option; /* 0xc9 */ 798 u8 rfe_option; 799 u8 res4[9]; 800 u8 usb_optional_function; 801 u8 res5[0x1e]; 802 u8 res6[2]; 803 u8 serial[0x0b]; /* 0xf5 */ 804 u8 vid; /* 0x100 */ 805 u8 res7; 806 u8 pid; 807 u8 res8[4]; 808 u8 mac_addr[ETH_ALEN]; /* 0x107 */ 809 u8 res9[2]; 810 u8 vendor_name[0x07]; 811 u8 res10[2]; 812 u8 device_name[0x14]; 813 u8 res11[0xcf]; 814 u8 package_type; /* 0x1fb */ 815 u8 res12[0x4]; 816 }; 817 818 struct rtl8192eu_efuse_tx_power { 819 u8 cck_base[6]; 820 u8 ht40_base[5]; 821 struct rtl8723au_idx ht20_ofdm_1s_diff; 822 struct rtl8723bu_pwr_idx pwr_diff[3]; 823 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 824 }; 825 826 struct rtl8192eu_efuse { 827 __le16 rtl_id; 828 u8 res0[0x0e]; 829 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 830 struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x3a */ 831 u8 res2[0x54]; 832 u8 channel_plan; /* 0xb8 */ 833 u8 xtal_k; 834 u8 thermal_meter; 835 u8 iqk_lck; 836 u8 pa_type; /* 0xbc */ 837 u8 lna_type_2g; /* 0xbd */ 838 u8 res3[1]; 839 u8 lna_type_5g; /* 0xbf */ 840 u8 res4[1]; 841 u8 rf_board_option; 842 u8 rf_feature_option; 843 u8 rf_bt_setting; 844 u8 eeprom_version; 845 u8 eeprom_customer_id; 846 u8 res5[3]; 847 u8 rf_antenna_option; /* 0xc9 */ 848 u8 res6[6]; 849 u8 vid; /* 0xd0 */ 850 u8 res7[1]; 851 u8 pid; /* 0xd2 */ 852 u8 res8[1]; 853 u8 usb_optional_function; 854 u8 res9[2]; 855 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 856 u8 res10[2]; 857 u8 vendor_name[7]; 858 u8 res11[2]; 859 u8 device_name[0x0b]; /* 0xe8 */ 860 u8 res12[2]; 861 u8 serial[0x0b]; /* 0xf5 */ 862 u8 res13[0x30]; 863 u8 unknown[0x0d]; /* 0x130 */ 864 u8 res14[0xc3]; 865 }; 866 867 struct rtl8xxxu_reg8val { 868 u16 reg; 869 u8 val; 870 }; 871 872 struct rtl8xxxu_reg32val { 873 u16 reg; 874 u32 val; 875 }; 876 877 struct rtl8xxxu_rfregval { 878 u8 reg; 879 u32 val; 880 }; 881 882 enum rtl8xxxu_rfpath { 883 RF_A = 0, 884 RF_B = 1, 885 }; 886 887 struct rtl8xxxu_rfregs { 888 u16 hssiparm1; 889 u16 hssiparm2; 890 u16 lssiparm; 891 u16 hspiread; 892 u16 lssiread; 893 u16 rf_sw_ctrl; 894 }; 895 896 #define H2C_MAX_MBOX 4 897 #define H2C_EXT BIT(7) 898 #define H2C_JOIN_BSS_DISCONNECT 0 899 #define H2C_JOIN_BSS_CONNECT 1 900 901 /* 902 * H2C (firmware) commands differ between the older generation chips 903 * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu, 904 * 8192[de]u, 8192eu, and 8812. 905 */ 906 enum h2c_cmd_8723a { 907 H2C_SET_POWER_MODE = 1, 908 H2C_JOIN_BSS_REPORT = 2, 909 H2C_SET_RSSI = 5, 910 H2C_SET_RATE_MASK = (6 | H2C_EXT), 911 }; 912 913 enum h2c_cmd_8723b { 914 /* 915 * Common Class: 000 916 */ 917 H2C_8723B_RSVD_PAGE = 0x00, 918 H2C_8723B_MEDIA_STATUS_RPT = 0x01, 919 H2C_8723B_SCAN_ENABLE = 0x02, 920 H2C_8723B_KEEP_ALIVE = 0x03, 921 H2C_8723B_DISCON_DECISION = 0x04, 922 H2C_8723B_PSD_OFFLOAD = 0x05, 923 H2C_8723B_AP_OFFLOAD = 0x08, 924 H2C_8723B_BCN_RSVDPAGE = 0x09, 925 H2C_8723B_PROBERSP_RSVDPAGE = 0x0A, 926 H2C_8723B_FCS_RSVDPAGE = 0x10, 927 H2C_8723B_FCS_INFO = 0x11, 928 H2C_8723B_AP_WOW_GPIO_CTRL = 0x13, 929 930 /* 931 * PoweSave Class: 001 932 */ 933 H2C_8723B_SET_PWR_MODE = 0x20, 934 H2C_8723B_PS_TUNING_PARA = 0x21, 935 H2C_8723B_PS_TUNING_PARA2 = 0x22, 936 H2C_8723B_P2P_LPS_PARAM = 0x23, 937 H2C_8723B_P2P_PS_OFFLOAD = 0x24, 938 H2C_8723B_PS_SCAN_ENABLE = 0x25, 939 H2C_8723B_SAP_PS_ = 0x26, 940 H2C_8723B_INACTIVE_PS_ = 0x27, 941 H2C_8723B_FWLPS_IN_IPS_ = 0x28, 942 943 /* 944 * Dynamic Mechanism Class: 010 945 */ 946 H2C_8723B_MACID_CFG_RAID = 0x40, 947 H2C_8723B_TXBF = 0x41, 948 H2C_8723B_RSSI_SETTING = 0x42, 949 H2C_8723B_AP_REQ_TXRPT = 0x43, 950 H2C_8723B_INIT_RATE_COLLECT = 0x44, 951 952 /* 953 * BT Class: 011 954 */ 955 H2C_8723B_B_TYPE_TDMA = 0x60, 956 H2C_8723B_BT_INFO = 0x61, 957 H2C_8723B_FORCE_BT_TXPWR = 0x62, 958 H2C_8723B_BT_IGNORE_WLANACT = 0x63, 959 H2C_8723B_DAC_SWING_VALUE = 0x64, 960 H2C_8723B_ANT_SEL_RSV = 0x65, 961 H2C_8723B_WL_OPMODE = 0x66, 962 H2C_8723B_BT_MP_OPER = 0x67, 963 H2C_8723B_BT_CONTROL = 0x68, 964 H2C_8723B_BT_WIFI_CTRL = 0x69, 965 H2C_8723B_BT_FW_PATCH = 0x6a, 966 H2C_8723B_BT_WLAN_CALIBRATION = 0x6d, 967 H2C_8723B_BT_GRANT = 0x6e, 968 969 /* 970 * WOWLAN Class: 100 971 */ 972 H2C_8723B_WOWLAN = 0x80, 973 H2C_8723B_REMOTE_WAKE_CTRL = 0x81, 974 H2C_8723B_AOAC_GLOBAL_INFO = 0x82, 975 H2C_8723B_AOAC_RSVD_PAGE = 0x83, 976 H2C_8723B_AOAC_RSVD_PAGE2 = 0x84, 977 H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85, 978 H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86, 979 H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87, 980 981 H2C_8723B_RESET_TSF = 0xC0, 982 }; 983 984 985 struct h2c_cmd { 986 union { 987 struct { 988 u8 cmd; 989 u8 data[7]; 990 } __packed cmd; 991 struct { 992 __le32 data; 993 __le16 ext; 994 } __packed raw; 995 struct { 996 __le32 data; 997 __le32 ext; 998 } __packed raw_wide; 999 struct { 1000 u8 cmd; 1001 u8 data; 1002 } __packed joinbss; 1003 struct { 1004 u8 cmd; 1005 __le16 mask_hi; 1006 u8 arg; 1007 __le16 mask_lo; 1008 } __packed ramask; 1009 struct { 1010 u8 cmd; 1011 u8 parm; 1012 u8 macid; 1013 u8 macid_end; 1014 } __packed media_status_rpt; 1015 struct { 1016 u8 cmd; 1017 u8 macid; 1018 /* 1019 * [0:4] - RAID 1020 * [7] - SGI 1021 */ 1022 u8 data1; 1023 /* 1024 * [0:1] - Bandwidth 1025 * [3] - No Update 1026 * [4:5] - VHT enable 1027 * [6] - DISPT 1028 * [7] - DISRA 1029 */ 1030 u8 data2; 1031 u8 ramask0; 1032 u8 ramask1; 1033 u8 ramask2; 1034 u8 ramask3; 1035 } __packed b_macid_cfg; 1036 struct { 1037 u8 cmd; 1038 u8 data1; 1039 u8 data2; 1040 u8 data3; 1041 u8 data4; 1042 u8 data5; 1043 } __packed b_type_dma; 1044 struct { 1045 u8 cmd; 1046 u8 data; 1047 } __packed bt_info; 1048 struct { 1049 u8 cmd; 1050 u8 operreq; 1051 u8 opcode; 1052 u8 data; 1053 u8 addr; 1054 } __packed bt_mp_oper; 1055 struct { 1056 u8 cmd; 1057 u8 data; 1058 } __packed bt_wlan_calibration; 1059 struct { 1060 u8 cmd; 1061 u8 data; 1062 } __packed ignore_wlan; 1063 struct { 1064 u8 cmd; 1065 u8 ant_inverse; 1066 u8 int_switch_type; 1067 } __packed ant_sel_rsv; 1068 struct { 1069 u8 cmd; 1070 u8 data; 1071 } __packed bt_grant; 1072 }; 1073 }; 1074 1075 enum c2h_evt_8723b { 1076 C2H_8723B_DEBUG = 0, 1077 C2H_8723B_TSF = 1, 1078 C2H_8723B_AP_RPT_RSP = 2, 1079 C2H_8723B_CCX_TX_RPT = 3, 1080 C2H_8723B_BT_RSSI = 4, 1081 C2H_8723B_BT_OP_MODE = 5, 1082 C2H_8723B_EXT_RA_RPT = 6, 1083 C2H_8723B_BT_INFO = 9, 1084 C2H_8723B_HW_INFO_EXCH = 0x0a, 1085 C2H_8723B_BT_MP_INFO = 0x0b, 1086 C2H_8723B_RA_REPORT = 0x0c, 1087 C2H_8723B_FW_DEBUG = 0xff, 1088 }; 1089 1090 enum bt_info_src_8723b { 1091 BT_INFO_SRC_8723B_WIFI_FW = 0x0, 1092 BT_INFO_SRC_8723B_BT_RSP = 0x1, 1093 BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2, 1094 }; 1095 1096 enum bt_mp_oper_opcode_8723b { 1097 BT_MP_OP_GET_BT_VERSION = 0x00, 1098 BT_MP_OP_RESET = 0x01, 1099 BT_MP_OP_TEST_CTRL = 0x02, 1100 BT_MP_OP_SET_BT_MODE = 0x03, 1101 BT_MP_OP_SET_CHNL_TX_GAIN = 0x04, 1102 BT_MP_OP_SET_PKT_TYPE_LEN = 0x05, 1103 BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06, 1104 BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07, 1105 BT_MP_OP_SET_PKT_HEADER = 0x08, 1106 BT_MP_OP_SET_WHITENCOEFF = 0x09, 1107 BT_MP_OP_SET_BD_ADDR_L = 0x0a, 1108 BT_MP_OP_SET_BD_ADDR_H = 0x0b, 1109 BT_MP_OP_WRITE_REG_ADDR = 0x0c, 1110 BT_MP_OP_WRITE_REG_VALUE = 0x0d, 1111 BT_MP_OP_GET_BT_STATUS = 0x0e, 1112 BT_MP_OP_GET_BD_ADDR_L = 0x0f, 1113 BT_MP_OP_GET_BD_ADDR_H = 0x10, 1114 BT_MP_OP_READ_REG = 0x11, 1115 BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12, 1116 BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13, 1117 BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14, 1118 BT_MP_OP_GET_RX_PKT_CNT_L = 0x15, 1119 BT_MP_OP_GET_RX_PKT_CNT_H = 0x16, 1120 BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17, 1121 BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18, 1122 BT_MP_OP_GET_RSSI = 0x19, 1123 BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a, 1124 BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b, 1125 BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c, 1126 BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d, 1127 BT_MP_OP_GET_AFH_MAP_L = 0x1e, 1128 BT_MP_OP_GET_AFH_MAP_M = 0x1f, 1129 BT_MP_OP_GET_AFH_MAP_H = 0x20, 1130 BT_MP_OP_GET_AFH_STATUS = 0x21, 1131 BT_MP_OP_SET_TRACKING_INTERVAL = 0x22, 1132 BT_MP_OP_SET_THERMAL_METER = 0x23, 1133 BT_MP_OP_ENABLE_CFO_TRACKING = 0x24, 1134 }; 1135 1136 enum rtl8xxxu_bw_mode { 1137 RTL8XXXU_CHANNEL_WIDTH_20 = 0, 1138 RTL8XXXU_CHANNEL_WIDTH_40 = 1, 1139 RTL8XXXU_CHANNEL_WIDTH_80 = 2, 1140 RTL8XXXU_CHANNEL_WIDTH_160 = 3, 1141 RTL8XXXU_CHANNEL_WIDTH_80_80 = 4, 1142 RTL8XXXU_CHANNEL_WIDTH_MAX = 5, 1143 }; 1144 1145 struct rtl8723bu_c2h { 1146 u8 id; 1147 u8 seq; 1148 union { 1149 struct { 1150 u8 payload[0]; 1151 } __packed raw; 1152 struct { 1153 u8 ext_id; 1154 u8 status:4; 1155 u8 retlen:4; 1156 u8 opcode_ver:4; 1157 u8 req_num:4; 1158 u8 payload[2]; 1159 } __packed bt_mp_info; 1160 struct { 1161 u8 response_source:4; 1162 u8 dummy0_0:4; 1163 1164 u8 bt_info; 1165 1166 u8 retry_count:4; 1167 u8 dummy2_0:1; 1168 u8 bt_page:1; 1169 u8 tx_rx_mask:1; 1170 u8 dummy2_2:1; 1171 1172 u8 rssi; 1173 1174 u8 basic_rate:1; 1175 u8 bt_has_reset:1; 1176 u8 dummy4_1:1; 1177 u8 ignore_wlan:1; 1178 u8 auto_report:1; 1179 u8 dummy4_2:3; 1180 1181 u8 a4; 1182 u8 a5; 1183 } __packed bt_info; 1184 struct { 1185 u8 rate:7; 1186 u8 sgi:1; 1187 u8 macid; 1188 u8 ldpc:1; 1189 u8 txbf:1; 1190 u8 noisy_state:1; 1191 u8 dummy2_0:5; 1192 u8 dummy3_0; 1193 u8 dummy4_0; 1194 u8 dummy5_0; 1195 u8 bw; 1196 } __packed ra_report; 1197 }; 1198 }; 1199 1200 struct rtl8xxxu_fileops; 1201 1202 /*mlme related.*/ 1203 enum wireless_mode { 1204 WIRELESS_MODE_UNKNOWN = 0, 1205 /* Sub-Element */ 1206 WIRELESS_MODE_B = BIT(0), 1207 WIRELESS_MODE_G = BIT(1), 1208 WIRELESS_MODE_A = BIT(2), 1209 WIRELESS_MODE_N_24G = BIT(3), 1210 WIRELESS_MODE_N_5G = BIT(4), 1211 WIRELESS_AUTO = BIT(5), 1212 WIRELESS_MODE_AC = BIT(6), 1213 WIRELESS_MODE_MAX = 0x7F, 1214 }; 1215 1216 /* from rtlwifi/wifi.h */ 1217 enum ratr_table_mode_new { 1218 RATEID_IDX_BGN_40M_2SS = 0, 1219 RATEID_IDX_BGN_40M_1SS = 1, 1220 RATEID_IDX_BGN_20M_2SS_BN = 2, 1221 RATEID_IDX_BGN_20M_1SS_BN = 3, 1222 RATEID_IDX_GN_N2SS = 4, 1223 RATEID_IDX_GN_N1SS = 5, 1224 RATEID_IDX_BG = 6, 1225 RATEID_IDX_G = 7, 1226 RATEID_IDX_B = 8, 1227 RATEID_IDX_VHT_2SS = 9, 1228 RATEID_IDX_VHT_1SS = 10, 1229 RATEID_IDX_MIX1 = 11, 1230 RATEID_IDX_MIX2 = 12, 1231 RATEID_IDX_VHT_3SS = 13, 1232 RATEID_IDX_BGN_3SS = 14, 1233 }; 1234 1235 #define BT_INFO_8723B_1ANT_B_FTP BIT(7) 1236 #define BT_INFO_8723B_1ANT_B_A2DP BIT(6) 1237 #define BT_INFO_8723B_1ANT_B_HID BIT(5) 1238 #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT(4) 1239 #define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT(3) 1240 #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT(2) 1241 #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT(1) 1242 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT(0) 1243 1244 enum _BT_8723B_1ANT_STATUS { 1245 BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE = 0x0, 1246 BT_8723B_1ANT_STATUS_CONNECTED_IDLE = 0x1, 1247 BT_8723B_1ANT_STATUS_INQ_PAGE = 0x2, 1248 BT_8723B_1ANT_STATUS_ACL_BUSY = 0x3, 1249 BT_8723B_1ANT_STATUS_SCO_BUSY = 0x4, 1250 BT_8723B_1ANT_STATUS_ACL_SCO_BUSY = 0x5, 1251 BT_8723B_1ANT_STATUS_MAX 1252 }; 1253 1254 struct rtl8xxxu_btcoex { 1255 u8 bt_status; 1256 bool bt_busy; 1257 bool has_sco; 1258 bool has_a2dp; 1259 bool has_hid; 1260 bool has_pan; 1261 bool hid_only; 1262 bool a2dp_only; 1263 bool c2h_bt_inquiry; 1264 }; 1265 1266 #define RTL8XXXU_RATR_STA_INIT 0 1267 #define RTL8XXXU_RATR_STA_HIGH 1 1268 #define RTL8XXXU_RATR_STA_MID 2 1269 #define RTL8XXXU_RATR_STA_LOW 3 1270 1271 #define RTL8XXXU_NOISE_FLOOR_MIN -100 1272 #define RTL8XXXU_SNR_THRESH_HIGH 50 1273 #define RTL8XXXU_SNR_THRESH_LOW 20 1274 1275 struct rtl8xxxu_ra_report { 1276 struct rate_info txrate; 1277 u32 bit_rate; 1278 u8 desc_rate; 1279 }; 1280 1281 struct rtl8xxxu_priv { 1282 struct ieee80211_hw *hw; 1283 struct usb_device *udev; 1284 struct rtl8xxxu_fileops *fops; 1285 1286 spinlock_t tx_urb_lock; 1287 struct list_head tx_urb_free_list; 1288 int tx_urb_free_count; 1289 bool tx_stopped; 1290 1291 spinlock_t rx_urb_lock; 1292 struct list_head rx_urb_pending_list; 1293 int rx_urb_pending_count; 1294 bool shutdown; 1295 struct work_struct rx_urb_wq; 1296 1297 u8 mac_addr[ETH_ALEN]; 1298 char chip_name[8]; 1299 char chip_vendor[8]; 1300 u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1301 u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1302 u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1303 u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1304 /* 1305 * The following entries are half-bytes split as: 1306 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 1307 */ 1308 struct rtl8723au_idx ht40_2s_tx_power_index_diff[ 1309 RTL8723A_CHANNEL_GROUPS]; 1310 struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1311 struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1312 struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1313 struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1314 /* 1315 * Newer generation chips only keep power diffs per TX count, 1316 * not per channel group. 1317 */ 1318 struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT]; 1319 struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT]; 1320 struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT]; 1321 struct rtl8xxxu_power_base *power_base; 1322 u32 chip_cut:4; 1323 u32 rom_rev:4; 1324 u32 is_multi_func:1; 1325 u32 has_wifi:1; 1326 u32 has_bluetooth:1; 1327 u32 enable_bluetooth:1; 1328 u32 has_gps:1; 1329 u32 hi_pa:1; 1330 u32 vendor_umc:1; 1331 u32 vendor_smic:1; 1332 u32 has_polarity_ctrl:1; 1333 u32 has_eeprom:1; 1334 u32 boot_eeprom:1; 1335 u32 usb_interrupts:1; 1336 u32 ep_tx_high_queue:1; 1337 u32 ep_tx_normal_queue:1; 1338 u32 ep_tx_low_queue:1; 1339 u32 has_xtalk:1; 1340 u32 rx_buf_aggregation:1; 1341 u8 xtalk; 1342 unsigned int pipe_interrupt; 1343 unsigned int pipe_in; 1344 unsigned int pipe_out[TXDESC_QUEUE_MAX]; 1345 u8 out_ep[RTL8XXXU_OUT_ENDPOINTS]; 1346 u8 ep_tx_count; 1347 u8 rf_paths; 1348 u8 rx_paths; 1349 u8 tx_paths; 1350 u32 rege94; 1351 u32 rege9c; 1352 u32 regeb4; 1353 u32 regebc; 1354 int next_mbox; 1355 int nr_out_eps; 1356 1357 struct mutex h2c_mutex; 1358 1359 struct usb_anchor rx_anchor; 1360 struct usb_anchor tx_anchor; 1361 struct usb_anchor int_anchor; 1362 struct rtl8xxxu_firmware_header *fw_data; 1363 size_t fw_size; 1364 struct mutex usb_buf_mutex; 1365 union { 1366 __le32 val32; 1367 __le16 val16; 1368 u8 val8; 1369 } usb_buf; 1370 union { 1371 u8 raw[EFUSE_MAP_LEN]; 1372 struct rtl8723au_efuse efuse8723; 1373 struct rtl8723bu_efuse efuse8723bu; 1374 struct rtl8192cu_efuse efuse8192; 1375 struct rtl8192eu_efuse efuse8192eu; 1376 } efuse_wifi; 1377 u32 adda_backup[RTL8XXXU_ADDA_REGS]; 1378 u32 mac_backup[RTL8XXXU_MAC_REGS]; 1379 u32 bb_backup[RTL8XXXU_BB_REGS]; 1380 u32 bb_recovery_backup[RTL8XXXU_BB_REGS]; 1381 enum rtl8xxxu_rtl_chip rtl_chip; 1382 u8 pi_enabled:1; 1383 u8 no_pape:1; 1384 u8 int_buf[USB_INTR_CONTENT_LENGTH]; 1385 u8 rssi_level; 1386 /* 1387 * Only one virtual interface permitted because only STA mode 1388 * is supported and no iface_combinations are provided. 1389 */ 1390 struct ieee80211_vif *vif; 1391 struct delayed_work ra_watchdog; 1392 struct work_struct c2hcmd_work; 1393 struct sk_buff_head c2hcmd_queue; 1394 spinlock_t c2hcmd_lock; 1395 struct rtl8xxxu_btcoex bt_coex; 1396 struct rtl8xxxu_ra_report ra_report; 1397 }; 1398 1399 struct rtl8xxxu_rx_urb { 1400 struct urb urb; 1401 struct ieee80211_hw *hw; 1402 struct list_head list; 1403 }; 1404 1405 struct rtl8xxxu_tx_urb { 1406 struct urb urb; 1407 struct ieee80211_hw *hw; 1408 struct list_head list; 1409 }; 1410 1411 struct rtl8xxxu_fileops { 1412 int (*parse_efuse) (struct rtl8xxxu_priv *priv); 1413 int (*load_firmware) (struct rtl8xxxu_priv *priv); 1414 int (*power_on) (struct rtl8xxxu_priv *priv); 1415 void (*power_off) (struct rtl8xxxu_priv *priv); 1416 void (*reset_8051) (struct rtl8xxxu_priv *priv); 1417 int (*llt_init) (struct rtl8xxxu_priv *priv); 1418 void (*init_phy_bb) (struct rtl8xxxu_priv *priv); 1419 int (*init_phy_rf) (struct rtl8xxxu_priv *priv); 1420 void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv); 1421 void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv); 1422 void (*config_channel) (struct ieee80211_hw *hw); 1423 int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb); 1424 void (*init_aggregation) (struct rtl8xxxu_priv *priv); 1425 void (*init_statistics) (struct rtl8xxxu_priv *priv); 1426 void (*enable_rf) (struct rtl8xxxu_priv *priv); 1427 void (*disable_rf) (struct rtl8xxxu_priv *priv); 1428 void (*usb_quirks) (struct rtl8xxxu_priv *priv); 1429 void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel, 1430 bool ht40); 1431 void (*update_rate_mask) (struct rtl8xxxu_priv *priv, 1432 u32 ramask, u8 rateid, int sgi); 1433 void (*report_connect) (struct rtl8xxxu_priv *priv, 1434 u8 macid, bool connect); 1435 void (*fill_txdesc) (struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 1436 struct ieee80211_tx_info *tx_info, 1437 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 1438 bool short_preamble, bool ampdu_enable, 1439 u32 rts_rate); 1440 int writeN_block_size; 1441 int rx_agg_buf_size; 1442 char tx_desc_size; 1443 char rx_desc_size; 1444 u8 has_s0s1:1; 1445 u8 has_tx_report:1; 1446 u8 gen2_thermal_meter:1; 1447 u8 needs_full_init:1; 1448 u32 adda_1t_init; 1449 u32 adda_1t_path_on; 1450 u32 adda_2t_path_on_a; 1451 u32 adda_2t_path_on_b; 1452 u16 trxff_boundary; 1453 u8 pbp_rx; 1454 u8 pbp_tx; 1455 struct rtl8xxxu_reg8val *mactable; 1456 u8 total_page_num; 1457 u8 page_num_hi; 1458 u8 page_num_lo; 1459 u8 page_num_norm; 1460 }; 1461 1462 extern int rtl8xxxu_debug; 1463 1464 extern struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[]; 1465 extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[]; 1466 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr); 1467 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr); 1468 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr); 1469 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val); 1470 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val); 1471 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val); 1472 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 1473 enum rtl8xxxu_rfpath path, u8 reg); 1474 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 1475 enum rtl8xxxu_rfpath path, u8 reg, u32 data); 1476 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 1477 u32 *backup, int count); 1478 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 1479 u32 *backup, int count); 1480 void rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, 1481 const u32 *reg, u32 *backup); 1482 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 1483 const u32 *reg, u32 *backup); 1484 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 1485 bool path_a_on); 1486 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 1487 const u32 *regs, u32 *backup); 1488 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 1489 int result[][8], int candidate, bool tx_only); 1490 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 1491 int result[][8], int candidate, bool tx_only); 1492 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 1493 struct rtl8xxxu_rfregval *table, 1494 enum rtl8xxxu_rfpath path); 1495 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 1496 struct rtl8xxxu_reg32val *array); 1497 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name); 1498 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv); 1499 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv); 1500 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv); 1501 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv); 1502 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start); 1503 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv); 1504 int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, 1505 struct h2c_cmd *h2c, int len); 1506 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv); 1507 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv); 1508 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv); 1509 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv); 1510 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv); 1511 void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, 1512 int channel, bool ht40); 1513 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw); 1514 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw); 1515 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv); 1516 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv); 1517 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, 1518 u32 ramask, u8 rateid, int sgi); 1519 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 1520 u32 ramask, u8 rateid, int sgi); 1521 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 1522 u8 macid, bool connect); 1523 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 1524 u8 macid, bool connect); 1525 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv); 1526 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv); 1527 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv); 1528 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv); 1529 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 1530 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 1531 int rtl8xxxu_gen2_channel_to_group(int channel); 1532 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 1533 int result[][8], int c1, int c2); 1534 void rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 1535 struct ieee80211_tx_info *tx_info, 1536 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 1537 bool short_preamble, bool ampdu_enable, 1538 u32 rts_rate); 1539 void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 1540 struct ieee80211_tx_info *tx_info, 1541 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 1542 bool short_preamble, bool ampdu_enable, 1543 u32 rts_rate); 1544 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 1545 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5); 1546 1547 extern struct rtl8xxxu_fileops rtl8192cu_fops; 1548 extern struct rtl8xxxu_fileops rtl8192eu_fops; 1549 extern struct rtl8xxxu_fileops rtl8723au_fops; 1550 extern struct rtl8xxxu_fileops rtl8723bu_fops; 1551
