1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * USB4 specific functionality
4 *
5 * Copyright (C) 2019, Intel Corporation
6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Rajmohan Mani <rajmohan.mani@intel.com>
8 */
9
10 #include <linux/delay.h>
11 #include <linux/ktime.h>
12
13 #include "sb_regs.h"
14 #include "tb.h"
15
16 #define USB4_DATA_DWORDS 16
17 #define USB4_DATA_RETRIES 3
18
19 enum usb4_switch_op {
20 USB4_SWITCH_OP_QUERY_DP_RESOURCE = 0x10,
21 USB4_SWITCH_OP_ALLOC_DP_RESOURCE = 0x11,
22 USB4_SWITCH_OP_DEALLOC_DP_RESOURCE = 0x12,
23 USB4_SWITCH_OP_NVM_WRITE = 0x20,
24 USB4_SWITCH_OP_NVM_AUTH = 0x21,
25 USB4_SWITCH_OP_NVM_READ = 0x22,
26 USB4_SWITCH_OP_NVM_SET_OFFSET = 0x23,
27 USB4_SWITCH_OP_DROM_READ = 0x24,
28 USB4_SWITCH_OP_NVM_SECTOR_SIZE = 0x25,
29 };
30
31 enum usb4_sb_target {
32 USB4_SB_TARGET_ROUTER,
33 USB4_SB_TARGET_PARTNER,
34 USB4_SB_TARGET_RETIMER,
35 };
36
37 #define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2)
38 #define USB4_NVM_READ_OFFSET_SHIFT 2
39 #define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24)
40 #define USB4_NVM_READ_LENGTH_SHIFT 24
41
42 #define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK
43 #define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT
44
45 #define USB4_DROM_ADDRESS_MASK GENMASK(14, 2)
46 #define USB4_DROM_ADDRESS_SHIFT 2
47 #define USB4_DROM_SIZE_MASK GENMASK(19, 15)
48 #define USB4_DROM_SIZE_SHIFT 15
49
50 #define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0)
51
52 typedef int (*read_block_fn)(void *, unsigned int, void *, size_t);
53 typedef int (*write_block_fn)(void *, const void *, size_t);
54
usb4_switch_wait_for_bit(struct tb_switch * sw,u32 offset,u32 bit,u32 value,int timeout_msec)55 static int usb4_switch_wait_for_bit(struct tb_switch *sw, u32 offset, u32 bit,
56 u32 value, int timeout_msec)
57 {
58 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec);
59
60 do {
61 u32 val;
62 int ret;
63
64 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1);
65 if (ret)
66 return ret;
67
68 if ((val & bit) == value)
69 return 0;
70
71 usleep_range(50, 100);
72 } while (ktime_before(ktime_get(), timeout));
73
74 return -ETIMEDOUT;
75 }
76
usb4_switch_op_read_data(struct tb_switch * sw,void * data,size_t dwords)77 static int usb4_switch_op_read_data(struct tb_switch *sw, void *data,
78 size_t dwords)
79 {
80 if (dwords > USB4_DATA_DWORDS)
81 return -EINVAL;
82
83 return tb_sw_read(sw, data, TB_CFG_SWITCH, ROUTER_CS_9, dwords);
84 }
85
usb4_switch_op_write_data(struct tb_switch * sw,const void * data,size_t dwords)86 static int usb4_switch_op_write_data(struct tb_switch *sw, const void *data,
87 size_t dwords)
88 {
89 if (dwords > USB4_DATA_DWORDS)
90 return -EINVAL;
91
92 return tb_sw_write(sw, data, TB_CFG_SWITCH, ROUTER_CS_9, dwords);
93 }
94
usb4_switch_op_read_metadata(struct tb_switch * sw,u32 * metadata)95 static int usb4_switch_op_read_metadata(struct tb_switch *sw, u32 *metadata)
96 {
97 return tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
98 }
99
usb4_switch_op_write_metadata(struct tb_switch * sw,u32 metadata)100 static int usb4_switch_op_write_metadata(struct tb_switch *sw, u32 metadata)
101 {
102 return tb_sw_write(sw, &metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
103 }
104
usb4_do_read_data(u16 address,void * buf,size_t size,read_block_fn read_block,void * read_block_data)105 static int usb4_do_read_data(u16 address, void *buf, size_t size,
106 read_block_fn read_block, void *read_block_data)
107 {
108 unsigned int retries = USB4_DATA_RETRIES;
109 unsigned int offset;
110
111 offset = address & 3;
112 address = address & ~3;
113
114 do {
115 size_t nbytes = min_t(size_t, size, USB4_DATA_DWORDS * 4);
116 unsigned int dwaddress, dwords;
117 u8 data[USB4_DATA_DWORDS * 4];
118 int ret;
119
120 dwaddress = address / 4;
121 dwords = ALIGN(nbytes, 4) / 4;
122
123 ret = read_block(read_block_data, dwaddress, data, dwords);
124 if (ret) {
125 if (ret != -ENODEV && retries--)
126 continue;
127 return ret;
128 }
129
130 memcpy(buf, data + offset, nbytes);
131
132 size -= nbytes;
133 address += nbytes;
134 buf += nbytes;
135 } while (size > 0);
136
137 return 0;
138 }
139
usb4_do_write_data(unsigned int address,const void * buf,size_t size,write_block_fn write_next_block,void * write_block_data)140 static int usb4_do_write_data(unsigned int address, const void *buf, size_t size,
141 write_block_fn write_next_block, void *write_block_data)
142 {
143 unsigned int retries = USB4_DATA_RETRIES;
144 unsigned int offset;
145
146 offset = address & 3;
147 address = address & ~3;
148
149 do {
150 u32 nbytes = min_t(u32, size, USB4_DATA_DWORDS * 4);
151 u8 data[USB4_DATA_DWORDS * 4];
152 int ret;
153
154 memcpy(data + offset, buf, nbytes);
155
156 ret = write_next_block(write_block_data, data, nbytes / 4);
157 if (ret) {
158 if (ret == -ETIMEDOUT) {
159 if (retries--)
160 continue;
161 ret = -EIO;
162 }
163 return ret;
164 }
165
166 size -= nbytes;
167 address += nbytes;
168 buf += nbytes;
169 } while (size > 0);
170
171 return 0;
172 }
173
usb4_switch_op(struct tb_switch * sw,u16 opcode,u8 * status)174 static int usb4_switch_op(struct tb_switch *sw, u16 opcode, u8 *status)
175 {
176 u32 val;
177 int ret;
178
179 val = opcode | ROUTER_CS_26_OV;
180 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
181 if (ret)
182 return ret;
183
184 ret = usb4_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500);
185 if (ret)
186 return ret;
187
188 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
189 if (ret)
190 return ret;
191
192 if (val & ROUTER_CS_26_ONS)
193 return -EOPNOTSUPP;
194
195 *status = (val & ROUTER_CS_26_STATUS_MASK) >> ROUTER_CS_26_STATUS_SHIFT;
196 return 0;
197 }
198
usb4_switch_check_wakes(struct tb_switch * sw)199 static void usb4_switch_check_wakes(struct tb_switch *sw)
200 {
201 struct tb_port *port;
202 bool wakeup = false;
203 u32 val;
204
205 if (!device_may_wakeup(&sw->dev))
206 return;
207
208 if (tb_route(sw)) {
209 if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1))
210 return;
211
212 tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n",
213 (val & ROUTER_CS_6_WOPS) ? "yes" : "no",
214 (val & ROUTER_CS_6_WOUS) ? "yes" : "no");
215
216 wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS);
217 }
218
219 /* Check for any connected downstream ports for USB4 wake */
220 tb_switch_for_each_port(sw, port) {
221 if (!tb_port_has_remote(port))
222 continue;
223
224 if (tb_port_read(port, &val, TB_CFG_PORT,
225 port->cap_usb4 + PORT_CS_18, 1))
226 break;
227
228 tb_port_dbg(port, "USB4 wake: %s\n",
229 (val & PORT_CS_18_WOU4S) ? "yes" : "no");
230
231 if (val & PORT_CS_18_WOU4S)
232 wakeup = true;
233 }
234
235 if (wakeup)
236 pm_wakeup_event(&sw->dev, 0);
237 }
238
link_is_usb4(struct tb_port * port)239 static bool link_is_usb4(struct tb_port *port)
240 {
241 u32 val;
242
243 if (!port->cap_usb4)
244 return false;
245
246 if (tb_port_read(port, &val, TB_CFG_PORT,
247 port->cap_usb4 + PORT_CS_18, 1))
248 return false;
249
250 return !(val & PORT_CS_18_TCM);
251 }
252
253 /**
254 * usb4_switch_setup() - Additional setup for USB4 device
255 * @sw: USB4 router to setup
256 *
257 * USB4 routers need additional settings in order to enable all the
258 * tunneling. This function enables USB and PCIe tunneling if it can be
259 * enabled (e.g the parent switch also supports them). If USB tunneling
260 * is not available for some reason (like that there is Thunderbolt 3
261 * switch upstream) then the internal xHCI controller is enabled
262 * instead.
263 */
usb4_switch_setup(struct tb_switch * sw)264 int usb4_switch_setup(struct tb_switch *sw)
265 {
266 struct tb_port *downstream_port;
267 struct tb_switch *parent;
268 bool tbt3, xhci;
269 u32 val = 0;
270 int ret;
271
272 usb4_switch_check_wakes(sw);
273
274 if (!tb_route(sw))
275 return 0;
276
277 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1);
278 if (ret)
279 return ret;
280
281 parent = tb_switch_parent(sw);
282 downstream_port = tb_port_at(tb_route(sw), parent);
283 sw->link_usb4 = link_is_usb4(downstream_port);
284 tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT3");
285
286 xhci = val & ROUTER_CS_6_HCI;
287 tbt3 = !(val & ROUTER_CS_6_TNS);
288
289 tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n",
290 tbt3 ? "yes" : "no", xhci ? "yes" : "no");
291
292 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
293 if (ret)
294 return ret;
295
296 if (sw->link_usb4 && tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) {
297 val |= ROUTER_CS_5_UTO;
298 xhci = false;
299 }
300
301 /* Only enable PCIe tunneling if the parent router supports it */
302 if (tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) {
303 val |= ROUTER_CS_5_PTO;
304 /*
305 * xHCI can be enabled if PCIe tunneling is supported
306 * and the parent does not have any USB3 dowstream
307 * adapters (so we cannot do USB 3.x tunneling).
308 */
309 if (xhci)
310 val |= ROUTER_CS_5_HCO;
311 }
312
313 /* TBT3 supported by the CM */
314 val |= ROUTER_CS_5_C3S;
315 /* Tunneling configuration is ready now */
316 val |= ROUTER_CS_5_CV;
317
318 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
319 if (ret)
320 return ret;
321
322 return usb4_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR,
323 ROUTER_CS_6_CR, 50);
324 }
325
326 /**
327 * usb4_switch_read_uid() - Read UID from USB4 router
328 * @sw: USB4 router
329 * @uid: UID is stored here
330 *
331 * Reads 64-bit UID from USB4 router config space.
332 */
usb4_switch_read_uid(struct tb_switch * sw,u64 * uid)333 int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid)
334 {
335 return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2);
336 }
337
usb4_switch_drom_read_block(void * data,unsigned int dwaddress,void * buf,size_t dwords)338 static int usb4_switch_drom_read_block(void *data,
339 unsigned int dwaddress, void *buf,
340 size_t dwords)
341 {
342 struct tb_switch *sw = data;
343 u8 status = 0;
344 u32 metadata;
345 int ret;
346
347 metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK;
348 metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) &
349 USB4_DROM_ADDRESS_MASK;
350
351 ret = usb4_switch_op_write_metadata(sw, metadata);
352 if (ret)
353 return ret;
354
355 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DROM_READ, &status);
356 if (ret)
357 return ret;
358
359 if (status)
360 return -EIO;
361
362 return usb4_switch_op_read_data(sw, buf, dwords);
363 }
364
365 /**
366 * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM
367 * @sw: USB4 router
368 * @address: Byte address inside DROM to start reading
369 * @buf: Buffer where the DROM content is stored
370 * @size: Number of bytes to read from DROM
371 *
372 * Uses USB4 router operations to read router DROM. For devices this
373 * should always work but for hosts it may return %-EOPNOTSUPP in which
374 * case the host router does not have DROM.
375 */
usb4_switch_drom_read(struct tb_switch * sw,unsigned int address,void * buf,size_t size)376 int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf,
377 size_t size)
378 {
379 return usb4_do_read_data(address, buf, size,
380 usb4_switch_drom_read_block, sw);
381 }
382
383 /**
384 * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding
385 * @sw: USB4 router
386 *
387 * Checks whether conditions are met so that lane bonding can be
388 * established with the upstream router. Call only for device routers.
389 */
usb4_switch_lane_bonding_possible(struct tb_switch * sw)390 bool usb4_switch_lane_bonding_possible(struct tb_switch *sw)
391 {
392 struct tb_port *up;
393 int ret;
394 u32 val;
395
396 up = tb_upstream_port(sw);
397 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1);
398 if (ret)
399 return false;
400
401 return !!(val & PORT_CS_18_BE);
402 }
403
404 /**
405 * usb4_switch_set_wake() - Enabled/disable wake
406 * @sw: USB4 router
407 * @flags: Wakeup flags (%0 to disable)
408 *
409 * Enables/disables router to wake up from sleep.
410 */
usb4_switch_set_wake(struct tb_switch * sw,unsigned int flags)411 int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags)
412 {
413 struct tb_port *port;
414 u64 route = tb_route(sw);
415 u32 val;
416 int ret;
417
418 /*
419 * Enable wakes coming from all USB4 downstream ports (from
420 * child routers). For device routers do this also for the
421 * upstream USB4 port.
422 */
423 tb_switch_for_each_port(sw, port) {
424 if (!tb_port_is_null(port))
425 continue;
426 if (!route && tb_is_upstream_port(port))
427 continue;
428 if (!port->cap_usb4)
429 continue;
430
431 ret = tb_port_read(port, &val, TB_CFG_PORT,
432 port->cap_usb4 + PORT_CS_19, 1);
433 if (ret)
434 return ret;
435
436 val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4);
437
438 if (flags & TB_WAKE_ON_CONNECT)
439 val |= PORT_CS_19_WOC;
440 if (flags & TB_WAKE_ON_DISCONNECT)
441 val |= PORT_CS_19_WOD;
442 if (flags & TB_WAKE_ON_USB4)
443 val |= PORT_CS_19_WOU4;
444
445 ret = tb_port_write(port, &val, TB_CFG_PORT,
446 port->cap_usb4 + PORT_CS_19, 1);
447 if (ret)
448 return ret;
449 }
450
451 /*
452 * Enable wakes from PCIe and USB 3.x on this router. Only
453 * needed for device routers.
454 */
455 if (route) {
456 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
457 if (ret)
458 return ret;
459
460 val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU);
461 if (flags & TB_WAKE_ON_USB3)
462 val |= ROUTER_CS_5_WOU;
463 if (flags & TB_WAKE_ON_PCIE)
464 val |= ROUTER_CS_5_WOP;
465
466 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
467 if (ret)
468 return ret;
469 }
470
471 return 0;
472 }
473
474 /**
475 * usb4_switch_set_sleep() - Prepare the router to enter sleep
476 * @sw: USB4 router
477 *
478 * Sets sleep bit for the router. Returns when the router sleep ready
479 * bit has been asserted.
480 */
usb4_switch_set_sleep(struct tb_switch * sw)481 int usb4_switch_set_sleep(struct tb_switch *sw)
482 {
483 int ret;
484 u32 val;
485
486 /* Set sleep bit and wait for sleep ready to be asserted */
487 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
488 if (ret)
489 return ret;
490
491 val |= ROUTER_CS_5_SLP;
492
493 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
494 if (ret)
495 return ret;
496
497 return usb4_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR,
498 ROUTER_CS_6_SLPR, 500);
499 }
500
501 /**
502 * usb4_switch_nvm_sector_size() - Return router NVM sector size
503 * @sw: USB4 router
504 *
505 * If the router supports NVM operations this function returns the NVM
506 * sector size in bytes. If NVM operations are not supported returns
507 * %-EOPNOTSUPP.
508 */
usb4_switch_nvm_sector_size(struct tb_switch * sw)509 int usb4_switch_nvm_sector_size(struct tb_switch *sw)
510 {
511 u32 metadata;
512 u8 status;
513 int ret;
514
515 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &status);
516 if (ret)
517 return ret;
518
519 if (status)
520 return status == 0x2 ? -EOPNOTSUPP : -EIO;
521
522 ret = usb4_switch_op_read_metadata(sw, &metadata);
523 if (ret)
524 return ret;
525
526 return metadata & USB4_NVM_SECTOR_SIZE_MASK;
527 }
528
usb4_switch_nvm_read_block(void * data,unsigned int dwaddress,void * buf,size_t dwords)529 static int usb4_switch_nvm_read_block(void *data,
530 unsigned int dwaddress, void *buf, size_t dwords)
531 {
532 struct tb_switch *sw = data;
533 u8 status = 0;
534 u32 metadata;
535 int ret;
536
537 metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) &
538 USB4_NVM_READ_LENGTH_MASK;
539 metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) &
540 USB4_NVM_READ_OFFSET_MASK;
541
542 ret = usb4_switch_op_write_metadata(sw, metadata);
543 if (ret)
544 return ret;
545
546 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_READ, &status);
547 if (ret)
548 return ret;
549
550 if (status)
551 return -EIO;
552
553 return usb4_switch_op_read_data(sw, buf, dwords);
554 }
555
556 /**
557 * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM
558 * @sw: USB4 router
559 * @address: Starting address in bytes
560 * @buf: Read data is placed here
561 * @size: How many bytes to read
562 *
563 * Reads NVM contents of the router. If NVM is not supported returns
564 * %-EOPNOTSUPP.
565 */
usb4_switch_nvm_read(struct tb_switch * sw,unsigned int address,void * buf,size_t size)566 int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf,
567 size_t size)
568 {
569 return usb4_do_read_data(address, buf, size,
570 usb4_switch_nvm_read_block, sw);
571 }
572
usb4_switch_nvm_set_offset(struct tb_switch * sw,unsigned int address)573 static int usb4_switch_nvm_set_offset(struct tb_switch *sw,
574 unsigned int address)
575 {
576 u32 metadata, dwaddress;
577 u8 status = 0;
578 int ret;
579
580 dwaddress = address / 4;
581 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
582 USB4_NVM_SET_OFFSET_MASK;
583
584 ret = usb4_switch_op_write_metadata(sw, metadata);
585 if (ret)
586 return ret;
587
588 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &status);
589 if (ret)
590 return ret;
591
592 return status ? -EIO : 0;
593 }
594
usb4_switch_nvm_write_next_block(void * data,const void * buf,size_t dwords)595 static int usb4_switch_nvm_write_next_block(void *data, const void *buf,
596 size_t dwords)
597 {
598 struct tb_switch *sw = data;
599 u8 status;
600 int ret;
601
602 ret = usb4_switch_op_write_data(sw, buf, dwords);
603 if (ret)
604 return ret;
605
606 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_WRITE, &status);
607 if (ret)
608 return ret;
609
610 return status ? -EIO : 0;
611 }
612
613 /**
614 * usb4_switch_nvm_write() - Write to the router NVM
615 * @sw: USB4 router
616 * @address: Start address where to write in bytes
617 * @buf: Pointer to the data to write
618 * @size: Size of @buf in bytes
619 *
620 * Writes @buf to the router NVM using USB4 router operations. If NVM
621 * write is not supported returns %-EOPNOTSUPP.
622 */
usb4_switch_nvm_write(struct tb_switch * sw,unsigned int address,const void * buf,size_t size)623 int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address,
624 const void *buf, size_t size)
625 {
626 int ret;
627
628 ret = usb4_switch_nvm_set_offset(sw, address);
629 if (ret)
630 return ret;
631
632 return usb4_do_write_data(address, buf, size,
633 usb4_switch_nvm_write_next_block, sw);
634 }
635
636 /**
637 * usb4_switch_nvm_authenticate() - Authenticate new NVM
638 * @sw: USB4 router
639 *
640 * After the new NVM has been written via usb4_switch_nvm_write(), this
641 * function triggers NVM authentication process. If the authentication
642 * is successful the router is power cycled and the new NVM starts
643 * running. In case of failure returns negative errno.
644 */
usb4_switch_nvm_authenticate(struct tb_switch * sw)645 int usb4_switch_nvm_authenticate(struct tb_switch *sw)
646 {
647 u8 status = 0;
648 int ret;
649
650 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, &status);
651 if (ret)
652 return ret;
653
654 switch (status) {
655 case 0x0:
656 tb_sw_dbg(sw, "NVM authentication successful\n");
657 return 0;
658 case 0x1:
659 return -EINVAL;
660 case 0x2:
661 return -EAGAIN;
662 case 0x3:
663 return -EOPNOTSUPP;
664 default:
665 return -EIO;
666 }
667 }
668
669 /**
670 * usb4_switch_query_dp_resource() - Query availability of DP IN resource
671 * @sw: USB4 router
672 * @in: DP IN adapter
673 *
674 * For DP tunneling this function can be used to query availability of
675 * DP IN resource. Returns true if the resource is available for DP
676 * tunneling, false otherwise.
677 */
usb4_switch_query_dp_resource(struct tb_switch * sw,struct tb_port * in)678 bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in)
679 {
680 u8 status;
681 int ret;
682
683 ret = usb4_switch_op_write_metadata(sw, in->port);
684 if (ret)
685 return false;
686
687 ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &status);
688 /*
689 * If DP resource allocation is not supported assume it is
690 * always available.
691 */
692 if (ret == -EOPNOTSUPP)
693 return true;
694 else if (ret)
695 return false;
696
697 return !status;
698 }
699
700 /**
701 * usb4_switch_alloc_dp_resource() - Allocate DP IN resource
702 * @sw: USB4 router
703 * @in: DP IN adapter
704 *
705 * Allocates DP IN resource for DP tunneling using USB4 router
706 * operations. If the resource was allocated returns %0. Otherwise
707 * returns negative errno, in particular %-EBUSY if the resource is
708 * already allocated.
709 */
usb4_switch_alloc_dp_resource(struct tb_switch * sw,struct tb_port * in)710 int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
711 {
712 u8 status;
713 int ret;
714
715 ret = usb4_switch_op_write_metadata(sw, in->port);
716 if (ret)
717 return ret;
718
719 ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &status);
720 if (ret == -EOPNOTSUPP)
721 return 0;
722 else if (ret)
723 return ret;
724
725 return status ? -EBUSY : 0;
726 }
727
728 /**
729 * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource
730 * @sw: USB4 router
731 * @in: DP IN adapter
732 *
733 * Releases the previously allocated DP IN resource.
734 */
usb4_switch_dealloc_dp_resource(struct tb_switch * sw,struct tb_port * in)735 int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
736 {
737 u8 status;
738 int ret;
739
740 ret = usb4_switch_op_write_metadata(sw, in->port);
741 if (ret)
742 return ret;
743
744 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &status);
745 if (ret == -EOPNOTSUPP)
746 return 0;
747 else if (ret)
748 return ret;
749
750 return status ? -EIO : 0;
751 }
752
usb4_port_idx(const struct tb_switch * sw,const struct tb_port * port)753 static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port)
754 {
755 struct tb_port *p;
756 int usb4_idx = 0;
757
758 /* Assume port is primary */
759 tb_switch_for_each_port(sw, p) {
760 if (!tb_port_is_null(p))
761 continue;
762 if (tb_is_upstream_port(p))
763 continue;
764 if (!p->link_nr) {
765 if (p == port)
766 break;
767 usb4_idx++;
768 }
769 }
770
771 return usb4_idx;
772 }
773
774 /**
775 * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter
776 * @sw: USB4 router
777 * @port: USB4 port
778 *
779 * USB4 routers have direct mapping between USB4 ports and PCIe
780 * downstream adapters where the PCIe topology is extended. This
781 * function returns the corresponding downstream PCIe adapter or %NULL
782 * if no such mapping was possible.
783 */
usb4_switch_map_pcie_down(struct tb_switch * sw,const struct tb_port * port)784 struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw,
785 const struct tb_port *port)
786 {
787 int usb4_idx = usb4_port_idx(sw, port);
788 struct tb_port *p;
789 int pcie_idx = 0;
790
791 /* Find PCIe down port matching usb4_port */
792 tb_switch_for_each_port(sw, p) {
793 if (!tb_port_is_pcie_down(p))
794 continue;
795
796 if (pcie_idx == usb4_idx)
797 return p;
798
799 pcie_idx++;
800 }
801
802 return NULL;
803 }
804
805 /**
806 * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter
807 * @sw: USB4 router
808 * @port: USB4 port
809 *
810 * USB4 routers have direct mapping between USB4 ports and USB 3.x
811 * downstream adapters where the USB 3.x topology is extended. This
812 * function returns the corresponding downstream USB 3.x adapter or
813 * %NULL if no such mapping was possible.
814 */
usb4_switch_map_usb3_down(struct tb_switch * sw,const struct tb_port * port)815 struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw,
816 const struct tb_port *port)
817 {
818 int usb4_idx = usb4_port_idx(sw, port);
819 struct tb_port *p;
820 int usb_idx = 0;
821
822 /* Find USB3 down port matching usb4_port */
823 tb_switch_for_each_port(sw, p) {
824 if (!tb_port_is_usb3_down(p))
825 continue;
826
827 if (usb_idx == usb4_idx)
828 return p;
829
830 usb_idx++;
831 }
832
833 return NULL;
834 }
835
836 /**
837 * usb4_port_unlock() - Unlock USB4 downstream port
838 * @port: USB4 port to unlock
839 *
840 * Unlocks USB4 downstream port so that the connection manager can
841 * access the router below this port.
842 */
usb4_port_unlock(struct tb_port * port)843 int usb4_port_unlock(struct tb_port *port)
844 {
845 int ret;
846 u32 val;
847
848 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
849 if (ret)
850 return ret;
851
852 val &= ~ADP_CS_4_LCK;
853 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
854 }
855
usb4_port_set_configured(struct tb_port * port,bool configured)856 static int usb4_port_set_configured(struct tb_port *port, bool configured)
857 {
858 int ret;
859 u32 val;
860
861 if (!port->cap_usb4)
862 return -EINVAL;
863
864 ret = tb_port_read(port, &val, TB_CFG_PORT,
865 port->cap_usb4 + PORT_CS_19, 1);
866 if (ret)
867 return ret;
868
869 if (configured)
870 val |= PORT_CS_19_PC;
871 else
872 val &= ~PORT_CS_19_PC;
873
874 return tb_port_write(port, &val, TB_CFG_PORT,
875 port->cap_usb4 + PORT_CS_19, 1);
876 }
877
878 /**
879 * usb4_port_configure() - Set USB4 port configured
880 * @port: USB4 router
881 *
882 * Sets the USB4 link to be configured for power management purposes.
883 */
usb4_port_configure(struct tb_port * port)884 int usb4_port_configure(struct tb_port *port)
885 {
886 return usb4_port_set_configured(port, true);
887 }
888
889 /**
890 * usb4_port_unconfigure() - Set USB4 port unconfigured
891 * @port: USB4 router
892 *
893 * Sets the USB4 link to be unconfigured for power management purposes.
894 */
usb4_port_unconfigure(struct tb_port * port)895 void usb4_port_unconfigure(struct tb_port *port)
896 {
897 usb4_port_set_configured(port, false);
898 }
899
usb4_set_xdomain_configured(struct tb_port * port,bool configured)900 static int usb4_set_xdomain_configured(struct tb_port *port, bool configured)
901 {
902 int ret;
903 u32 val;
904
905 if (!port->cap_usb4)
906 return -EINVAL;
907
908 ret = tb_port_read(port, &val, TB_CFG_PORT,
909 port->cap_usb4 + PORT_CS_19, 1);
910 if (ret)
911 return ret;
912
913 if (configured)
914 val |= PORT_CS_19_PID;
915 else
916 val &= ~PORT_CS_19_PID;
917
918 return tb_port_write(port, &val, TB_CFG_PORT,
919 port->cap_usb4 + PORT_CS_19, 1);
920 }
921
922 /**
923 * usb4_port_configure_xdomain() - Configure port for XDomain
924 * @port: USB4 port connected to another host
925 *
926 * Marks the USB4 port as being connected to another host. Returns %0 in
927 * success and negative errno in failure.
928 */
usb4_port_configure_xdomain(struct tb_port * port)929 int usb4_port_configure_xdomain(struct tb_port *port)
930 {
931 return usb4_set_xdomain_configured(port, true);
932 }
933
934 /**
935 * usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain
936 * @port: USB4 port that was connected to another host
937 *
938 * Clears USB4 port from being marked as XDomain.
939 */
usb4_port_unconfigure_xdomain(struct tb_port * port)940 void usb4_port_unconfigure_xdomain(struct tb_port *port)
941 {
942 usb4_set_xdomain_configured(port, false);
943 }
944
usb4_port_wait_for_bit(struct tb_port * port,u32 offset,u32 bit,u32 value,int timeout_msec)945 static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit,
946 u32 value, int timeout_msec)
947 {
948 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec);
949
950 do {
951 u32 val;
952 int ret;
953
954 ret = tb_port_read(port, &val, TB_CFG_PORT, offset, 1);
955 if (ret)
956 return ret;
957
958 if ((val & bit) == value)
959 return 0;
960
961 usleep_range(50, 100);
962 } while (ktime_before(ktime_get(), timeout));
963
964 return -ETIMEDOUT;
965 }
966
usb4_port_read_data(struct tb_port * port,void * data,size_t dwords)967 static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords)
968 {
969 if (dwords > USB4_DATA_DWORDS)
970 return -EINVAL;
971
972 return tb_port_read(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
973 dwords);
974 }
975
usb4_port_write_data(struct tb_port * port,const void * data,size_t dwords)976 static int usb4_port_write_data(struct tb_port *port, const void *data,
977 size_t dwords)
978 {
979 if (dwords > USB4_DATA_DWORDS)
980 return -EINVAL;
981
982 return tb_port_write(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
983 dwords);
984 }
985
usb4_port_sb_read(struct tb_port * port,enum usb4_sb_target target,u8 index,u8 reg,void * buf,u8 size)986 static int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target,
987 u8 index, u8 reg, void *buf, u8 size)
988 {
989 size_t dwords = DIV_ROUND_UP(size, 4);
990 int ret;
991 u32 val;
992
993 if (!port->cap_usb4)
994 return -EINVAL;
995
996 val = reg;
997 val |= size << PORT_CS_1_LENGTH_SHIFT;
998 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
999 if (target == USB4_SB_TARGET_RETIMER)
1000 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1001 val |= PORT_CS_1_PND;
1002
1003 ret = tb_port_write(port, &val, TB_CFG_PORT,
1004 port->cap_usb4 + PORT_CS_1, 1);
1005 if (ret)
1006 return ret;
1007
1008 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1009 PORT_CS_1_PND, 0, 500);
1010 if (ret)
1011 return ret;
1012
1013 ret = tb_port_read(port, &val, TB_CFG_PORT,
1014 port->cap_usb4 + PORT_CS_1, 1);
1015 if (ret)
1016 return ret;
1017
1018 if (val & PORT_CS_1_NR)
1019 return -ENODEV;
1020 if (val & PORT_CS_1_RC)
1021 return -EIO;
1022
1023 return buf ? usb4_port_read_data(port, buf, dwords) : 0;
1024 }
1025
usb4_port_sb_write(struct tb_port * port,enum usb4_sb_target target,u8 index,u8 reg,const void * buf,u8 size)1026 static int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target,
1027 u8 index, u8 reg, const void *buf, u8 size)
1028 {
1029 size_t dwords = DIV_ROUND_UP(size, 4);
1030 int ret;
1031 u32 val;
1032
1033 if (!port->cap_usb4)
1034 return -EINVAL;
1035
1036 if (buf) {
1037 ret = usb4_port_write_data(port, buf, dwords);
1038 if (ret)
1039 return ret;
1040 }
1041
1042 val = reg;
1043 val |= size << PORT_CS_1_LENGTH_SHIFT;
1044 val |= PORT_CS_1_WNR_WRITE;
1045 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1046 if (target == USB4_SB_TARGET_RETIMER)
1047 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1048 val |= PORT_CS_1_PND;
1049
1050 ret = tb_port_write(port, &val, TB_CFG_PORT,
1051 port->cap_usb4 + PORT_CS_1, 1);
1052 if (ret)
1053 return ret;
1054
1055 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1056 PORT_CS_1_PND, 0, 500);
1057 if (ret)
1058 return ret;
1059
1060 ret = tb_port_read(port, &val, TB_CFG_PORT,
1061 port->cap_usb4 + PORT_CS_1, 1);
1062 if (ret)
1063 return ret;
1064
1065 if (val & PORT_CS_1_NR)
1066 return -ENODEV;
1067 if (val & PORT_CS_1_RC)
1068 return -EIO;
1069
1070 return 0;
1071 }
1072
usb4_port_sb_op(struct tb_port * port,enum usb4_sb_target target,u8 index,enum usb4_sb_opcode opcode,int timeout_msec)1073 static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target,
1074 u8 index, enum usb4_sb_opcode opcode, int timeout_msec)
1075 {
1076 ktime_t timeout;
1077 u32 val;
1078 int ret;
1079
1080 val = opcode;
1081 ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, &val,
1082 sizeof(val));
1083 if (ret)
1084 return ret;
1085
1086 timeout = ktime_add_ms(ktime_get(), timeout_msec);
1087
1088 do {
1089 /* Check results */
1090 ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE,
1091 &val, sizeof(val));
1092 if (ret)
1093 return ret;
1094
1095 switch (val) {
1096 case 0:
1097 return 0;
1098
1099 case USB4_SB_OPCODE_ERR:
1100 return -EAGAIN;
1101
1102 case USB4_SB_OPCODE_ONS:
1103 return -EOPNOTSUPP;
1104
1105 default:
1106 if (val != opcode)
1107 return -EIO;
1108 break;
1109 }
1110 } while (ktime_before(ktime_get(), timeout));
1111
1112 return -ETIMEDOUT;
1113 }
1114
1115 /**
1116 * usb4_port_enumerate_retimers() - Send RT broadcast transaction
1117 * @port: USB4 port
1118 *
1119 * This forces the USB4 port to send broadcast RT transaction which
1120 * makes the retimers on the link to assign index to themselves. Returns
1121 * %0 in case of success and negative errno if there was an error.
1122 */
usb4_port_enumerate_retimers(struct tb_port * port)1123 int usb4_port_enumerate_retimers(struct tb_port *port)
1124 {
1125 u32 val;
1126
1127 val = USB4_SB_OPCODE_ENUMERATE_RETIMERS;
1128 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1129 USB4_SB_OPCODE, &val, sizeof(val));
1130 }
1131
usb4_port_retimer_op(struct tb_port * port,u8 index,enum usb4_sb_opcode opcode,int timeout_msec)1132 static inline int usb4_port_retimer_op(struct tb_port *port, u8 index,
1133 enum usb4_sb_opcode opcode,
1134 int timeout_msec)
1135 {
1136 return usb4_port_sb_op(port, USB4_SB_TARGET_RETIMER, index, opcode,
1137 timeout_msec);
1138 }
1139
1140 /**
1141 * usb4_port_retimer_read() - Read from retimer sideband registers
1142 * @port: USB4 port
1143 * @index: Retimer index
1144 * @reg: Sideband register to read
1145 * @buf: Data from @reg is stored here
1146 * @size: Number of bytes to read
1147 *
1148 * Function reads retimer sideband registers starting from @reg. The
1149 * retimer is connected to @port at @index. Returns %0 in case of
1150 * success, and read data is copied to @buf. If there is no retimer
1151 * present at given @index returns %-ENODEV. In any other failure
1152 * returns negative errno.
1153 */
usb4_port_retimer_read(struct tb_port * port,u8 index,u8 reg,void * buf,u8 size)1154 int usb4_port_retimer_read(struct tb_port *port, u8 index, u8 reg, void *buf,
1155 u8 size)
1156 {
1157 return usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index, reg, buf,
1158 size);
1159 }
1160
1161 /**
1162 * usb4_port_retimer_write() - Write to retimer sideband registers
1163 * @port: USB4 port
1164 * @index: Retimer index
1165 * @reg: Sideband register to write
1166 * @buf: Data that is written starting from @reg
1167 * @size: Number of bytes to write
1168 *
1169 * Writes retimer sideband registers starting from @reg. The retimer is
1170 * connected to @port at @index. Returns %0 in case of success. If there
1171 * is no retimer present at given @index returns %-ENODEV. In any other
1172 * failure returns negative errno.
1173 */
usb4_port_retimer_write(struct tb_port * port,u8 index,u8 reg,const void * buf,u8 size)1174 int usb4_port_retimer_write(struct tb_port *port, u8 index, u8 reg,
1175 const void *buf, u8 size)
1176 {
1177 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, reg, buf,
1178 size);
1179 }
1180
1181 /**
1182 * usb4_port_retimer_is_last() - Is the retimer last on-board retimer
1183 * @port: USB4 port
1184 * @index: Retimer index
1185 *
1186 * If the retimer at @index is last one (connected directly to the
1187 * Type-C port) this function returns %1. If it is not returns %0. If
1188 * the retimer is not present returns %-ENODEV. Otherwise returns
1189 * negative errno.
1190 */
usb4_port_retimer_is_last(struct tb_port * port,u8 index)1191 int usb4_port_retimer_is_last(struct tb_port *port, u8 index)
1192 {
1193 u32 metadata;
1194 int ret;
1195
1196 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_LAST_RETIMER,
1197 500);
1198 if (ret)
1199 return ret;
1200
1201 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata,
1202 sizeof(metadata));
1203 return ret ? ret : metadata & 1;
1204 }
1205
1206 /**
1207 * usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size
1208 * @port: USB4 port
1209 * @index: Retimer index
1210 *
1211 * Reads NVM sector size (in bytes) of a retimer at @index. This
1212 * operation can be used to determine whether the retimer supports NVM
1213 * upgrade for example. Returns sector size in bytes or negative errno
1214 * in case of error. Specifically returns %-ENODEV if there is no
1215 * retimer at @index.
1216 */
usb4_port_retimer_nvm_sector_size(struct tb_port * port,u8 index)1217 int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index)
1218 {
1219 u32 metadata;
1220 int ret;
1221
1222 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE,
1223 500);
1224 if (ret)
1225 return ret;
1226
1227 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata,
1228 sizeof(metadata));
1229 return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK;
1230 }
1231
usb4_port_retimer_nvm_set_offset(struct tb_port * port,u8 index,unsigned int address)1232 static int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index,
1233 unsigned int address)
1234 {
1235 u32 metadata, dwaddress;
1236 int ret;
1237
1238 dwaddress = address / 4;
1239 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
1240 USB4_NVM_SET_OFFSET_MASK;
1241
1242 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata,
1243 sizeof(metadata));
1244 if (ret)
1245 return ret;
1246
1247 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_SET_OFFSET,
1248 500);
1249 }
1250
1251 struct retimer_info {
1252 struct tb_port *port;
1253 u8 index;
1254 };
1255
usb4_port_retimer_nvm_write_next_block(void * data,const void * buf,size_t dwords)1256 static int usb4_port_retimer_nvm_write_next_block(void *data, const void *buf,
1257 size_t dwords)
1258
1259 {
1260 const struct retimer_info *info = data;
1261 struct tb_port *port = info->port;
1262 u8 index = info->index;
1263 int ret;
1264
1265 ret = usb4_port_retimer_write(port, index, USB4_SB_DATA,
1266 buf, dwords * 4);
1267 if (ret)
1268 return ret;
1269
1270 return usb4_port_retimer_op(port, index,
1271 USB4_SB_OPCODE_NVM_BLOCK_WRITE, 1000);
1272 }
1273
1274 /**
1275 * usb4_port_retimer_nvm_write() - Write to retimer NVM
1276 * @port: USB4 port
1277 * @index: Retimer index
1278 * @address: Byte address where to start the write
1279 * @buf: Data to write
1280 * @size: Size in bytes how much to write
1281 *
1282 * Writes @size bytes from @buf to the retimer NVM. Used for NVM
1283 * upgrade. Returns %0 if the data was written successfully and negative
1284 * errno in case of failure. Specifically returns %-ENODEV if there is
1285 * no retimer at @index.
1286 */
usb4_port_retimer_nvm_write(struct tb_port * port,u8 index,unsigned int address,const void * buf,size_t size)1287 int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address,
1288 const void *buf, size_t size)
1289 {
1290 struct retimer_info info = { .port = port, .index = index };
1291 int ret;
1292
1293 ret = usb4_port_retimer_nvm_set_offset(port, index, address);
1294 if (ret)
1295 return ret;
1296
1297 return usb4_do_write_data(address, buf, size,
1298 usb4_port_retimer_nvm_write_next_block, &info);
1299 }
1300
1301 /**
1302 * usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade
1303 * @port: USB4 port
1304 * @index: Retimer index
1305 *
1306 * After the new NVM image has been written via usb4_port_retimer_nvm_write()
1307 * this function can be used to trigger the NVM upgrade process. If
1308 * successful the retimer restarts with the new NVM and may not have the
1309 * index set so one needs to call usb4_port_enumerate_retimers() to
1310 * force index to be assigned.
1311 */
usb4_port_retimer_nvm_authenticate(struct tb_port * port,u8 index)1312 int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index)
1313 {
1314 u32 val;
1315
1316 /*
1317 * We need to use the raw operation here because once the
1318 * authentication completes the retimer index is not set anymore
1319 * so we do not get back the status now.
1320 */
1321 val = USB4_SB_OPCODE_NVM_AUTH_WRITE;
1322 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
1323 USB4_SB_OPCODE, &val, sizeof(val));
1324 }
1325
1326 /**
1327 * usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade
1328 * @port: USB4 port
1329 * @index: Retimer index
1330 * @status: Raw status code read from metadata
1331 *
1332 * This can be called after usb4_port_retimer_nvm_authenticate() and
1333 * usb4_port_enumerate_retimers() to fetch status of the NVM upgrade.
1334 *
1335 * Returns %0 if the authentication status was successfully read. The
1336 * completion metadata (the result) is then stored into @status. If
1337 * reading the status fails, returns negative errno.
1338 */
usb4_port_retimer_nvm_authenticate_status(struct tb_port * port,u8 index,u32 * status)1339 int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index,
1340 u32 *status)
1341 {
1342 u32 metadata, val;
1343 int ret;
1344
1345 ret = usb4_port_retimer_read(port, index, USB4_SB_OPCODE, &val,
1346 sizeof(val));
1347 if (ret)
1348 return ret;
1349
1350 switch (val) {
1351 case 0:
1352 *status = 0;
1353 return 0;
1354
1355 case USB4_SB_OPCODE_ERR:
1356 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA,
1357 &metadata, sizeof(metadata));
1358 if (ret)
1359 return ret;
1360
1361 *status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK;
1362 return 0;
1363
1364 case USB4_SB_OPCODE_ONS:
1365 return -EOPNOTSUPP;
1366
1367 default:
1368 return -EIO;
1369 }
1370 }
1371
usb4_port_retimer_nvm_read_block(void * data,unsigned int dwaddress,void * buf,size_t dwords)1372 static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress,
1373 void *buf, size_t dwords)
1374 {
1375 const struct retimer_info *info = data;
1376 struct tb_port *port = info->port;
1377 u8 index = info->index;
1378 u32 metadata;
1379 int ret;
1380
1381 metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT;
1382 if (dwords < USB4_DATA_DWORDS)
1383 metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT;
1384
1385 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata,
1386 sizeof(metadata));
1387 if (ret)
1388 return ret;
1389
1390 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_READ, 500);
1391 if (ret)
1392 return ret;
1393
1394 return usb4_port_retimer_read(port, index, USB4_SB_DATA, buf,
1395 dwords * 4);
1396 }
1397
1398 /**
1399 * usb4_port_retimer_nvm_read() - Read contents of retimer NVM
1400 * @port: USB4 port
1401 * @index: Retimer index
1402 * @address: NVM address (in bytes) to start reading
1403 * @buf: Data read from NVM is stored here
1404 * @size: Number of bytes to read
1405 *
1406 * Reads retimer NVM and copies the contents to @buf. Returns %0 if the
1407 * read was successful and negative errno in case of failure.
1408 * Specifically returns %-ENODEV if there is no retimer at @index.
1409 */
usb4_port_retimer_nvm_read(struct tb_port * port,u8 index,unsigned int address,void * buf,size_t size)1410 int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index,
1411 unsigned int address, void *buf, size_t size)
1412 {
1413 struct retimer_info info = { .port = port, .index = index };
1414
1415 return usb4_do_read_data(address, buf, size,
1416 usb4_port_retimer_nvm_read_block, &info);
1417 }
1418
1419 /**
1420 * usb4_usb3_port_max_link_rate() - Maximum support USB3 link rate
1421 * @port: USB3 adapter port
1422 *
1423 * Return maximum supported link rate of a USB3 adapter in Mb/s.
1424 * Negative errno in case of error.
1425 */
usb4_usb3_port_max_link_rate(struct tb_port * port)1426 int usb4_usb3_port_max_link_rate(struct tb_port *port)
1427 {
1428 int ret, lr;
1429 u32 val;
1430
1431 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port))
1432 return -EINVAL;
1433
1434 ret = tb_port_read(port, &val, TB_CFG_PORT,
1435 port->cap_adap + ADP_USB3_CS_4, 1);
1436 if (ret)
1437 return ret;
1438
1439 lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT;
1440 return lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000;
1441 }
1442
1443 /**
1444 * usb4_usb3_port_actual_link_rate() - Established USB3 link rate
1445 * @port: USB3 adapter port
1446 *
1447 * Return actual established link rate of a USB3 adapter in Mb/s. If the
1448 * link is not up returns %0 and negative errno in case of failure.
1449 */
usb4_usb3_port_actual_link_rate(struct tb_port * port)1450 int usb4_usb3_port_actual_link_rate(struct tb_port *port)
1451 {
1452 int ret, lr;
1453 u32 val;
1454
1455 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port))
1456 return -EINVAL;
1457
1458 ret = tb_port_read(port, &val, TB_CFG_PORT,
1459 port->cap_adap + ADP_USB3_CS_4, 1);
1460 if (ret)
1461 return ret;
1462
1463 if (!(val & ADP_USB3_CS_4_ULV))
1464 return 0;
1465
1466 lr = val & ADP_USB3_CS_4_ALR_MASK;
1467 return lr == ADP_USB3_CS_4_ALR_20G ? 20000 : 10000;
1468 }
1469
usb4_usb3_port_cm_request(struct tb_port * port,bool request)1470 static int usb4_usb3_port_cm_request(struct tb_port *port, bool request)
1471 {
1472 int ret;
1473 u32 val;
1474
1475 if (!tb_port_is_usb3_down(port))
1476 return -EINVAL;
1477 if (tb_route(port->sw))
1478 return -EINVAL;
1479
1480 ret = tb_port_read(port, &val, TB_CFG_PORT,
1481 port->cap_adap + ADP_USB3_CS_2, 1);
1482 if (ret)
1483 return ret;
1484
1485 if (request)
1486 val |= ADP_USB3_CS_2_CMR;
1487 else
1488 val &= ~ADP_USB3_CS_2_CMR;
1489
1490 ret = tb_port_write(port, &val, TB_CFG_PORT,
1491 port->cap_adap + ADP_USB3_CS_2, 1);
1492 if (ret)
1493 return ret;
1494
1495 /*
1496 * We can use val here directly as the CMR bit is in the same place
1497 * as HCA. Just mask out others.
1498 */
1499 val &= ADP_USB3_CS_2_CMR;
1500 return usb4_port_wait_for_bit(port, port->cap_adap + ADP_USB3_CS_1,
1501 ADP_USB3_CS_1_HCA, val, 1500);
1502 }
1503
usb4_usb3_port_set_cm_request(struct tb_port * port)1504 static inline int usb4_usb3_port_set_cm_request(struct tb_port *port)
1505 {
1506 return usb4_usb3_port_cm_request(port, true);
1507 }
1508
usb4_usb3_port_clear_cm_request(struct tb_port * port)1509 static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port)
1510 {
1511 return usb4_usb3_port_cm_request(port, false);
1512 }
1513
usb3_bw_to_mbps(u32 bw,u8 scale)1514 static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale)
1515 {
1516 unsigned long uframes;
1517
1518 uframes = bw * 512UL << scale;
1519 return DIV_ROUND_CLOSEST(uframes * 8000, 1000 * 1000);
1520 }
1521
mbps_to_usb3_bw(unsigned int mbps,u8 scale)1522 static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale)
1523 {
1524 unsigned long uframes;
1525
1526 /* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */
1527 uframes = ((unsigned long)mbps * 1000 * 1000) / 8000;
1528 return DIV_ROUND_UP(uframes, 512UL << scale);
1529 }
1530
usb4_usb3_port_read_allocated_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)1531 static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port,
1532 int *upstream_bw,
1533 int *downstream_bw)
1534 {
1535 u32 val, bw, scale;
1536 int ret;
1537
1538 ret = tb_port_read(port, &val, TB_CFG_PORT,
1539 port->cap_adap + ADP_USB3_CS_2, 1);
1540 if (ret)
1541 return ret;
1542
1543 ret = tb_port_read(port, &scale, TB_CFG_PORT,
1544 port->cap_adap + ADP_USB3_CS_3, 1);
1545 if (ret)
1546 return ret;
1547
1548 scale &= ADP_USB3_CS_3_SCALE_MASK;
1549
1550 bw = val & ADP_USB3_CS_2_AUBW_MASK;
1551 *upstream_bw = usb3_bw_to_mbps(bw, scale);
1552
1553 bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT;
1554 *downstream_bw = usb3_bw_to_mbps(bw, scale);
1555
1556 return 0;
1557 }
1558
1559 /**
1560 * usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3
1561 * @port: USB3 adapter port
1562 * @upstream_bw: Allocated upstream bandwidth is stored here
1563 * @downstream_bw: Allocated downstream bandwidth is stored here
1564 *
1565 * Stores currently allocated USB3 bandwidth into @upstream_bw and
1566 * @downstream_bw in Mb/s. Returns %0 in case of success and negative
1567 * errno in failure.
1568 */
usb4_usb3_port_allocated_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)1569 int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw,
1570 int *downstream_bw)
1571 {
1572 int ret;
1573
1574 ret = usb4_usb3_port_set_cm_request(port);
1575 if (ret)
1576 return ret;
1577
1578 ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw,
1579 downstream_bw);
1580 usb4_usb3_port_clear_cm_request(port);
1581
1582 return ret;
1583 }
1584
usb4_usb3_port_read_consumed_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)1585 static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port,
1586 int *upstream_bw,
1587 int *downstream_bw)
1588 {
1589 u32 val, bw, scale;
1590 int ret;
1591
1592 ret = tb_port_read(port, &val, TB_CFG_PORT,
1593 port->cap_adap + ADP_USB3_CS_1, 1);
1594 if (ret)
1595 return ret;
1596
1597 ret = tb_port_read(port, &scale, TB_CFG_PORT,
1598 port->cap_adap + ADP_USB3_CS_3, 1);
1599 if (ret)
1600 return ret;
1601
1602 scale &= ADP_USB3_CS_3_SCALE_MASK;
1603
1604 bw = val & ADP_USB3_CS_1_CUBW_MASK;
1605 *upstream_bw = usb3_bw_to_mbps(bw, scale);
1606
1607 bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT;
1608 *downstream_bw = usb3_bw_to_mbps(bw, scale);
1609
1610 return 0;
1611 }
1612
usb4_usb3_port_write_allocated_bandwidth(struct tb_port * port,int upstream_bw,int downstream_bw)1613 static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port,
1614 int upstream_bw,
1615 int downstream_bw)
1616 {
1617 u32 val, ubw, dbw, scale;
1618 int ret;
1619
1620 /* Read the used scale, hardware default is 0 */
1621 ret = tb_port_read(port, &scale, TB_CFG_PORT,
1622 port->cap_adap + ADP_USB3_CS_3, 1);
1623 if (ret)
1624 return ret;
1625
1626 scale &= ADP_USB3_CS_3_SCALE_MASK;
1627 ubw = mbps_to_usb3_bw(upstream_bw, scale);
1628 dbw = mbps_to_usb3_bw(downstream_bw, scale);
1629
1630 ret = tb_port_read(port, &val, TB_CFG_PORT,
1631 port->cap_adap + ADP_USB3_CS_2, 1);
1632 if (ret)
1633 return ret;
1634
1635 val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK);
1636 val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT;
1637 val |= ubw;
1638
1639 return tb_port_write(port, &val, TB_CFG_PORT,
1640 port->cap_adap + ADP_USB3_CS_2, 1);
1641 }
1642
1643 /**
1644 * usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3
1645 * @port: USB3 adapter port
1646 * @upstream_bw: New upstream bandwidth
1647 * @downstream_bw: New downstream bandwidth
1648 *
1649 * This can be used to set how much bandwidth is allocated for the USB3
1650 * tunneled isochronous traffic. @upstream_bw and @downstream_bw are the
1651 * new values programmed to the USB3 adapter allocation registers. If
1652 * the values are lower than what is currently consumed the allocation
1653 * is set to what is currently consumed instead (consumed bandwidth
1654 * cannot be taken away by CM). The actual new values are returned in
1655 * @upstream_bw and @downstream_bw.
1656 *
1657 * Returns %0 in case of success and negative errno if there was a
1658 * failure.
1659 */
usb4_usb3_port_allocate_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)1660 int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw,
1661 int *downstream_bw)
1662 {
1663 int ret, consumed_up, consumed_down, allocate_up, allocate_down;
1664
1665 ret = usb4_usb3_port_set_cm_request(port);
1666 if (ret)
1667 return ret;
1668
1669 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
1670 &consumed_down);
1671 if (ret)
1672 goto err_request;
1673
1674 /* Don't allow it go lower than what is consumed */
1675 allocate_up = max(*upstream_bw, consumed_up);
1676 allocate_down = max(*downstream_bw, consumed_down);
1677
1678 ret = usb4_usb3_port_write_allocated_bandwidth(port, allocate_up,
1679 allocate_down);
1680 if (ret)
1681 goto err_request;
1682
1683 *upstream_bw = allocate_up;
1684 *downstream_bw = allocate_down;
1685
1686 err_request:
1687 usb4_usb3_port_clear_cm_request(port);
1688 return ret;
1689 }
1690
1691 /**
1692 * usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth
1693 * @port: USB3 adapter port
1694 * @upstream_bw: New allocated upstream bandwidth
1695 * @downstream_bw: New allocated downstream bandwidth
1696 *
1697 * Releases USB3 allocated bandwidth down to what is actually consumed.
1698 * The new bandwidth is returned in @upstream_bw and @downstream_bw.
1699 *
1700 * Returns 0% in success and negative errno in case of failure.
1701 */
usb4_usb3_port_release_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)1702 int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw,
1703 int *downstream_bw)
1704 {
1705 int ret, consumed_up, consumed_down;
1706
1707 ret = usb4_usb3_port_set_cm_request(port);
1708 if (ret)
1709 return ret;
1710
1711 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
1712 &consumed_down);
1713 if (ret)
1714 goto err_request;
1715
1716 /*
1717 * Always keep 1000 Mb/s to make sure xHCI has at least some
1718 * bandwidth available for isochronous traffic.
1719 */
1720 if (consumed_up < 1000)
1721 consumed_up = 1000;
1722 if (consumed_down < 1000)
1723 consumed_down = 1000;
1724
1725 ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up,
1726 consumed_down);
1727 if (ret)
1728 goto err_request;
1729
1730 *upstream_bw = consumed_up;
1731 *downstream_bw = consumed_down;
1732
1733 err_request:
1734 usb4_usb3_port_clear_cm_request(port);
1735 return ret;
1736 }
1737
