1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/opp.h" 32 #include "inc/hw/link_encoder.h" 33 #include "core_status.h" 34 35 struct pipe_ctx; 36 struct dc_state; 37 struct dc_stream_status; 38 struct dc_writeback_info; 39 struct dchub_init_data; 40 struct dc_static_screen_params; 41 struct resource_pool; 42 struct dc_phy_addr_space_config; 43 struct dc_virtual_addr_space_config; 44 struct dpp; 45 struct dce_hwseq; 46 struct link_resource; 47 struct dc_dmub_cmd; 48 49 struct subvp_pipe_control_lock_fast_params { 50 struct dc *dc; 51 bool lock; 52 struct pipe_ctx *pipe_ctx; 53 }; 54 55 struct pipe_control_lock_params { 56 struct dc *dc; 57 struct pipe_ctx *pipe_ctx; 58 bool lock; 59 }; 60 61 struct set_flip_control_gsl_params { 62 struct pipe_ctx *pipe_ctx; 63 bool flip_immediate; 64 }; 65 66 struct program_triplebuffer_params { 67 const struct dc *dc; 68 struct pipe_ctx *pipe_ctx; 69 bool enableTripleBuffer; 70 }; 71 72 struct update_plane_addr_params { 73 struct dc *dc; 74 struct pipe_ctx *pipe_ctx; 75 }; 76 77 struct set_input_transfer_func_params { 78 struct dc *dc; 79 struct pipe_ctx *pipe_ctx; 80 struct dc_plane_state *plane_state; 81 }; 82 83 struct program_gamut_remap_params { 84 struct pipe_ctx *pipe_ctx; 85 }; 86 87 struct program_manual_trigger_params { 88 struct pipe_ctx *pipe_ctx; 89 }; 90 91 struct send_dmcub_cmd_params { 92 struct dc_context *ctx; 93 union dmub_rb_cmd *cmd; 94 enum dm_dmub_wait_type wait_type; 95 }; 96 97 struct setup_dpp_params { 98 struct pipe_ctx *pipe_ctx; 99 }; 100 101 struct program_bias_and_scale_params { 102 struct pipe_ctx *pipe_ctx; 103 }; 104 105 struct set_output_transfer_func_params { 106 struct dc *dc; 107 struct pipe_ctx *pipe_ctx; 108 const struct dc_stream_state *stream; 109 }; 110 111 struct update_visual_confirm_params { 112 struct dc *dc; 113 struct pipe_ctx *pipe_ctx; 114 int mpcc_id; 115 }; 116 117 struct power_on_mpc_mem_pwr_params { 118 struct mpc *mpc; 119 int mpcc_id; 120 bool power_on; 121 }; 122 123 struct set_output_csc_params { 124 struct mpc *mpc; 125 int opp_id; 126 const uint16_t *regval; 127 enum mpc_output_csc_mode ocsc_mode; 128 }; 129 130 struct set_ocsc_default_params { 131 struct mpc *mpc; 132 int opp_id; 133 enum dc_color_space color_space; 134 enum mpc_output_csc_mode ocsc_mode; 135 }; 136 137 union block_sequence_params { 138 struct update_plane_addr_params update_plane_addr_params; 139 struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; 140 struct pipe_control_lock_params pipe_control_lock_params; 141 struct set_flip_control_gsl_params set_flip_control_gsl_params; 142 struct program_triplebuffer_params program_triplebuffer_params; 143 struct set_input_transfer_func_params set_input_transfer_func_params; 144 struct program_gamut_remap_params program_gamut_remap_params; 145 struct program_manual_trigger_params program_manual_trigger_params; 146 struct send_dmcub_cmd_params send_dmcub_cmd_params; 147 struct setup_dpp_params setup_dpp_params; 148 struct program_bias_and_scale_params program_bias_and_scale_params; 149 struct set_output_transfer_func_params set_output_transfer_func_params; 150 struct update_visual_confirm_params update_visual_confirm_params; 151 struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params; 152 struct set_output_csc_params set_output_csc_params; 153 struct set_ocsc_default_params set_ocsc_default_params; 154 }; 155 156 enum block_sequence_func { 157 DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST = 0, 158 OPTC_PIPE_CONTROL_LOCK, 159 HUBP_SET_FLIP_CONTROL_GSL, 160 HUBP_PROGRAM_TRIPLEBUFFER, 161 HUBP_UPDATE_PLANE_ADDR, 162 DPP_SET_INPUT_TRANSFER_FUNC, 163 DPP_PROGRAM_GAMUT_REMAP, 164 OPTC_PROGRAM_MANUAL_TRIGGER, 165 DMUB_SEND_DMCUB_CMD, 166 DPP_SETUP_DPP, 167 DPP_PROGRAM_BIAS_AND_SCALE, 168 DPP_SET_OUTPUT_TRANSFER_FUNC, 169 MPC_UPDATE_VISUAL_CONFIRM, 170 MPC_POWER_ON_MPC_MEM_PWR, 171 MPC_SET_OUTPUT_CSC, 172 MPC_SET_OCSC_DEFAULT, 173 }; 174 175 struct block_sequence { 176 union block_sequence_params params; 177 enum block_sequence_func func; 178 }; 179 180 struct hw_sequencer_funcs { 181 void (*hardware_release)(struct dc *dc); 182 /* Embedded Display Related */ 183 void (*edp_power_control)(struct dc_link *link, bool enable); 184 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 185 void (*edp_wait_for_T12)(struct dc_link *link); 186 187 /* Pipe Programming Related */ 188 void (*init_hw)(struct dc *dc); 189 void (*power_down_on_boot)(struct dc *dc); 190 void (*enable_accelerated_mode)(struct dc *dc, 191 struct dc_state *context); 192 enum dc_status (*apply_ctx_to_hw)(struct dc *dc, 193 struct dc_state *context); 194 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); 195 void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank); 196 void (*apply_ctx_for_surface)(struct dc *dc, 197 const struct dc_stream_state *stream, 198 int num_planes, struct dc_state *context); 199 void (*program_front_end_for_ctx)(struct dc *dc, 200 struct dc_state *context); 201 void (*wait_for_pending_cleared)(struct dc *dc, 202 struct dc_state *context); 203 void (*post_unlock_program_front_end)(struct dc *dc, 204 struct dc_state *context); 205 void (*update_plane_addr)(const struct dc *dc, 206 struct pipe_ctx *pipe_ctx); 207 void (*update_dchub)(struct dce_hwseq *hws, 208 struct dchub_init_data *dh_data); 209 void (*wait_for_mpcc_disconnect)(struct dc *dc, 210 struct resource_pool *res_pool, 211 struct pipe_ctx *pipe_ctx); 212 void (*edp_backlight_control)( 213 struct dc_link *link, 214 bool enable); 215 void (*program_triplebuffer)(const struct dc *dc, 216 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 217 void (*update_pending_status)(struct pipe_ctx *pipe_ctx); 218 void (*power_down)(struct dc *dc); 219 void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable); 220 221 /* Pipe Lock Related */ 222 void (*pipe_control_lock)(struct dc *dc, 223 struct pipe_ctx *pipe, bool lock); 224 void (*interdependent_update_lock)(struct dc *dc, 225 struct dc_state *context, bool lock); 226 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, 227 bool flip_immediate); 228 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock); 229 230 /* Timing Related */ 231 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 232 struct crtc_position *position); 233 int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); 234 void (*calc_vupdate_position)( 235 struct dc *dc, 236 struct pipe_ctx *pipe_ctx, 237 uint32_t *start_line, 238 uint32_t *end_line); 239 void (*enable_per_frame_crtc_position_reset)(struct dc *dc, 240 int group_size, struct pipe_ctx *grouped_pipes[]); 241 void (*enable_timing_synchronization)(struct dc *dc, 242 int group_index, int group_size, 243 struct pipe_ctx *grouped_pipes[]); 244 void (*enable_vblanks_synchronization)(struct dc *dc, 245 int group_index, int group_size, 246 struct pipe_ctx *grouped_pipes[]); 247 void (*setup_periodic_interrupt)(struct dc *dc, 248 struct pipe_ctx *pipe_ctx); 249 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 250 struct dc_crtc_timing_adjust adjust); 251 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 252 int num_pipes, 253 const struct dc_static_screen_params *events); 254 #ifndef TRIM_FSFT 255 bool (*optimize_timing_for_fsft)(struct dc *dc, 256 struct dc_crtc_timing *timing, 257 unsigned int max_input_rate_in_khz); 258 #endif 259 260 /* Stream Related */ 261 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 262 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 263 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 264 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 265 struct dc_link_settings *link_settings); 266 267 /* Bandwidth Related */ 268 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); 269 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); 270 void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); 271 272 /* Infopacket Related */ 273 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 274 void (*send_immediate_sdp_message)( 275 struct pipe_ctx *pipe_ctx, 276 const uint8_t *custom_sdp_message, 277 unsigned int sdp_message_size); 278 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 279 void (*set_dmdata_attributes)(struct pipe_ctx *pipe); 280 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); 281 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 282 283 /* Cursor Related */ 284 void (*set_cursor_position)(struct pipe_ctx *pipe); 285 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 286 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 287 288 /* Colour Related */ 289 void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); 290 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, 291 enum dc_color_space colorspace, 292 uint16_t *matrix, int opp_id); 293 294 /* VM Related */ 295 int (*init_sys_ctx)(struct dce_hwseq *hws, 296 struct dc *dc, 297 struct dc_phy_addr_space_config *pa_config); 298 void (*init_vm_ctx)(struct dce_hwseq *hws, 299 struct dc *dc, 300 struct dc_virtual_addr_space_config *va_config, 301 int vmid); 302 303 /* Writeback Related */ 304 void (*update_writeback)(struct dc *dc, 305 struct dc_writeback_info *wb_info, 306 struct dc_state *context); 307 void (*enable_writeback)(struct dc *dc, 308 struct dc_writeback_info *wb_info, 309 struct dc_state *context); 310 void (*disable_writeback)(struct dc *dc, 311 unsigned int dwb_pipe_inst); 312 313 bool (*mmhubbub_warmup)(struct dc *dc, 314 unsigned int num_dwb, 315 struct dc_writeback_info *wb_info); 316 317 /* Clock Related */ 318 enum dc_status (*set_clock)(struct dc *dc, 319 enum dc_clock_type clock_type, 320 uint32_t clk_khz, uint32_t stepping); 321 void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, 322 struct dc_clock_config *clock_cfg); 323 void (*optimize_pwr_state)(const struct dc *dc, 324 struct dc_state *context); 325 void (*exit_optimized_pwr_state)(const struct dc *dc, 326 struct dc_state *context); 327 328 /* Audio Related */ 329 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 330 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); 331 332 /* Stereo 3D Related */ 333 void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); 334 335 /* HW State Logging Related */ 336 void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); 337 void (*get_hw_state)(struct dc *dc, char *pBuf, 338 unsigned int bufSize, unsigned int mask); 339 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 340 341 bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, 342 uint32_t backlight_pwm_u16_16, 343 uint32_t frame_ramp); 344 345 void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); 346 347 void (*set_pipe)(struct pipe_ctx *pipe_ctx); 348 349 void (*enable_dp_link_output)(struct dc_link *link, 350 const struct link_resource *link_res, 351 enum signal_type signal, 352 enum clock_source_id clock_source, 353 const struct dc_link_settings *link_settings); 354 void (*enable_tmds_link_output)(struct dc_link *link, 355 const struct link_resource *link_res, 356 enum signal_type signal, 357 enum clock_source_id clock_source, 358 enum dc_color_depth color_depth, 359 uint32_t pixel_clock); 360 void (*enable_lvds_link_output)(struct dc_link *link, 361 const struct link_resource *link_res, 362 enum clock_source_id clock_source, 363 uint32_t pixel_clock); 364 void (*disable_link_output)(struct dc_link *link, 365 const struct link_resource *link_res, 366 enum signal_type signal); 367 368 void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); 369 370 /* Idle Optimization Related */ 371 bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable); 372 373 bool (*does_plane_fit_in_mall)(struct dc *dc, struct dc_plane_state *plane, 374 struct dc_cursor_attributes *cursor_attr); 375 376 bool (*is_abm_supported)(struct dc *dc, 377 struct dc_state *context, struct dc_stream_state *stream); 378 379 void (*set_disp_pattern_generator)(const struct dc *dc, 380 struct pipe_ctx *pipe_ctx, 381 enum controller_dp_test_pattern test_pattern, 382 enum controller_dp_color_space color_space, 383 enum dc_color_depth color_depth, 384 const struct tg_color *solid_color, 385 int width, int height, int offset); 386 387 void (*subvp_pipe_control_lock_fast)(union block_sequence_params *params); 388 void (*z10_restore)(const struct dc *dc); 389 void (*z10_save_init)(struct dc *dc); 390 391 void (*update_visual_confirm_color)(struct dc *dc, 392 struct pipe_ctx *pipe_ctx, 393 int mpcc_id); 394 395 void (*update_phantom_vp_position)(struct dc *dc, 396 struct dc_state *context, 397 struct pipe_ctx *phantom_pipe); 398 void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe); 399 400 void (*commit_subvp_config)(struct dc *dc, struct dc_state *context); 401 void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context); 402 void (*subvp_pipe_control_lock)(struct dc *dc, 403 struct dc_state *context, 404 bool lock, 405 bool should_lock_all_pipes, 406 struct pipe_ctx *top_pipe_to_program, 407 bool subvp_prev_use); 408 409 }; 410 411 void color_space_to_black_color( 412 const struct dc *dc, 413 enum dc_color_space colorspace, 414 struct tg_color *black_color); 415 416 bool hwss_wait_for_blank_complete( 417 struct timing_generator *tg); 418 419 const uint16_t *find_color_matrix( 420 enum dc_color_space color_space, 421 uint32_t *array_size); 422 423 void get_surface_visual_confirm_color( 424 const struct pipe_ctx *pipe_ctx, 425 struct tg_color *color); 426 427 void get_subvp_visual_confirm_color( 428 struct dc *dc, 429 struct dc_state *context, 430 struct pipe_ctx *pipe_ctx, 431 struct tg_color *color); 432 433 void get_hdr_visual_confirm_color( 434 struct pipe_ctx *pipe_ctx, 435 struct tg_color *color); 436 void get_mpctree_visual_confirm_color( 437 struct pipe_ctx *pipe_ctx, 438 struct tg_color *color); 439 void get_surface_tile_visual_confirm_color( 440 struct pipe_ctx *pipe_ctx, 441 struct tg_color *color); 442 443 void get_mclk_switch_visual_confirm_color( 444 struct dc *dc, 445 struct dc_state *context, 446 struct pipe_ctx *pipe_ctx, 447 struct tg_color *color); 448 449 void hwss_execute_sequence(struct dc *dc, 450 struct block_sequence block_sequence[], 451 int num_steps); 452 453 void hwss_build_fast_sequence(struct dc *dc, 454 struct dc_dmub_cmd *dc_dmub_cmd, 455 unsigned int dmub_cmd_count, 456 struct block_sequence block_sequence[], 457 int *num_steps, 458 struct pipe_ctx *pipe_ctx); 459 460 void hwss_send_dmcub_cmd(union block_sequence_params *params); 461 462 void hwss_program_manual_trigger(union block_sequence_params *params); 463 464 void hwss_setup_dpp(union block_sequence_params *params); 465 466 void hwss_program_bias_and_scale(union block_sequence_params *params); 467 468 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params); 469 470 void hwss_set_output_csc(union block_sequence_params *params); 471 472 void hwss_set_ocsc_default(union block_sequence_params *params); 473 474 #endif /* __DC_HW_SEQUENCER_H__ */ 475
