1 /*******************************************************************
2  * This file is part of the Emulex Linux Device Driver for         *
3  * Fibre Channel Host Bus Adapters.                                *
4  * Copyright (C) 2017-2018 Broadcom. All Rights Reserved. The term *
5  * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.     *
6  * Copyright (C) 2004-2016 Emulex.  All rights reserved.           *
7  * EMULEX and SLI are trademarks of Emulex.                        *
8  * www.broadcom.com                                                *
9  *                                                                 *
10  * This program is free software; you can redistribute it and/or   *
11  * modify it under the terms of version 2 of the GNU General       *
12  * Public License as published by the Free Software Foundation.    *
13  * This program is distributed in the hope that it will be useful. *
14  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
15  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
16  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
17  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
19  * more details, a copy of which can be found in the file COPYING  *
20  * included with this package.                                     *
21  *******************************************************************/
22 
23 #define FDMI_DID        0xfffffaU
24 #define NameServer_DID  0xfffffcU
25 #define SCR_DID         0xfffffdU
26 #define Fabric_DID      0xfffffeU
27 #define Bcast_DID       0xffffffU
28 #define Mask_DID        0xffffffU
29 #define CT_DID_MASK     0xffff00U
30 #define Fabric_DID_MASK 0xfff000U
31 #define WELL_KNOWN_DID_MASK 0xfffff0U
32 
33 #define PT2PT_LocalID	1
34 #define PT2PT_RemoteID	2
35 
36 #define FF_DEF_EDTOV          2000	/* Default E_D_TOV (2000ms) */
37 #define FF_DEF_ALTOV            15	/* Default AL_TIME (15ms) */
38 #define FF_DEF_RATOV            10	/* Default RA_TOV (10s) */
39 #define FF_DEF_ARBTOV         1900	/* Default ARB_TOV (1900ms) */
40 
41 #define LPFC_BUF_RING0        64	/* Number of buffers to post to RING
42 					   0 */
43 
44 #define FCELSSIZE             1024	/* maximum ELS transfer size */
45 
46 #define LPFC_FCP_RING            0	/* ring 0 for FCP initiator commands */
47 #define LPFC_EXTRA_RING          1	/* ring 1 for other protocols */
48 #define LPFC_ELS_RING            2	/* ring 2 for ELS commands */
49 
50 #define SLI2_IOCB_CMD_R0_ENTRIES    172	/* SLI-2 FCP command ring entries */
51 #define SLI2_IOCB_RSP_R0_ENTRIES    134	/* SLI-2 FCP response ring entries */
52 #define SLI2_IOCB_CMD_R1_ENTRIES      4	/* SLI-2 extra command ring entries */
53 #define SLI2_IOCB_RSP_R1_ENTRIES      4	/* SLI-2 extra response ring entries */
54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36	/* SLI-2 extra FCP cmd ring entries */
55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52	/* SLI-2 extra FCP rsp ring entries */
56 #define SLI2_IOCB_CMD_R2_ENTRIES     20	/* SLI-2 ELS command ring entries */
57 #define SLI2_IOCB_RSP_R2_ENTRIES     20	/* SLI-2 ELS response ring entries */
58 #define SLI2_IOCB_CMD_R3_ENTRIES      0
59 #define SLI2_IOCB_RSP_R3_ENTRIES      0
60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62 
63 #define SLI2_IOCB_CMD_SIZE	32
64 #define SLI2_IOCB_RSP_SIZE	32
65 #define SLI3_IOCB_CMD_SIZE	128
66 #define SLI3_IOCB_RSP_SIZE	64
67 
68 #define LPFC_UNREG_ALL_RPIS_VPORT	0xffff
69 #define LPFC_UNREG_ALL_DFLT_RPIS	0xffffffff
70 
71 /* vendor ID used in SCSI netlink calls */
72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
73 
74 #define FW_REV_STR_SIZE	32
75 /* Common Transport structures and definitions */
76 
77 union CtRevisionId {
78 	/* Structure is in Big Endian format */
79 	struct {
80 		uint32_t Revision:8;
81 		uint32_t InId:24;
82 	} bits;
83 	uint32_t word;
84 };
85 
86 union CtCommandResponse {
87 	/* Structure is in Big Endian format */
88 	struct {
89 		uint32_t CmdRsp:16;
90 		uint32_t Size:16;
91 	} bits;
92 	uint32_t word;
93 };
94 
95 /* FC4 Feature bits for RFF_ID */
96 #define FC4_FEATURE_TARGET	0x1
97 #define FC4_FEATURE_INIT	0x2
98 #define FC4_FEATURE_NVME_DISC	0x4
99 
100 struct lpfc_sli_ct_request {
101 	/* Structure is in Big Endian format */
102 	union CtRevisionId RevisionId;
103 	uint8_t FsType;
104 	uint8_t FsSubType;
105 	uint8_t Options;
106 	uint8_t Rsrvd1;
107 	union CtCommandResponse CommandResponse;
108 	uint8_t Rsrvd2;
109 	uint8_t ReasonCode;
110 	uint8_t Explanation;
111 	uint8_t VendorUnique;
112 #define LPFC_CT_PREAMBLE	20	/* Size of CTReq + 4 up to here */
113 
114 	union {
115 		uint32_t PortID;
116 		struct gid {
117 			uint8_t PortType;	/* for GID_PT requests */
118 			uint8_t DomainScope;
119 			uint8_t AreaScope;
120 			uint8_t Fc4Type;	/* for GID_FT requests */
121 		} gid;
122 		struct gid_ff {
123 			uint8_t Flags;
124 			uint8_t DomainScope;
125 			uint8_t AreaScope;
126 			uint8_t rsvd1;
127 			uint8_t rsvd2;
128 			uint8_t rsvd3;
129 			uint8_t Fc4FBits;
130 			uint8_t Fc4Type;
131 		} gid_ff;
132 		struct rft {
133 			uint32_t PortId;	/* For RFT_ID requests */
134 
135 #ifdef __BIG_ENDIAN_BITFIELD
136 			uint32_t rsvd0:16;
137 			uint32_t rsvd1:7;
138 			uint32_t fcpReg:1;	/* Type 8 */
139 			uint32_t rsvd2:2;
140 			uint32_t ipReg:1;	/* Type 5 */
141 			uint32_t rsvd3:5;
142 #else	/*  __LITTLE_ENDIAN_BITFIELD */
143 			uint32_t rsvd0:16;
144 			uint32_t fcpReg:1;	/* Type 8 */
145 			uint32_t rsvd1:7;
146 			uint32_t rsvd3:5;
147 			uint32_t ipReg:1;	/* Type 5 */
148 			uint32_t rsvd2:2;
149 #endif
150 
151 			uint32_t rsvd[7];
152 		} rft;
153 		struct rnn {
154 			uint32_t PortId;	/* For RNN_ID requests */
155 			uint8_t wwnn[8];
156 		} rnn;
157 		struct rsnn {	/* For RSNN_ID requests */
158 			uint8_t wwnn[8];
159 			uint8_t len;
160 			uint8_t symbname[255];
161 		} rsnn;
162 		struct da_id { /* For DA_ID requests */
163 			uint32_t port_id;
164 		} da_id;
165 		struct rspn {	/* For RSPN_ID requests */
166 			uint32_t PortId;
167 			uint8_t len;
168 			uint8_t symbname[255];
169 		} rspn;
170 		struct gff {
171 			uint32_t PortId;
172 		} gff;
173 		struct gff_acc {
174 			uint8_t fbits[128];
175 		} gff_acc;
176 		struct gft {
177 			uint32_t PortId;
178 		} gft;
179 		struct gft_acc {
180 			uint32_t fc4_types[8];
181 		} gft_acc;
182 #define FCP_TYPE_FEATURE_OFFSET 7
183 		struct rff {
184 			uint32_t PortId;
185 			uint8_t reserved[2];
186 			uint8_t fbits;
187 			uint8_t type_code;     /* type=8 for FCP */
188 		} rff;
189 	} un;
190 };
191 
192 #define LPFC_MAX_CT_SIZE	(60 * 4096)
193 
194 #define  SLI_CT_REVISION        1
195 #define  GID_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
196 			   sizeof(struct gid))
197 #define  GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
198 			   sizeof(struct gid_ff))
199 #define  GFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
200 			   sizeof(struct gff))
201 #define  GFT_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
202 			   sizeof(struct gft))
203 #define  RFT_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
204 			   sizeof(struct rft))
205 #define  RFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
206 			   sizeof(struct rff))
207 #define  RNN_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
208 			   sizeof(struct rnn))
209 #define  RSNN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
210 			   sizeof(struct rsnn))
211 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
212 			  sizeof(struct da_id))
213 #define  RSPN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
214 			   sizeof(struct rspn))
215 
216 /*
217  * FsType Definitions
218  */
219 
220 #define  SLI_CT_MANAGEMENT_SERVICE        0xFA
221 #define  SLI_CT_TIME_SERVICE              0xFB
222 #define  SLI_CT_DIRECTORY_SERVICE         0xFC
223 #define  SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
224 
225 /*
226  * Directory Service Subtypes
227  */
228 
229 #define  SLI_CT_DIRECTORY_NAME_SERVER     0x02
230 
231 /*
232  * Response Codes
233  */
234 
235 #define  SLI_CT_RESPONSE_FS_RJT           0x8001
236 #define  SLI_CT_RESPONSE_FS_ACC           0x8002
237 
238 /*
239  * Reason Codes
240  */
241 
242 #define  SLI_CT_NO_ADDITIONAL_EXPL	  0x0
243 #define  SLI_CT_INVALID_COMMAND           0x01
244 #define  SLI_CT_INVALID_VERSION           0x02
245 #define  SLI_CT_LOGICAL_ERROR             0x03
246 #define  SLI_CT_INVALID_IU_SIZE           0x04
247 #define  SLI_CT_LOGICAL_BUSY              0x05
248 #define  SLI_CT_PROTOCOL_ERROR            0x07
249 #define  SLI_CT_UNABLE_TO_PERFORM_REQ     0x09
250 #define  SLI_CT_REQ_NOT_SUPPORTED         0x0b
251 #define  SLI_CT_HBA_INFO_NOT_REGISTERED	  0x10
252 #define  SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE  0x11
253 #define  SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN      0x12
254 #define  SLI_CT_HBA_ATTR_NOT_PRESENT	  0x13
255 #define  SLI_CT_PORT_INFO_NOT_REGISTERED  0x20
256 #define  SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
257 #define  SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN     0x22
258 #define  SLI_CT_VENDOR_UNIQUE             0xff
259 
260 /*
261  * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
262  */
263 
264 #define  SLI_CT_NO_PORT_ID                0x01
265 #define  SLI_CT_NO_PORT_NAME              0x02
266 #define  SLI_CT_NO_NODE_NAME              0x03
267 #define  SLI_CT_NO_CLASS_OF_SERVICE       0x04
268 #define  SLI_CT_NO_IP_ADDRESS             0x05
269 #define  SLI_CT_NO_IPA                    0x06
270 #define  SLI_CT_NO_FC4_TYPES              0x07
271 #define  SLI_CT_NO_SYMBOLIC_PORT_NAME     0x08
272 #define  SLI_CT_NO_SYMBOLIC_NODE_NAME     0x09
273 #define  SLI_CT_NO_PORT_TYPE              0x0A
274 #define  SLI_CT_ACCESS_DENIED             0x10
275 #define  SLI_CT_INVALID_PORT_ID           0x11
276 #define  SLI_CT_DATABASE_EMPTY            0x12
277 
278 /*
279  * Name Server Command Codes
280  */
281 
282 #define  SLI_CTNS_GA_NXT      0x0100
283 #define  SLI_CTNS_GPN_ID      0x0112
284 #define  SLI_CTNS_GNN_ID      0x0113
285 #define  SLI_CTNS_GCS_ID      0x0114
286 #define  SLI_CTNS_GFT_ID      0x0117
287 #define  SLI_CTNS_GSPN_ID     0x0118
288 #define  SLI_CTNS_GPT_ID      0x011A
289 #define  SLI_CTNS_GFF_ID      0x011F
290 #define  SLI_CTNS_GID_PN      0x0121
291 #define  SLI_CTNS_GID_NN      0x0131
292 #define  SLI_CTNS_GIP_NN      0x0135
293 #define  SLI_CTNS_GIPA_NN     0x0136
294 #define  SLI_CTNS_GSNN_NN     0x0139
295 #define  SLI_CTNS_GNN_IP      0x0153
296 #define  SLI_CTNS_GIPA_IP     0x0156
297 #define  SLI_CTNS_GID_FT      0x0171
298 #define  SLI_CTNS_GID_FF      0x01F1
299 #define  SLI_CTNS_GID_PT      0x01A1
300 #define  SLI_CTNS_RPN_ID      0x0212
301 #define  SLI_CTNS_RNN_ID      0x0213
302 #define  SLI_CTNS_RCS_ID      0x0214
303 #define  SLI_CTNS_RFT_ID      0x0217
304 #define  SLI_CTNS_RSPN_ID     0x0218
305 #define  SLI_CTNS_RPT_ID      0x021A
306 #define  SLI_CTNS_RFF_ID      0x021F
307 #define  SLI_CTNS_RIP_NN      0x0235
308 #define  SLI_CTNS_RIPA_NN     0x0236
309 #define  SLI_CTNS_RSNN_NN     0x0239
310 #define  SLI_CTNS_DA_ID       0x0300
311 
312 /*
313  * Port Types
314  */
315 
316 #define SLI_CTPT_N_PORT		0x01
317 #define SLI_CTPT_NL_PORT	0x02
318 #define SLI_CTPT_FNL_PORT	0x03
319 #define SLI_CTPT_IP		0x04
320 #define SLI_CTPT_FCP		0x08
321 #define SLI_CTPT_NVME		0x28
322 #define SLI_CTPT_NX_PORT	0x7F
323 #define SLI_CTPT_F_PORT		0x81
324 #define SLI_CTPT_FL_PORT	0x82
325 #define SLI_CTPT_E_PORT		0x84
326 
327 #define SLI_CT_LAST_ENTRY     0x80000000
328 
329 /* Fibre Channel Service Parameter definitions */
330 
331 #define FC_PH_4_0   6		/* FC-PH version 4.0 */
332 #define FC_PH_4_1   7		/* FC-PH version 4.1 */
333 #define FC_PH_4_2   8		/* FC-PH version 4.2 */
334 #define FC_PH_4_3   9		/* FC-PH version 4.3 */
335 
336 #define FC_PH_LOW   8		/* Lowest supported FC-PH version */
337 #define FC_PH_HIGH  9		/* Highest supported FC-PH version */
338 #define FC_PH3   0x20		/* FC-PH-3 version */
339 
340 #define FF_FRAME_SIZE     2048
341 
342 struct lpfc_name {
343 	union {
344 		struct {
345 #ifdef __BIG_ENDIAN_BITFIELD
346 			uint8_t nameType:4;	/* FC Word 0, bit 28:31 */
347 			uint8_t IEEEextMsn:4;	/* FC Word 0, bit 24:27, bit
348 						   8:11 of IEEE ext */
349 #else	/*  __LITTLE_ENDIAN_BITFIELD */
350 			uint8_t IEEEextMsn:4;	/* FC Word 0, bit 24:27, bit
351 						   8:11 of IEEE ext */
352 			uint8_t nameType:4;	/* FC Word 0, bit 28:31 */
353 #endif
354 
355 #define NAME_IEEE           0x1	/* IEEE name - nameType */
356 #define NAME_IEEE_EXT       0x2	/* IEEE extended name */
357 #define NAME_FC_TYPE        0x3	/* FC native name type */
358 #define NAME_IP_TYPE        0x4	/* IP address */
359 #define NAME_CCITT_TYPE     0xC
360 #define NAME_CCITT_GR_TYPE  0xE
361 			uint8_t IEEEextLsb;	/* FC Word 0, bit 16:23, IEEE
362 						   extended Lsb */
363 			uint8_t IEEE[6];	/* FC IEEE address */
364 		} s;
365 		uint8_t wwn[8];
366 		uint64_t name;
367 	} u;
368 };
369 
370 struct csp {
371 	uint8_t fcphHigh;	/* FC Word 0, byte 0 */
372 	uint8_t fcphLow;
373 	uint8_t bbCreditMsb;
374 	uint8_t bbCreditLsb;	/* FC Word 0, byte 3 */
375 
376 /*
377  * Word 1 Bit 31 in common service parameter is overloaded.
378  * Word 1 Bit 31 in FLOGI request is multiple NPort request
379  * Word 1 Bit 31 in FLOGI response is clean address bit
380  */
381 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
382 /*
383  * Word 1 Bit 30 in common service parameter is overloaded.
384  * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
385  * Word 1 Bit 30 in PLOGI request is random offset
386  */
387 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
388 /*
389  * Word 1 Bit 29 in common service parameter is overloaded.
390  * Word 1 Bit 29 in FLOGI response is multiple NPort assignment
391  * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level
392  */
393 #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */
394 #ifdef __BIG_ENDIAN_BITFIELD
395 	uint16_t request_multiple_Nport:1;	/* FC Word 1, bit 31 */
396 	uint16_t randomOffset:1;	/* FC Word 1, bit 30 */
397 	uint16_t response_multiple_NPort:1;	/* FC Word 1, bit 29 */
398 	uint16_t fPort:1;	/* FC Word 1, bit 28 */
399 	uint16_t altBbCredit:1;	/* FC Word 1, bit 27 */
400 	uint16_t edtovResolution:1;	/* FC Word 1, bit 26 */
401 	uint16_t multicast:1;	/* FC Word 1, bit 25 */
402 	uint16_t broadcast:1;	/* FC Word 1, bit 24 */
403 
404 	uint16_t huntgroup:1;	/* FC Word 1, bit 23 */
405 	uint16_t simplex:1;	/* FC Word 1, bit 22 */
406 	uint16_t word1Reserved1:3;	/* FC Word 1, bit 21:19 */
407 	uint16_t dhd:1;		/* FC Word 1, bit 18 */
408 	uint16_t contIncSeqCnt:1;	/* FC Word 1, bit 17 */
409 	uint16_t payloadlength:1;	/* FC Word 1, bit 16 */
410 #else	/*  __LITTLE_ENDIAN_BITFIELD */
411 	uint16_t broadcast:1;	/* FC Word 1, bit 24 */
412 	uint16_t multicast:1;	/* FC Word 1, bit 25 */
413 	uint16_t edtovResolution:1;	/* FC Word 1, bit 26 */
414 	uint16_t altBbCredit:1;	/* FC Word 1, bit 27 */
415 	uint16_t fPort:1;	/* FC Word 1, bit 28 */
416 	uint16_t response_multiple_NPort:1;	/* FC Word 1, bit 29 */
417 	uint16_t randomOffset:1;	/* FC Word 1, bit 30 */
418 	uint16_t request_multiple_Nport:1;	/* FC Word 1, bit 31 */
419 
420 	uint16_t payloadlength:1;	/* FC Word 1, bit 16 */
421 	uint16_t contIncSeqCnt:1;	/* FC Word 1, bit 17 */
422 	uint16_t dhd:1;		/* FC Word 1, bit 18 */
423 	uint16_t word1Reserved1:3;	/* FC Word 1, bit 21:19 */
424 	uint16_t simplex:1;	/* FC Word 1, bit 22 */
425 	uint16_t huntgroup:1;	/* FC Word 1, bit 23 */
426 #endif
427 
428 	uint8_t bbRcvSizeMsb;	/* Upper nibble is reserved */
429 	uint8_t bbRcvSizeLsb;	/* FC Word 1, byte 3 */
430 	union {
431 		struct {
432 			uint8_t word2Reserved1;	/* FC Word 2 byte 0 */
433 
434 			uint8_t totalConcurrSeq;	/* FC Word 2 byte 1 */
435 			uint8_t roByCategoryMsb;	/* FC Word 2 byte 2 */
436 
437 			uint8_t roByCategoryLsb;	/* FC Word 2 byte 3 */
438 		} nPort;
439 		uint32_t r_a_tov;	/* R_A_TOV must be in B.E. format */
440 	} w2;
441 
442 	uint32_t e_d_tov;	/* E_D_TOV must be in B.E. format */
443 };
444 
445 struct class_parms {
446 #ifdef __BIG_ENDIAN_BITFIELD
447 	uint8_t classValid:1;	/* FC Word 0, bit 31 */
448 	uint8_t intermix:1;	/* FC Word 0, bit 30 */
449 	uint8_t stackedXparent:1;	/* FC Word 0, bit 29 */
450 	uint8_t stackedLockDown:1;	/* FC Word 0, bit 28 */
451 	uint8_t seqDelivery:1;	/* FC Word 0, bit 27 */
452 	uint8_t word0Reserved1:3;	/* FC Word 0, bit 24:26 */
453 #else	/*  __LITTLE_ENDIAN_BITFIELD */
454 	uint8_t word0Reserved1:3;	/* FC Word 0, bit 24:26 */
455 	uint8_t seqDelivery:1;	/* FC Word 0, bit 27 */
456 	uint8_t stackedLockDown:1;	/* FC Word 0, bit 28 */
457 	uint8_t stackedXparent:1;	/* FC Word 0, bit 29 */
458 	uint8_t intermix:1;	/* FC Word 0, bit 30 */
459 	uint8_t classValid:1;	/* FC Word 0, bit 31 */
460 
461 #endif
462 
463 	uint8_t word0Reserved2;	/* FC Word 0, bit 16:23 */
464 
465 #ifdef __BIG_ENDIAN_BITFIELD
466 	uint8_t iCtlXidReAssgn:2;	/* FC Word 0, Bit 14:15 */
467 	uint8_t iCtlInitialPa:2;	/* FC Word 0, bit 12:13 */
468 	uint8_t iCtlAck0capable:1;	/* FC Word 0, bit 11 */
469 	uint8_t iCtlAckNcapable:1;	/* FC Word 0, bit 10 */
470 	uint8_t word0Reserved3:2;	/* FC Word 0, bit  8: 9 */
471 #else	/*  __LITTLE_ENDIAN_BITFIELD */
472 	uint8_t word0Reserved3:2;	/* FC Word 0, bit  8: 9 */
473 	uint8_t iCtlAckNcapable:1;	/* FC Word 0, bit 10 */
474 	uint8_t iCtlAck0capable:1;	/* FC Word 0, bit 11 */
475 	uint8_t iCtlInitialPa:2;	/* FC Word 0, bit 12:13 */
476 	uint8_t iCtlXidReAssgn:2;	/* FC Word 0, Bit 14:15 */
477 #endif
478 
479 	uint8_t word0Reserved4;	/* FC Word 0, bit  0: 7 */
480 
481 #ifdef __BIG_ENDIAN_BITFIELD
482 	uint8_t rCtlAck0capable:1;	/* FC Word 1, bit 31 */
483 	uint8_t rCtlAckNcapable:1;	/* FC Word 1, bit 30 */
484 	uint8_t rCtlXidInterlck:1;	/* FC Word 1, bit 29 */
485 	uint8_t rCtlErrorPolicy:2;	/* FC Word 1, bit 27:28 */
486 	uint8_t word1Reserved1:1;	/* FC Word 1, bit 26 */
487 	uint8_t rCtlCatPerSeq:2;	/* FC Word 1, bit 24:25 */
488 #else	/*  __LITTLE_ENDIAN_BITFIELD */
489 	uint8_t rCtlCatPerSeq:2;	/* FC Word 1, bit 24:25 */
490 	uint8_t word1Reserved1:1;	/* FC Word 1, bit 26 */
491 	uint8_t rCtlErrorPolicy:2;	/* FC Word 1, bit 27:28 */
492 	uint8_t rCtlXidInterlck:1;	/* FC Word 1, bit 29 */
493 	uint8_t rCtlAckNcapable:1;	/* FC Word 1, bit 30 */
494 	uint8_t rCtlAck0capable:1;	/* FC Word 1, bit 31 */
495 #endif
496 
497 	uint8_t word1Reserved2;	/* FC Word 1, bit 16:23 */
498 	uint8_t rcvDataSizeMsb;	/* FC Word 1, bit  8:15 */
499 	uint8_t rcvDataSizeLsb;	/* FC Word 1, bit  0: 7 */
500 
501 	uint8_t concurrentSeqMsb;	/* FC Word 2, bit 24:31 */
502 	uint8_t concurrentSeqLsb;	/* FC Word 2, bit 16:23 */
503 	uint8_t EeCreditSeqMsb;	/* FC Word 2, bit  8:15 */
504 	uint8_t EeCreditSeqLsb;	/* FC Word 2, bit  0: 7 */
505 
506 	uint8_t openSeqPerXchgMsb;	/* FC Word 3, bit 24:31 */
507 	uint8_t openSeqPerXchgLsb;	/* FC Word 3, bit 16:23 */
508 	uint8_t word3Reserved1;	/* Fc Word 3, bit  8:15 */
509 	uint8_t word3Reserved2;	/* Fc Word 3, bit  0: 7 */
510 };
511 
512 #define FAPWWN_KEY_VENDOR	0x42524344 /*valid vendor version fawwpn key*/
513 
514 struct serv_parm {	/* Structure is in Big Endian format */
515 	struct csp cmn;
516 	struct lpfc_name portName;
517 	struct lpfc_name nodeName;
518 	struct class_parms cls1;
519 	struct class_parms cls2;
520 	struct class_parms cls3;
521 	struct class_parms cls4;
522 	union {
523 		uint8_t vendorVersion[16];
524 		struct {
525 			uint32_t vid;
526 #define LPFC_VV_EMLX_ID	0x454d4c58	/* EMLX */
527 			uint32_t flags;
528 #define LPFC_VV_SUPPRESS_RSP	1
529 		} vv;
530 	} un;
531 };
532 
533 /*
534  * Virtual Fabric Tagging Header
535  */
536 struct fc_vft_header {
537 	 uint32_t word0;
538 #define fc_vft_hdr_r_ctl_SHIFT		24
539 #define fc_vft_hdr_r_ctl_MASK		0xFF
540 #define fc_vft_hdr_r_ctl_WORD		word0
541 #define fc_vft_hdr_ver_SHIFT		22
542 #define fc_vft_hdr_ver_MASK		0x3
543 #define fc_vft_hdr_ver_WORD		word0
544 #define fc_vft_hdr_type_SHIFT		18
545 #define fc_vft_hdr_type_MASK		0xF
546 #define fc_vft_hdr_type_WORD		word0
547 #define fc_vft_hdr_e_SHIFT		16
548 #define fc_vft_hdr_e_MASK		0x1
549 #define fc_vft_hdr_e_WORD		word0
550 #define fc_vft_hdr_priority_SHIFT	13
551 #define fc_vft_hdr_priority_MASK	0x7
552 #define fc_vft_hdr_priority_WORD	word0
553 #define fc_vft_hdr_vf_id_SHIFT		1
554 #define fc_vft_hdr_vf_id_MASK		0xFFF
555 #define fc_vft_hdr_vf_id_WORD		word0
556 	uint32_t word1;
557 #define fc_vft_hdr_hopct_SHIFT		24
558 #define fc_vft_hdr_hopct_MASK		0xFF
559 #define fc_vft_hdr_hopct_WORD		word1
560 };
561 
562 /*
563  *  Extended Link Service LS_COMMAND codes (Payload Word 0)
564  */
565 #ifdef __BIG_ENDIAN_BITFIELD
566 #define ELS_CMD_MASK      0xffff0000
567 #define ELS_RSP_MASK      0xff000000
568 #define ELS_CMD_LS_RJT    0x01000000
569 #define ELS_CMD_ACC       0x02000000
570 #define ELS_CMD_PLOGI     0x03000000
571 #define ELS_CMD_FLOGI     0x04000000
572 #define ELS_CMD_LOGO      0x05000000
573 #define ELS_CMD_ABTX      0x06000000
574 #define ELS_CMD_RCS       0x07000000
575 #define ELS_CMD_RES       0x08000000
576 #define ELS_CMD_RSS       0x09000000
577 #define ELS_CMD_RSI       0x0A000000
578 #define ELS_CMD_ESTS      0x0B000000
579 #define ELS_CMD_ESTC      0x0C000000
580 #define ELS_CMD_ADVC      0x0D000000
581 #define ELS_CMD_RTV       0x0E000000
582 #define ELS_CMD_RLS       0x0F000000
583 #define ELS_CMD_ECHO      0x10000000
584 #define ELS_CMD_TEST      0x11000000
585 #define ELS_CMD_RRQ       0x12000000
586 #define ELS_CMD_REC       0x13000000
587 #define ELS_CMD_RDP       0x18000000
588 #define ELS_CMD_PRLI      0x20100014
589 #define ELS_CMD_NVMEPRLI  0x20140018
590 #define ELS_CMD_PRLO      0x21100014
591 #define ELS_CMD_PRLO_ACC  0x02100014
592 #define ELS_CMD_PDISC     0x50000000
593 #define ELS_CMD_FDISC     0x51000000
594 #define ELS_CMD_ADISC     0x52000000
595 #define ELS_CMD_FARP      0x54000000
596 #define ELS_CMD_FARPR     0x55000000
597 #define ELS_CMD_RPS       0x56000000
598 #define ELS_CMD_RPL       0x57000000
599 #define ELS_CMD_FAN       0x60000000
600 #define ELS_CMD_RSCN      0x61040000
601 #define ELS_CMD_SCR       0x62000000
602 #define ELS_CMD_RNID      0x78000000
603 #define ELS_CMD_LIRR      0x7A000000
604 #define ELS_CMD_LCB	  0x81000000
605 #else	/*  __LITTLE_ENDIAN_BITFIELD */
606 #define ELS_CMD_MASK      0xffff
607 #define ELS_RSP_MASK      0xff
608 #define ELS_CMD_LS_RJT    0x01
609 #define ELS_CMD_ACC       0x02
610 #define ELS_CMD_PLOGI     0x03
611 #define ELS_CMD_FLOGI     0x04
612 #define ELS_CMD_LOGO      0x05
613 #define ELS_CMD_ABTX      0x06
614 #define ELS_CMD_RCS       0x07
615 #define ELS_CMD_RES       0x08
616 #define ELS_CMD_RSS       0x09
617 #define ELS_CMD_RSI       0x0A
618 #define ELS_CMD_ESTS      0x0B
619 #define ELS_CMD_ESTC      0x0C
620 #define ELS_CMD_ADVC      0x0D
621 #define ELS_CMD_RTV       0x0E
622 #define ELS_CMD_RLS       0x0F
623 #define ELS_CMD_ECHO      0x10
624 #define ELS_CMD_TEST      0x11
625 #define ELS_CMD_RRQ       0x12
626 #define ELS_CMD_REC       0x13
627 #define ELS_CMD_RDP	  0x18
628 #define ELS_CMD_PRLI      0x14001020
629 #define ELS_CMD_NVMEPRLI  0x18001420
630 #define ELS_CMD_PRLO      0x14001021
631 #define ELS_CMD_PRLO_ACC  0x14001002
632 #define ELS_CMD_PDISC     0x50
633 #define ELS_CMD_FDISC     0x51
634 #define ELS_CMD_ADISC     0x52
635 #define ELS_CMD_FARP      0x54
636 #define ELS_CMD_FARPR     0x55
637 #define ELS_CMD_RPS       0x56
638 #define ELS_CMD_RPL       0x57
639 #define ELS_CMD_FAN       0x60
640 #define ELS_CMD_RSCN      0x0461
641 #define ELS_CMD_SCR       0x62
642 #define ELS_CMD_RNID      0x78
643 #define ELS_CMD_LIRR      0x7A
644 #define ELS_CMD_LCB	  0x81
645 #endif
646 
647 /*
648  *  LS_RJT Payload Definition
649  */
650 
651 struct ls_rjt {	/* Structure is in Big Endian format */
652 	union {
653 		uint32_t lsRjtError;
654 		struct {
655 			uint8_t lsRjtRsvd0;	/* FC Word 0, bit 24:31 */
656 
657 			uint8_t lsRjtRsnCode;	/* FC Word 0, bit 16:23 */
658 			/* LS_RJT reason codes */
659 #define LSRJT_INVALID_CMD     0x01
660 #define LSRJT_LOGICAL_ERR     0x03
661 #define LSRJT_LOGICAL_BSY     0x05
662 #define LSRJT_PROTOCOL_ERR    0x07
663 #define LSRJT_UNABLE_TPC      0x09	/* Unable to perform command */
664 #define LSRJT_CMD_UNSUPPORTED 0x0B
665 #define LSRJT_VENDOR_UNIQUE   0xFF	/* See Byte 3 */
666 
667 			uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
668 			/* LS_RJT reason explanation */
669 #define LSEXP_NOTHING_MORE      0x00
670 #define LSEXP_SPARM_OPTIONS     0x01
671 #define LSEXP_SPARM_ICTL        0x03
672 #define LSEXP_SPARM_RCTL        0x05
673 #define LSEXP_SPARM_RCV_SIZE    0x07
674 #define LSEXP_SPARM_CONCUR_SEQ  0x09
675 #define LSEXP_SPARM_CREDIT      0x0B
676 #define LSEXP_INVALID_PNAME     0x0D
677 #define LSEXP_INVALID_NNAME     0x0E
678 #define LSEXP_INVALID_CSP       0x0F
679 #define LSEXP_INVALID_ASSOC_HDR 0x11
680 #define LSEXP_ASSOC_HDR_REQ     0x13
681 #define LSEXP_INVALID_O_SID     0x15
682 #define LSEXP_INVALID_OX_RX     0x17
683 #define LSEXP_CMD_IN_PROGRESS   0x19
684 #define LSEXP_PORT_LOGIN_REQ    0x1E
685 #define LSEXP_INVALID_NPORT_ID  0x1F
686 #define LSEXP_INVALID_SEQ_ID    0x21
687 #define LSEXP_INVALID_XCHG      0x23
688 #define LSEXP_INACTIVE_XCHG     0x25
689 #define LSEXP_RQ_REQUIRED       0x27
690 #define LSEXP_OUT_OF_RESOURCE   0x29
691 #define LSEXP_CANT_GIVE_DATA    0x2A
692 #define LSEXP_REQ_UNSUPPORTED   0x2C
693 			uint8_t vendorUnique;	/* FC Word 0, bit  0: 7 */
694 		} b;
695 	} un;
696 };
697 
698 /*
699  *  N_Port Login (FLOGO/PLOGO Request) Payload Definition
700  */
701 
702 typedef struct _LOGO {		/* Structure is in Big Endian format */
703 	union {
704 		uint32_t nPortId32;	/* Access nPortId as a word */
705 		struct {
706 			uint8_t word1Reserved1;	/* FC Word 1, bit 31:24 */
707 			uint8_t nPortIdByte0;	/* N_port  ID bit 16:23 */
708 			uint8_t nPortIdByte1;	/* N_port  ID bit  8:15 */
709 			uint8_t nPortIdByte2;	/* N_port  ID bit  0: 7 */
710 		} b;
711 	} un;
712 	struct lpfc_name portName;	/* N_port name field */
713 } LOGO;
714 
715 /*
716  *  FCP Login (PRLI Request / ACC) Payload Definition
717  */
718 
719 #define PRLX_PAGE_LEN   0x10
720 #define TPRLO_PAGE_LEN  0x14
721 
722 typedef struct _PRLI {		/* Structure is in Big Endian format */
723 	uint8_t prliType;	/* FC Parm Word 0, bit 24:31 */
724 
725 #define PRLI_FCP_TYPE 0x08
726 #define PRLI_NVME_TYPE 0x28
727 	uint8_t word0Reserved1;	/* FC Parm Word 0, bit 16:23 */
728 
729 #ifdef __BIG_ENDIAN_BITFIELD
730 	uint8_t origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
731 	uint8_t respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
732 	uint8_t estabImagePair:1;	/* FC Parm Word 0, bit 13 */
733 
734 	/*    ACC = imagePairEstablished */
735 	uint8_t word0Reserved2:1;	/* FC Parm Word 0, bit 12 */
736 	uint8_t acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, ACC ONLY */
737 #else	/*  __LITTLE_ENDIAN_BITFIELD */
738 	uint8_t acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, ACC ONLY */
739 	uint8_t word0Reserved2:1;	/* FC Parm Word 0, bit 12 */
740 	uint8_t estabImagePair:1;	/* FC Parm Word 0, bit 13 */
741 	uint8_t respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
742 	uint8_t origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
743 	/*    ACC = imagePairEstablished */
744 #endif
745 
746 #define PRLI_REQ_EXECUTED     0x1	/* acceptRspCode */
747 #define PRLI_NO_RESOURCES     0x2
748 #define PRLI_INIT_INCOMPLETE  0x3
749 #define PRLI_NO_SUCH_PA       0x4
750 #define PRLI_PREDEF_CONFIG    0x5
751 #define PRLI_PARTIAL_SUCCESS  0x6
752 #define PRLI_INVALID_PAGE_CNT 0x7
753 	uint8_t word0Reserved3;	/* FC Parm Word 0, bit 0:7 */
754 
755 	uint32_t origProcAssoc;	/* FC Parm Word 1, bit 0:31 */
756 
757 	uint32_t respProcAssoc;	/* FC Parm Word 2, bit 0:31 */
758 
759 	uint8_t word3Reserved1;	/* FC Parm Word 3, bit 24:31 */
760 	uint8_t word3Reserved2;	/* FC Parm Word 3, bit 16:23 */
761 
762 #ifdef __BIG_ENDIAN_BITFIELD
763 	uint16_t Word3bit15Resved:1;	/* FC Parm Word 3, bit 15 */
764 	uint16_t Word3bit14Resved:1;	/* FC Parm Word 3, bit 14 */
765 	uint16_t Word3bit13Resved:1;	/* FC Parm Word 3, bit 13 */
766 	uint16_t Word3bit12Resved:1;	/* FC Parm Word 3, bit 12 */
767 	uint16_t Word3bit11Resved:1;	/* FC Parm Word 3, bit 11 */
768 	uint16_t Word3bit10Resved:1;	/* FC Parm Word 3, bit 10 */
769 	uint16_t TaskRetryIdReq:1;	/* FC Parm Word 3, bit  9 */
770 	uint16_t Retry:1;	/* FC Parm Word 3, bit  8 */
771 	uint16_t ConfmComplAllowed:1;	/* FC Parm Word 3, bit  7 */
772 	uint16_t dataOverLay:1;	/* FC Parm Word 3, bit  6 */
773 	uint16_t initiatorFunc:1;	/* FC Parm Word 3, bit  5 */
774 	uint16_t targetFunc:1;	/* FC Parm Word 3, bit  4 */
775 	uint16_t cmdDataMixEna:1;	/* FC Parm Word 3, bit  3 */
776 	uint16_t dataRspMixEna:1;	/* FC Parm Word 3, bit  2 */
777 	uint16_t readXferRdyDis:1;	/* FC Parm Word 3, bit  1 */
778 	uint16_t writeXferRdyDis:1;	/* FC Parm Word 3, bit  0 */
779 #else	/*  __LITTLE_ENDIAN_BITFIELD */
780 	uint16_t Retry:1;	/* FC Parm Word 3, bit  8 */
781 	uint16_t TaskRetryIdReq:1;	/* FC Parm Word 3, bit  9 */
782 	uint16_t Word3bit10Resved:1;	/* FC Parm Word 3, bit 10 */
783 	uint16_t Word3bit11Resved:1;	/* FC Parm Word 3, bit 11 */
784 	uint16_t Word3bit12Resved:1;	/* FC Parm Word 3, bit 12 */
785 	uint16_t Word3bit13Resved:1;	/* FC Parm Word 3, bit 13 */
786 	uint16_t Word3bit14Resved:1;	/* FC Parm Word 3, bit 14 */
787 	uint16_t Word3bit15Resved:1;	/* FC Parm Word 3, bit 15 */
788 	uint16_t writeXferRdyDis:1;	/* FC Parm Word 3, bit  0 */
789 	uint16_t readXferRdyDis:1;	/* FC Parm Word 3, bit  1 */
790 	uint16_t dataRspMixEna:1;	/* FC Parm Word 3, bit  2 */
791 	uint16_t cmdDataMixEna:1;	/* FC Parm Word 3, bit  3 */
792 	uint16_t targetFunc:1;	/* FC Parm Word 3, bit  4 */
793 	uint16_t initiatorFunc:1;	/* FC Parm Word 3, bit  5 */
794 	uint16_t dataOverLay:1;	/* FC Parm Word 3, bit  6 */
795 	uint16_t ConfmComplAllowed:1;	/* FC Parm Word 3, bit  7 */
796 #endif
797 } PRLI;
798 
799 /*
800  *  FCP Logout (PRLO Request / ACC) Payload Definition
801  */
802 
803 typedef struct _PRLO {		/* Structure is in Big Endian format */
804 	uint8_t prloType;	/* FC Parm Word 0, bit 24:31 */
805 
806 #define PRLO_FCP_TYPE  0x08
807 	uint8_t word0Reserved1;	/* FC Parm Word 0, bit 16:23 */
808 
809 #ifdef __BIG_ENDIAN_BITFIELD
810 	uint8_t origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
811 	uint8_t respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
812 	uint8_t word0Reserved2:2;	/* FC Parm Word 0, bit 12:13 */
813 	uint8_t acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, ACC ONLY */
814 #else	/*  __LITTLE_ENDIAN_BITFIELD */
815 	uint8_t acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, ACC ONLY */
816 	uint8_t word0Reserved2:2;	/* FC Parm Word 0, bit 12:13 */
817 	uint8_t respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
818 	uint8_t origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
819 #endif
820 
821 #define PRLO_REQ_EXECUTED     0x1	/* acceptRspCode */
822 #define PRLO_NO_SUCH_IMAGE    0x4
823 #define PRLO_INVALID_PAGE_CNT 0x7
824 
825 	uint8_t word0Reserved3;	/* FC Parm Word 0, bit 0:7 */
826 
827 	uint32_t origProcAssoc;	/* FC Parm Word 1, bit 0:31 */
828 
829 	uint32_t respProcAssoc;	/* FC Parm Word 2, bit 0:31 */
830 
831 	uint32_t word3Reserved1;	/* FC Parm Word 3, bit 0:31 */
832 } PRLO;
833 
834 typedef struct _ADISC {		/* Structure is in Big Endian format */
835 	uint32_t hardAL_PA;
836 	struct lpfc_name portName;
837 	struct lpfc_name nodeName;
838 	uint32_t DID;
839 } ADISC;
840 
841 typedef struct _FARP {		/* Structure is in Big Endian format */
842 	uint32_t Mflags:8;
843 	uint32_t Odid:24;
844 #define FARP_NO_ACTION          0	/* FARP information enclosed, no
845 					   action */
846 #define FARP_MATCH_PORT         0x1	/* Match on Responder Port Name */
847 #define FARP_MATCH_NODE         0x2	/* Match on Responder Node Name */
848 #define FARP_MATCH_IP           0x4	/* Match on IP address, not supported */
849 #define FARP_MATCH_IPV4         0x5	/* Match on IPV4 address, not
850 					   supported */
851 #define FARP_MATCH_IPV6         0x6	/* Match on IPV6 address, not
852 					   supported */
853 	uint32_t Rflags:8;
854 	uint32_t Rdid:24;
855 #define FARP_REQUEST_PLOGI      0x1	/* Request for PLOGI */
856 #define FARP_REQUEST_FARPR      0x2	/* Request for FARP Response */
857 	struct lpfc_name OportName;
858 	struct lpfc_name OnodeName;
859 	struct lpfc_name RportName;
860 	struct lpfc_name RnodeName;
861 	uint8_t Oipaddr[16];
862 	uint8_t Ripaddr[16];
863 } FARP;
864 
865 typedef struct _FAN {		/* Structure is in Big Endian format */
866 	uint32_t Fdid;
867 	struct lpfc_name FportName;
868 	struct lpfc_name FnodeName;
869 } FAN;
870 
871 typedef struct _SCR {		/* Structure is in Big Endian format */
872 	uint8_t resvd1;
873 	uint8_t resvd2;
874 	uint8_t resvd3;
875 	uint8_t Function;
876 #define  SCR_FUNC_FABRIC     0x01
877 #define  SCR_FUNC_NPORT      0x02
878 #define  SCR_FUNC_FULL       0x03
879 #define  SCR_CLEAR           0xff
880 } SCR;
881 
882 typedef struct _RNID_TOP_DISC {
883 	struct lpfc_name portName;
884 	uint8_t resvd[8];
885 	uint32_t unitType;
886 #define RNID_HBA            0x7
887 #define RNID_HOST           0xa
888 #define RNID_DRIVER         0xd
889 	uint32_t physPort;
890 	uint32_t attachedNodes;
891 	uint16_t ipVersion;
892 #define RNID_IPV4           0x1
893 #define RNID_IPV6           0x2
894 	uint16_t UDPport;
895 	uint8_t ipAddr[16];
896 	uint16_t resvd1;
897 	uint16_t flags;
898 #define RNID_TD_SUPPORT     0x1
899 #define RNID_LP_VALID       0x2
900 } RNID_TOP_DISC;
901 
902 typedef struct _RNID {		/* Structure is in Big Endian format */
903 	uint8_t Format;
904 #define RNID_TOPOLOGY_DISC  0xdf
905 	uint8_t CommonLen;
906 	uint8_t resvd1;
907 	uint8_t SpecificLen;
908 	struct lpfc_name portName;
909 	struct lpfc_name nodeName;
910 	union {
911 		RNID_TOP_DISC topologyDisc;	/* topology disc (0xdf) */
912 	} un;
913 } RNID;
914 
915 typedef struct  _RPS {		/* Structure is in Big Endian format */
916 	union {
917 		uint32_t portNum;
918 		struct lpfc_name portName;
919 	} un;
920 } RPS;
921 
922 typedef struct  _RPS_RSP {	/* Structure is in Big Endian format */
923 	uint16_t rsvd1;
924 	uint16_t portStatus;
925 	uint32_t linkFailureCnt;
926 	uint32_t lossSyncCnt;
927 	uint32_t lossSignalCnt;
928 	uint32_t primSeqErrCnt;
929 	uint32_t invalidXmitWord;
930 	uint32_t crcCnt;
931 } RPS_RSP;
932 
933 struct RLS {			/* Structure is in Big Endian format */
934 	uint32_t rls;
935 #define rls_rsvd_SHIFT		24
936 #define rls_rsvd_MASK		0x000000ff
937 #define rls_rsvd_WORD		rls
938 #define rls_did_SHIFT		0
939 #define rls_did_MASK		0x00ffffff
940 #define rls_did_WORD		rls
941 };
942 
943 struct  RLS_RSP {		/* Structure is in Big Endian format */
944 	uint32_t linkFailureCnt;
945 	uint32_t lossSyncCnt;
946 	uint32_t lossSignalCnt;
947 	uint32_t primSeqErrCnt;
948 	uint32_t invalidXmitWord;
949 	uint32_t crcCnt;
950 };
951 
952 struct RRQ {			/* Structure is in Big Endian format */
953 	uint32_t rrq;
954 #define rrq_rsvd_SHIFT		24
955 #define rrq_rsvd_MASK		0x000000ff
956 #define rrq_rsvd_WORD		rrq
957 #define rrq_did_SHIFT		0
958 #define rrq_did_MASK		0x00ffffff
959 #define rrq_did_WORD		rrq
960 	uint32_t rrq_exchg;
961 #define rrq_oxid_SHIFT		16
962 #define rrq_oxid_MASK		0xffff
963 #define rrq_oxid_WORD		rrq_exchg
964 #define rrq_rxid_SHIFT		0
965 #define rrq_rxid_MASK		0xffff
966 #define rrq_rxid_WORD		rrq_exchg
967 };
968 
969 #define LPFC_MAX_VFN_PER_PFN	255 /* Maximum VFs allowed per ARI */
970 #define LPFC_DEF_VFN_PER_PFN	0   /* Default VFs due to platform limitation*/
971 
972 struct RTV_RSP {		/* Structure is in Big Endian format */
973 	uint32_t ratov;
974 	uint32_t edtov;
975 	uint32_t qtov;
976 #define qtov_rsvd0_SHIFT	28
977 #define qtov_rsvd0_MASK		0x0000000f
978 #define qtov_rsvd0_WORD		qtov		/* reserved */
979 #define qtov_edtovres_SHIFT	27
980 #define qtov_edtovres_MASK	0x00000001
981 #define qtov_edtovres_WORD	qtov		/* E_D_TOV Resolution */
982 #define qtov__rsvd1_SHIFT	19
983 #define qtov_rsvd1_MASK		0x0000003f
984 #define qtov_rsvd1_WORD		qtov		/* reserved */
985 #define qtov_rttov_SHIFT	18
986 #define qtov_rttov_MASK		0x00000001
987 #define qtov_rttov_WORD		qtov		/* R_T_TOV value */
988 #define qtov_rsvd2_SHIFT	0
989 #define qtov_rsvd2_MASK		0x0003ffff
990 #define qtov_rsvd2_WORD		qtov		/* reserved */
991 };
992 
993 
994 typedef struct  _RPL {		/* Structure is in Big Endian format */
995 	uint32_t maxsize;
996 	uint32_t index;
997 } RPL;
998 
999 typedef struct  _PORT_NUM_BLK {
1000 	uint32_t portNum;
1001 	uint32_t portID;
1002 	struct lpfc_name portName;
1003 } PORT_NUM_BLK;
1004 
1005 typedef struct  _RPL_RSP {	/* Structure is in Big Endian format */
1006 	uint32_t listLen;
1007 	uint32_t index;
1008 	PORT_NUM_BLK port_num_blk;
1009 } RPL_RSP;
1010 
1011 /* This is used for RSCN command */
1012 typedef struct _D_ID {		/* Structure is in Big Endian format */
1013 	union {
1014 		uint32_t word;
1015 		struct {
1016 #ifdef __BIG_ENDIAN_BITFIELD
1017 			uint8_t resv;
1018 			uint8_t domain;
1019 			uint8_t area;
1020 			uint8_t id;
1021 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1022 			uint8_t id;
1023 			uint8_t area;
1024 			uint8_t domain;
1025 			uint8_t resv;
1026 #endif
1027 		} b;
1028 	} un;
1029 } D_ID;
1030 
1031 #define RSCN_ADDRESS_FORMAT_PORT	0x0
1032 #define RSCN_ADDRESS_FORMAT_AREA	0x1
1033 #define RSCN_ADDRESS_FORMAT_DOMAIN	0x2
1034 #define RSCN_ADDRESS_FORMAT_FABRIC	0x3
1035 #define RSCN_ADDRESS_FORMAT_MASK	0x3
1036 
1037 /*
1038  *  Structure to define all ELS Payload types
1039  */
1040 
1041 typedef struct _ELS_PKT {	/* Structure is in Big Endian format */
1042 	uint8_t elsCode;	/* FC Word 0, bit 24:31 */
1043 	uint8_t elsByte1;
1044 	uint8_t elsByte2;
1045 	uint8_t elsByte3;
1046 	union {
1047 		struct ls_rjt lsRjt;	/* Payload for LS_RJT ELS response */
1048 		struct serv_parm logi;	/* Payload for PLOGI/FLOGI/PDISC/ACC */
1049 		LOGO logo;	/* Payload for PLOGO/FLOGO/ACC */
1050 		PRLI prli;	/* Payload for PRLI/ACC */
1051 		PRLO prlo;	/* Payload for PRLO/ACC */
1052 		ADISC adisc;	/* Payload for ADISC/ACC */
1053 		FARP farp;	/* Payload for FARP/ACC */
1054 		FAN fan;	/* Payload for FAN */
1055 		SCR scr;	/* Payload for SCR/ACC */
1056 		RNID rnid;	/* Payload for RNID */
1057 		uint8_t pad[128 - 4];	/* Pad out to payload of 128 bytes */
1058 	} un;
1059 } ELS_PKT;
1060 
1061 /*
1062  * Link Cable Beacon (LCB) ELS Frame
1063  */
1064 
1065 struct fc_lcb_request_frame {
1066 	uint32_t      lcb_command;      /* ELS command opcode (0x81)     */
1067 	uint8_t       lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1068 #define LPFC_LCB_ON		0x1
1069 #define LPFC_LCB_OFF		0x2
1070 	uint8_t       reserved[2];
1071 	uint8_t	      capability;	/* LCB Payload Word 1, bit 0:7 */
1072 	uint8_t       lcb_type; /* LCB Payload Word 2, bit 24:31 */
1073 #define LPFC_LCB_GREEN		0x1
1074 #define LPFC_LCB_AMBER		0x2
1075 	uint8_t       lcb_frequency;    /* LCB Payload Word 2, bit 16:23 */
1076 #define LCB_CAPABILITY_DURATION	1
1077 #define BEACON_VERSION_V1	1
1078 #define BEACON_VERSION_V0	0
1079 	uint16_t      lcb_duration;     /* LCB Payload Word 2, bit 15:0  */
1080 };
1081 
1082 /*
1083  * Link Cable Beacon (LCB) ELS Response Frame
1084  */
1085 struct fc_lcb_res_frame {
1086 	uint32_t      lcb_ls_acc;       /* Acceptance of LCB request (0x02) */
1087 	uint8_t       lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1088 	uint8_t       reserved[2];
1089 	uint8_t	      capability;	/* LCB Payload Word 1, bit 0:7 */
1090 	uint8_t       lcb_type; /* LCB Payload Word 2, bit 24:31 */
1091 	uint8_t       lcb_frequency;    /* LCB Payload Word 2, bit 16:23 */
1092 	uint16_t      lcb_duration;     /* LCB Payload Word 2, bit 15:0  */
1093 };
1094 
1095 /*
1096  * Read Diagnostic Parameters (RDP) ELS frame.
1097  */
1098 #define SFF_PG0_IDENT_SFP              0x3
1099 
1100 #define SFP_FLAG_PT_OPTICAL            0x0
1101 #define SFP_FLAG_PT_SWLASER            0x01
1102 #define SFP_FLAG_PT_LWLASER_LC1310     0x02
1103 #define SFP_FLAG_PT_LWLASER_LL1550     0x03
1104 #define SFP_FLAG_PT_MASK               0x0F
1105 #define SFP_FLAG_PT_SHIFT              0
1106 
1107 #define SFP_FLAG_IS_OPTICAL_PORT       0x01
1108 #define SFP_FLAG_IS_OPTICAL_MASK       0x010
1109 #define SFP_FLAG_IS_OPTICAL_SHIFT      4
1110 
1111 #define SFP_FLAG_IS_DESC_VALID         0x01
1112 #define SFP_FLAG_IS_DESC_VALID_MASK    0x020
1113 #define SFP_FLAG_IS_DESC_VALID_SHIFT   5
1114 
1115 #define SFP_FLAG_CT_UNKNOWN            0x0
1116 #define SFP_FLAG_CT_SFP_PLUS           0x01
1117 #define SFP_FLAG_CT_MASK               0x3C
1118 #define SFP_FLAG_CT_SHIFT              6
1119 
1120 struct fc_rdp_port_name_info {
1121 	uint8_t wwnn[8];
1122 	uint8_t wwpn[8];
1123 };
1124 
1125 
1126 /*
1127  * Link Error Status Block Structure (FC-FS-3) for RDP
1128  * This similar to RPS ELS
1129  */
1130 struct fc_link_status {
1131 	uint32_t      link_failure_cnt;
1132 	uint32_t      loss_of_synch_cnt;
1133 	uint32_t      loss_of_signal_cnt;
1134 	uint32_t      primitive_seq_proto_err;
1135 	uint32_t      invalid_trans_word;
1136 	uint32_t      invalid_crc_cnt;
1137 
1138 };
1139 
1140 #define RDP_PORT_NAMES_DESC_TAG  0x00010003
1141 struct fc_rdp_port_name_desc {
1142 	uint32_t	tag;     /* 0001 0003h */
1143 	uint32_t	length;  /* set to size of payload struct */
1144 	struct fc_rdp_port_name_info  port_names;
1145 };
1146 
1147 
1148 struct fc_rdp_fec_info {
1149 	uint32_t CorrectedBlocks;
1150 	uint32_t UncorrectableBlocks;
1151 };
1152 
1153 #define RDP_FEC_DESC_TAG  0x00010005
1154 struct fc_fec_rdp_desc {
1155 	uint32_t tag;
1156 	uint32_t length;
1157 	struct fc_rdp_fec_info info;
1158 };
1159 
1160 struct fc_rdp_link_error_status_payload_info {
1161 	struct fc_link_status link_status; /* 24 bytes */
1162 	uint32_t  port_type;             /* bits 31-30 only */
1163 };
1164 
1165 #define RDP_LINK_ERROR_STATUS_DESC_TAG  0x00010002
1166 struct fc_rdp_link_error_status_desc {
1167 	uint32_t         tag;     /* 0001 0002h */
1168 	uint32_t         length;  /* set to size of payload struct */
1169 	struct fc_rdp_link_error_status_payload_info info;
1170 };
1171 
1172 #define VN_PT_PHY_UNKNOWN      0x00
1173 #define VN_PT_PHY_PF_PORT      0x01
1174 #define VN_PT_PHY_ETH_MAC      0x10
1175 #define VN_PT_PHY_SHIFT                30
1176 
1177 #define RDP_PS_1GB             0x8000
1178 #define RDP_PS_2GB             0x4000
1179 #define RDP_PS_4GB             0x2000
1180 #define RDP_PS_10GB            0x1000
1181 #define RDP_PS_8GB             0x0800
1182 #define RDP_PS_16GB            0x0400
1183 #define RDP_PS_32GB            0x0200
1184 #define RDP_PS_64GB            0x0100
1185 #define RDP_PS_128GB           0x0080
1186 #define RDP_PS_256GB           0x0040
1187 
1188 #define RDP_CAP_USER_CONFIGURED 0x0002
1189 #define RDP_CAP_UNKNOWN         0x0001
1190 #define RDP_PS_UNKNOWN          0x0002
1191 #define RDP_PS_NOT_ESTABLISHED  0x0001
1192 
1193 struct fc_rdp_port_speed {
1194 	uint16_t   capabilities;
1195 	uint16_t   speed;
1196 };
1197 
1198 struct fc_rdp_port_speed_info {
1199 	struct fc_rdp_port_speed   port_speed;
1200 };
1201 
1202 #define RDP_PORT_SPEED_DESC_TAG  0x00010001
1203 struct fc_rdp_port_speed_desc {
1204 	uint32_t         tag;            /* 00010001h */
1205 	uint32_t         length;         /* set to size of payload struct */
1206 	struct fc_rdp_port_speed_info info;
1207 };
1208 
1209 #define RDP_NPORT_ID_SIZE      4
1210 #define RDP_N_PORT_DESC_TAG    0x00000003
1211 struct fc_rdp_nport_desc {
1212 	uint32_t         tag;          /* 0000 0003h, big endian */
1213 	uint32_t         length;       /* size of RDP_N_PORT_ID struct */
1214 	uint32_t         nport_id : 12;
1215 	uint32_t         reserved : 8;
1216 };
1217 
1218 
1219 struct fc_rdp_link_service_info {
1220 	uint32_t         els_req;    /* Request payload word 0 value.*/
1221 };
1222 
1223 #define RDP_LINK_SERVICE_DESC_TAG  0x00000001
1224 struct fc_rdp_link_service_desc {
1225 	uint32_t         tag;     /* Descriptor tag  1 */
1226 	uint32_t         length;  /* set to size of payload struct. */
1227 	struct fc_rdp_link_service_info  payload;
1228 				  /* must be ELS req Word 0(0x18) */
1229 };
1230 
1231 struct fc_rdp_sfp_info {
1232 	uint16_t	temperature;
1233 	uint16_t	vcc;
1234 	uint16_t	tx_bias;
1235 	uint16_t	tx_power;
1236 	uint16_t	rx_power;
1237 	uint16_t	flags;
1238 };
1239 
1240 #define RDP_SFP_DESC_TAG  0x00010000
1241 struct fc_rdp_sfp_desc {
1242 	uint32_t         tag;
1243 	uint32_t         length;  /* set to size of sfp_info struct */
1244 	struct fc_rdp_sfp_info sfp_info;
1245 };
1246 
1247 /* Buffer Credit Descriptor */
1248 struct fc_rdp_bbc_info {
1249 	uint32_t              port_bbc; /* FC_Port buffer-to-buffer credit */
1250 	uint32_t              attached_port_bbc;
1251 	uint32_t              rtt;      /* Round trip time */
1252 };
1253 #define RDP_BBC_DESC_TAG  0x00010006
1254 struct fc_rdp_bbc_desc {
1255 	uint32_t              tag;
1256 	uint32_t              length;
1257 	struct fc_rdp_bbc_info  bbc_info;
1258 };
1259 
1260 /* Optical Element Type Transgression Flags */
1261 #define RDP_OET_LOW_WARNING  0x1
1262 #define RDP_OET_HIGH_WARNING 0x2
1263 #define RDP_OET_LOW_ALARM    0x4
1264 #define RDP_OET_HIGH_ALARM   0x8
1265 
1266 #define RDP_OED_TEMPERATURE  0x1
1267 #define RDP_OED_VOLTAGE      0x2
1268 #define RDP_OED_TXBIAS       0x3
1269 #define RDP_OED_TXPOWER      0x4
1270 #define RDP_OED_RXPOWER      0x5
1271 
1272 #define RDP_OED_TYPE_SHIFT   28
1273 /* Optical Element Data descriptor */
1274 struct fc_rdp_oed_info {
1275 	uint16_t            hi_alarm;
1276 	uint16_t            lo_alarm;
1277 	uint16_t            hi_warning;
1278 	uint16_t            lo_warning;
1279 	uint32_t            function_flags;
1280 };
1281 #define RDP_OED_DESC_TAG  0x00010007
1282 struct fc_rdp_oed_sfp_desc {
1283 	uint32_t             tag;
1284 	uint32_t             length;
1285 	struct fc_rdp_oed_info oed_info;
1286 };
1287 
1288 /* Optical Product Data descriptor */
1289 struct fc_rdp_opd_sfp_info {
1290 	uint8_t            vendor_name[16];
1291 	uint8_t            model_number[16];
1292 	uint8_t            serial_number[16];
1293 	uint8_t            revision[4];
1294 	uint8_t            date[8];
1295 };
1296 
1297 #define RDP_OPD_DESC_TAG  0x00010008
1298 struct fc_rdp_opd_sfp_desc {
1299 	uint32_t             tag;
1300 	uint32_t             length;
1301 	struct fc_rdp_opd_sfp_info opd_info;
1302 };
1303 
1304 struct fc_rdp_req_frame {
1305 	uint32_t         rdp_command;           /* ELS command opcode (0x18)*/
1306 	uint32_t         rdp_des_length;        /* RDP Payload Word 1 */
1307 	struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1308 };
1309 
1310 
1311 struct fc_rdp_res_frame {
1312 	uint32_t    reply_sequence;		/* FC word0 LS_ACC or LS_RJT */
1313 	uint32_t   length;			/* FC Word 1      */
1314 	struct fc_rdp_link_service_desc link_service_desc;    /* Word 2 -4   */
1315 	struct fc_rdp_sfp_desc sfp_desc;                      /* Word 5 -9   */
1316 	struct fc_rdp_port_speed_desc portspeed_desc;         /* Word 10 -12 */
1317 	struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */
1318 	struct fc_rdp_port_name_desc diag_port_names_desc;    /* Word 22 -27 */
1319 	struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */
1320 	struct fc_fec_rdp_desc fec_desc;                      /* FC word 34-37*/
1321 	struct fc_rdp_bbc_desc bbc_desc;                      /* FC Word 38-42*/
1322 	struct fc_rdp_oed_sfp_desc oed_temp_desc;             /* FC Word 43-47*/
1323 	struct fc_rdp_oed_sfp_desc oed_voltage_desc;          /* FC word 48-52*/
1324 	struct fc_rdp_oed_sfp_desc oed_txbias_desc;           /* FC word 53-57*/
1325 	struct fc_rdp_oed_sfp_desc oed_txpower_desc;          /* FC word 58-62*/
1326 	struct fc_rdp_oed_sfp_desc oed_rxpower_desc;          /* FC word 63-67*/
1327 	struct fc_rdp_opd_sfp_desc opd_desc;                  /* FC word 68-84*/
1328 };
1329 
1330 
1331 /******** FDMI ********/
1332 
1333 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1334 #define  SLI_CT_FDMI_Subtypes     0x10	/* Management Service Subtype */
1335 
1336 /*
1337  * Registered Port List Format
1338  */
1339 struct lpfc_fdmi_reg_port_list {
1340 	uint32_t EntryCnt;
1341 	uint32_t pe;		/* Variable-length array */
1342 };
1343 
1344 
1345 /* Definitions for HBA / Port attribute entries */
1346 
1347 struct lpfc_fdmi_attr_def { /* Defined in TLV format */
1348 	/* Structure is in Big Endian format */
1349 	uint32_t AttrType:16;
1350 	uint32_t AttrLen:16;
1351 	uint32_t AttrValue;  /* Marks start of Value (ATTRIBUTE_ENTRY) */
1352 };
1353 
1354 
1355 /* Attribute Entry */
1356 struct lpfc_fdmi_attr_entry {
1357 	union {
1358 		uint32_t AttrInt;
1359 		uint8_t  AttrTypes[32];
1360 		uint8_t  AttrString[256];
1361 		struct lpfc_name AttrWWN;
1362 	} un;
1363 };
1364 
1365 #define LPFC_FDMI_MAX_AE_SIZE	sizeof(struct lpfc_fdmi_attr_entry)
1366 
1367 /*
1368  * HBA Attribute Block
1369  */
1370 struct lpfc_fdmi_attr_block {
1371 	uint32_t EntryCnt;		/* Number of HBA attribute entries */
1372 	struct lpfc_fdmi_attr_entry Entry;	/* Variable-length array */
1373 };
1374 
1375 /*
1376  * Port Entry
1377  */
1378 struct lpfc_fdmi_port_entry {
1379 	struct lpfc_name PortName;
1380 };
1381 
1382 /*
1383  * HBA Identifier
1384  */
1385 struct lpfc_fdmi_hba_ident {
1386 	struct lpfc_name PortName;
1387 };
1388 
1389 /*
1390  * Register HBA(RHBA)
1391  */
1392 struct lpfc_fdmi_reg_hba {
1393 	struct lpfc_fdmi_hba_ident hi;
1394 	struct lpfc_fdmi_reg_port_list rpl;	/* variable-length array */
1395 /* struct lpfc_fdmi_attr_block   ab; */
1396 };
1397 
1398 /*
1399  * Register HBA Attributes (RHAT)
1400  */
1401 struct lpfc_fdmi_reg_hbaattr {
1402 	struct lpfc_name HBA_PortName;
1403 	struct lpfc_fdmi_attr_block ab;
1404 };
1405 
1406 /*
1407  * Register Port Attributes (RPA)
1408  */
1409 struct lpfc_fdmi_reg_portattr {
1410 	struct lpfc_name PortName;
1411 	struct lpfc_fdmi_attr_block ab;
1412 };
1413 
1414 /*
1415  * HBA MAnagement Operations Command Codes
1416  */
1417 #define  SLI_MGMT_GRHL     0x100	/* Get registered HBA list */
1418 #define  SLI_MGMT_GHAT     0x101	/* Get HBA attributes */
1419 #define  SLI_MGMT_GRPL     0x102	/* Get registered Port list */
1420 #define  SLI_MGMT_GPAT     0x110	/* Get Port attributes */
1421 #define  SLI_MGMT_GPAS     0x120	/* Get Port Statistics */
1422 #define  SLI_MGMT_RHBA     0x200	/* Register HBA */
1423 #define  SLI_MGMT_RHAT     0x201	/* Register HBA attributes */
1424 #define  SLI_MGMT_RPRT     0x210	/* Register Port */
1425 #define  SLI_MGMT_RPA      0x211	/* Register Port attributes */
1426 #define  SLI_MGMT_DHBA     0x300	/* De-register HBA */
1427 #define  SLI_MGMT_DHAT     0x301	/* De-register HBA attributes */
1428 #define  SLI_MGMT_DPRT     0x310	/* De-register Port */
1429 #define  SLI_MGMT_DPA      0x311	/* De-register Port attributes */
1430 
1431 #define LPFC_FDMI_MAX_RETRY     3  /* Max retries for a FDMI command */
1432 
1433 /*
1434  * HBA Attribute Types
1435  */
1436 #define  RHBA_NODENAME           0x1 /* 8 byte WWNN */
1437 #define  RHBA_MANUFACTURER       0x2 /* 4 to 64 byte ASCII string */
1438 #define  RHBA_SERIAL_NUMBER      0x3 /* 4 to 64 byte ASCII string */
1439 #define  RHBA_MODEL              0x4 /* 4 to 256 byte ASCII string */
1440 #define  RHBA_MODEL_DESCRIPTION  0x5 /* 4 to 256 byte ASCII string */
1441 #define  RHBA_HARDWARE_VERSION   0x6 /* 4 to 256 byte ASCII string */
1442 #define  RHBA_DRIVER_VERSION     0x7 /* 4 to 256 byte ASCII string */
1443 #define  RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1444 #define  RHBA_FIRMWARE_VERSION   0x9 /* 4 to 256 byte ASCII string */
1445 #define  RHBA_OS_NAME_VERSION	 0xa /* 4 to 256 byte ASCII string */
1446 #define  RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1447 #define  RHBA_SYM_NODENAME       0xc /* 4 to 256 byte ASCII string */
1448 #define  RHBA_VENDOR_INFO        0xd  /* 32-bit unsigned int */
1449 #define  RHBA_NUM_PORTS          0xe  /* 32-bit unsigned int */
1450 #define  RHBA_FABRIC_WWNN        0xf  /* 8 byte WWNN */
1451 #define  RHBA_BIOS_VERSION       0x10 /* 4 to 256 byte ASCII string */
1452 #define  RHBA_BIOS_STATE         0x11 /* 32-bit unsigned int */
1453 #define  RHBA_VENDOR_ID          0xe0 /* 8 byte ASCII string */
1454 
1455 /* Bit mask for all individual HBA attributes */
1456 #define LPFC_FDMI_HBA_ATTR_wwnn			0x00000001
1457 #define LPFC_FDMI_HBA_ATTR_manufacturer		0x00000002
1458 #define LPFC_FDMI_HBA_ATTR_sn			0x00000004
1459 #define LPFC_FDMI_HBA_ATTR_model		0x00000008
1460 #define LPFC_FDMI_HBA_ATTR_description		0x00000010
1461 #define LPFC_FDMI_HBA_ATTR_hdw_ver		0x00000020
1462 #define LPFC_FDMI_HBA_ATTR_drvr_ver		0x00000040
1463 #define LPFC_FDMI_HBA_ATTR_rom_ver		0x00000080
1464 #define LPFC_FDMI_HBA_ATTR_fmw_ver		0x00000100
1465 #define LPFC_FDMI_HBA_ATTR_os_ver		0x00000200
1466 #define LPFC_FDMI_HBA_ATTR_ct_len		0x00000400
1467 #define LPFC_FDMI_HBA_ATTR_symbolic_name	0x00000800
1468 #define LPFC_FDMI_HBA_ATTR_vendor_info		0x00001000 /* Not used */
1469 #define LPFC_FDMI_HBA_ATTR_num_ports		0x00002000
1470 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn		0x00004000
1471 #define LPFC_FDMI_HBA_ATTR_bios_ver		0x00008000
1472 #define LPFC_FDMI_HBA_ATTR_bios_state		0x00010000 /* Not used */
1473 #define LPFC_FDMI_HBA_ATTR_vendor_id		0x00020000
1474 
1475 /* Bit mask for FDMI-1 defined HBA attributes */
1476 #define LPFC_FDMI1_HBA_ATTR			0x000007ff
1477 
1478 /* Bit mask for FDMI-2 defined HBA attributes */
1479 /* Skip vendor_info and bios_state */
1480 #define LPFC_FDMI2_HBA_ATTR			0x0002efff
1481 
1482 /*
1483  * Port Attrubute Types
1484  */
1485 #define  RPRT_SUPPORTED_FC4_TYPES     0x1 /* 32 byte binary array */
1486 #define  RPRT_SUPPORTED_SPEED         0x2 /* 32-bit unsigned int */
1487 #define  RPRT_PORT_SPEED              0x3 /* 32-bit unsigned int */
1488 #define  RPRT_MAX_FRAME_SIZE          0x4 /* 32-bit unsigned int */
1489 #define  RPRT_OS_DEVICE_NAME          0x5 /* 4 to 256 byte ASCII string */
1490 #define  RPRT_HOST_NAME               0x6 /* 4 to 256 byte ASCII string */
1491 #define  RPRT_NODENAME                0x7 /* 8 byte WWNN */
1492 #define  RPRT_PORTNAME                0x8 /* 8 byte WWPN */
1493 #define  RPRT_SYM_PORTNAME            0x9 /* 4 to 256 byte ASCII string */
1494 #define  RPRT_PORT_TYPE               0xa /* 32-bit unsigned int */
1495 #define  RPRT_SUPPORTED_CLASS         0xb /* 32-bit unsigned int */
1496 #define  RPRT_FABRICNAME              0xc /* 8 byte Fabric WWPN */
1497 #define  RPRT_ACTIVE_FC4_TYPES        0xd /* 32 byte binary array */
1498 #define  RPRT_PORT_STATE              0x101 /* 32-bit unsigned int */
1499 #define  RPRT_DISC_PORT               0x102 /* 32-bit unsigned int */
1500 #define  RPRT_PORT_ID                 0x103 /* 32-bit unsigned int */
1501 #define  RPRT_SMART_SERVICE           0xf100 /* 4 to 256 byte ASCII string */
1502 #define  RPRT_SMART_GUID              0xf101 /* 8 byte WWNN + 8 byte WWPN */
1503 #define  RPRT_SMART_VERSION           0xf102 /* 4 to 256 byte ASCII string */
1504 #define  RPRT_SMART_MODEL             0xf103 /* 4 to 256 byte ASCII string */
1505 #define  RPRT_SMART_PORT_INFO         0xf104 /* 32-bit unsigned int */
1506 #define  RPRT_SMART_QOS               0xf105 /* 32-bit unsigned int */
1507 #define  RPRT_SMART_SECURITY          0xf106 /* 32-bit unsigned int */
1508 
1509 /* Bit mask for all individual PORT attributes */
1510 #define LPFC_FDMI_PORT_ATTR_fc4type		0x00000001
1511 #define LPFC_FDMI_PORT_ATTR_support_speed	0x00000002
1512 #define LPFC_FDMI_PORT_ATTR_speed		0x00000004
1513 #define LPFC_FDMI_PORT_ATTR_max_frame		0x00000008
1514 #define LPFC_FDMI_PORT_ATTR_os_devname		0x00000010
1515 #define LPFC_FDMI_PORT_ATTR_host_name		0x00000020
1516 #define LPFC_FDMI_PORT_ATTR_wwnn		0x00000040
1517 #define LPFC_FDMI_PORT_ATTR_wwpn		0x00000080
1518 #define LPFC_FDMI_PORT_ATTR_symbolic_name	0x00000100
1519 #define LPFC_FDMI_PORT_ATTR_port_type		0x00000200
1520 #define LPFC_FDMI_PORT_ATTR_class		0x00000400
1521 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn		0x00000800
1522 #define LPFC_FDMI_PORT_ATTR_port_state		0x00001000
1523 #define LPFC_FDMI_PORT_ATTR_active_fc4type	0x00002000
1524 #define LPFC_FDMI_PORT_ATTR_num_disc		0x00004000
1525 #define LPFC_FDMI_PORT_ATTR_nportid		0x00008000
1526 #define LPFC_FDMI_SMART_ATTR_service		0x00010000 /* Vendor specific */
1527 #define LPFC_FDMI_SMART_ATTR_guid		0x00020000 /* Vendor specific */
1528 #define LPFC_FDMI_SMART_ATTR_version		0x00040000 /* Vendor specific */
1529 #define LPFC_FDMI_SMART_ATTR_model		0x00080000 /* Vendor specific */
1530 #define LPFC_FDMI_SMART_ATTR_port_info		0x00100000 /* Vendor specific */
1531 #define LPFC_FDMI_SMART_ATTR_qos		0x00200000 /* Vendor specific */
1532 #define LPFC_FDMI_SMART_ATTR_security		0x00400000 /* Vendor specific */
1533 
1534 /* Bit mask for FDMI-1 defined PORT attributes */
1535 #define LPFC_FDMI1_PORT_ATTR			0x0000003f
1536 
1537 /* Bit mask for FDMI-2 defined PORT attributes */
1538 #define LPFC_FDMI2_PORT_ATTR			0x0000ffff
1539 
1540 /* Bit mask for Smart SAN defined PORT attributes */
1541 #define LPFC_FDMI2_SMART_ATTR			0x007fffff
1542 
1543 /* Defines for PORT port state attribute */
1544 #define LPFC_FDMI_PORTSTATE_UNKNOWN	1
1545 #define LPFC_FDMI_PORTSTATE_ONLINE	2
1546 
1547 /* Defines for PORT port type attribute */
1548 #define LPFC_FDMI_PORTTYPE_UNKNOWN	0
1549 #define LPFC_FDMI_PORTTYPE_NPORT	1
1550 #define LPFC_FDMI_PORTTYPE_NLPORT	2
1551 
1552 /*
1553  *  Begin HBA configuration parameters.
1554  *  The PCI configuration register BAR assignments are:
1555  *  BAR0, offset 0x10 - SLIM base memory address
1556  *  BAR1, offset 0x14 - SLIM base memory high address
1557  *  BAR2, offset 0x18 - REGISTER base memory address
1558  *  BAR3, offset 0x1c - REGISTER base memory high address
1559  *  BAR4, offset 0x20 - BIU I/O registers
1560  *  BAR5, offset 0x24 - REGISTER base io high address
1561  */
1562 
1563 /* Number of rings currently used and available. */
1564 #define MAX_SLI3_CONFIGURED_RINGS     3
1565 #define MAX_SLI3_RINGS                4
1566 
1567 /* IOCB / Mailbox is owned by FireFly */
1568 #define OWN_CHIP        1
1569 
1570 /* IOCB / Mailbox is owned by Host */
1571 #define OWN_HOST        0
1572 
1573 /* Number of 4-byte words in an IOCB. */
1574 #define IOCB_WORD_SZ    8
1575 
1576 /* network headers for Dfctl field */
1577 #define FC_NET_HDR      0x20
1578 
1579 /* Start FireFly Register definitions */
1580 #define PCI_VENDOR_ID_EMULEX        0x10df
1581 #define PCI_DEVICE_ID_FIREFLY       0x1ae5
1582 #define PCI_DEVICE_ID_PROTEUS_VF    0xe100
1583 #define PCI_DEVICE_ID_BALIUS        0xe131
1584 #define PCI_DEVICE_ID_PROTEUS_PF    0xe180
1585 #define PCI_DEVICE_ID_LANCER_FC     0xe200
1586 #define PCI_DEVICE_ID_LANCER_FC_VF  0xe208
1587 #define PCI_DEVICE_ID_LANCER_FCOE   0xe260
1588 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1589 #define PCI_DEVICE_ID_LANCER_G6_FC  0xe300
1590 #define PCI_DEVICE_ID_LANCER_G7_FC  0xf400
1591 #define PCI_DEVICE_ID_SAT_SMB       0xf011
1592 #define PCI_DEVICE_ID_SAT_MID       0xf015
1593 #define PCI_DEVICE_ID_RFLY          0xf095
1594 #define PCI_DEVICE_ID_PFLY          0xf098
1595 #define PCI_DEVICE_ID_LP101         0xf0a1
1596 #define PCI_DEVICE_ID_TFLY          0xf0a5
1597 #define PCI_DEVICE_ID_BSMB          0xf0d1
1598 #define PCI_DEVICE_ID_BMID          0xf0d5
1599 #define PCI_DEVICE_ID_ZSMB          0xf0e1
1600 #define PCI_DEVICE_ID_ZMID          0xf0e5
1601 #define PCI_DEVICE_ID_NEPTUNE       0xf0f5
1602 #define PCI_DEVICE_ID_NEPTUNE_SCSP  0xf0f6
1603 #define PCI_DEVICE_ID_NEPTUNE_DCSP  0xf0f7
1604 #define PCI_DEVICE_ID_SAT           0xf100
1605 #define PCI_DEVICE_ID_SAT_SCSP      0xf111
1606 #define PCI_DEVICE_ID_SAT_DCSP      0xf112
1607 #define PCI_DEVICE_ID_FALCON        0xf180
1608 #define PCI_DEVICE_ID_SUPERFLY      0xf700
1609 #define PCI_DEVICE_ID_DRAGONFLY     0xf800
1610 #define PCI_DEVICE_ID_CENTAUR       0xf900
1611 #define PCI_DEVICE_ID_PEGASUS       0xf980
1612 #define PCI_DEVICE_ID_THOR          0xfa00
1613 #define PCI_DEVICE_ID_VIPER         0xfb00
1614 #define PCI_DEVICE_ID_LP10000S      0xfc00
1615 #define PCI_DEVICE_ID_LP11000S      0xfc10
1616 #define PCI_DEVICE_ID_LPE11000S     0xfc20
1617 #define PCI_DEVICE_ID_SAT_S         0xfc40
1618 #define PCI_DEVICE_ID_PROTEUS_S     0xfc50
1619 #define PCI_DEVICE_ID_HELIOS        0xfd00
1620 #define PCI_DEVICE_ID_HELIOS_SCSP   0xfd11
1621 #define PCI_DEVICE_ID_HELIOS_DCSP   0xfd12
1622 #define PCI_DEVICE_ID_ZEPHYR        0xfe00
1623 #define PCI_DEVICE_ID_HORNET        0xfe05
1624 #define PCI_DEVICE_ID_ZEPHYR_SCSP   0xfe11
1625 #define PCI_DEVICE_ID_ZEPHYR_DCSP   0xfe12
1626 #define PCI_VENDOR_ID_SERVERENGINE  0x19a2
1627 #define PCI_DEVICE_ID_TIGERSHARK    0x0704
1628 #define PCI_DEVICE_ID_TOMCAT        0x0714
1629 #define PCI_DEVICE_ID_SKYHAWK       0x0724
1630 #define PCI_DEVICE_ID_SKYHAWK_VF    0x072c
1631 
1632 #define JEDEC_ID_ADDRESS            0x0080001c
1633 #define FIREFLY_JEDEC_ID            0x1ACC
1634 #define SUPERFLY_JEDEC_ID           0x0020
1635 #define DRAGONFLY_JEDEC_ID          0x0021
1636 #define DRAGONFLY_V2_JEDEC_ID       0x0025
1637 #define CENTAUR_2G_JEDEC_ID         0x0026
1638 #define CENTAUR_1G_JEDEC_ID         0x0028
1639 #define PEGASUS_ORION_JEDEC_ID      0x0036
1640 #define PEGASUS_JEDEC_ID            0x0038
1641 #define THOR_JEDEC_ID               0x0012
1642 #define HELIOS_JEDEC_ID             0x0364
1643 #define ZEPHYR_JEDEC_ID             0x0577
1644 #define VIPER_JEDEC_ID              0x4838
1645 #define SATURN_JEDEC_ID             0x1004
1646 #define HORNET_JDEC_ID              0x2057706D
1647 
1648 #define JEDEC_ID_MASK               0x0FFFF000
1649 #define JEDEC_ID_SHIFT              12
1650 #define FC_JEDEC_ID(id)             ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1651 
1652 typedef struct {		/* FireFly BIU registers */
1653 	uint32_t hostAtt;	/* See definitions for Host Attention
1654 				   register */
1655 	uint32_t chipAtt;	/* See definitions for Chip Attention
1656 				   register */
1657 	uint32_t hostStatus;	/* See definitions for Host Status register */
1658 	uint32_t hostControl;	/* See definitions for Host Control register */
1659 	uint32_t buiConfig;	/* See definitions for BIU configuration
1660 				   register */
1661 } FF_REGS;
1662 
1663 /* IO Register size in bytes */
1664 #define FF_REG_AREA_SIZE       256
1665 
1666 /* Host Attention Register */
1667 
1668 #define HA_REG_OFFSET  0	/* Byte offset from register base address */
1669 
1670 #define HA_R0RE_REQ    0x00000001	/* Bit  0 */
1671 #define HA_R0CE_RSP    0x00000002	/* Bit  1 */
1672 #define HA_R0ATT       0x00000008	/* Bit  3 */
1673 #define HA_R1RE_REQ    0x00000010	/* Bit  4 */
1674 #define HA_R1CE_RSP    0x00000020	/* Bit  5 */
1675 #define HA_R1ATT       0x00000080	/* Bit  7 */
1676 #define HA_R2RE_REQ    0x00000100	/* Bit  8 */
1677 #define HA_R2CE_RSP    0x00000200	/* Bit  9 */
1678 #define HA_R2ATT       0x00000800	/* Bit 11 */
1679 #define HA_R3RE_REQ    0x00001000	/* Bit 12 */
1680 #define HA_R3CE_RSP    0x00002000	/* Bit 13 */
1681 #define HA_R3ATT       0x00008000	/* Bit 15 */
1682 #define HA_LATT        0x20000000	/* Bit 29 */
1683 #define HA_MBATT       0x40000000	/* Bit 30 */
1684 #define HA_ERATT       0x80000000	/* Bit 31 */
1685 
1686 #define HA_RXRE_REQ    0x00000001	/* Bit  0 */
1687 #define HA_RXCE_RSP    0x00000002	/* Bit  1 */
1688 #define HA_RXATT       0x00000008	/* Bit  3 */
1689 #define HA_RXMASK      0x0000000f
1690 
1691 #define HA_R0_CLR_MSK	(HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1692 #define HA_R1_CLR_MSK	(HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1693 #define HA_R2_CLR_MSK	(HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1694 #define HA_R3_CLR_MSK	(HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1695 
1696 #define HA_R0_POS	3
1697 #define HA_R1_POS	7
1698 #define HA_R2_POS	11
1699 #define HA_R3_POS	15
1700 #define HA_LE_POS	29
1701 #define HA_MB_POS	30
1702 #define HA_ER_POS	31
1703 /* Chip Attention Register */
1704 
1705 #define CA_REG_OFFSET  4	/* Byte offset from register base address */
1706 
1707 #define CA_R0CE_REQ    0x00000001	/* Bit  0 */
1708 #define CA_R0RE_RSP    0x00000002	/* Bit  1 */
1709 #define CA_R0ATT       0x00000008	/* Bit  3 */
1710 #define CA_R1CE_REQ    0x00000010	/* Bit  4 */
1711 #define CA_R1RE_RSP    0x00000020	/* Bit  5 */
1712 #define CA_R1ATT       0x00000080	/* Bit  7 */
1713 #define CA_R2CE_REQ    0x00000100	/* Bit  8 */
1714 #define CA_R2RE_RSP    0x00000200	/* Bit  9 */
1715 #define CA_R2ATT       0x00000800	/* Bit 11 */
1716 #define CA_R3CE_REQ    0x00001000	/* Bit 12 */
1717 #define CA_R3RE_RSP    0x00002000	/* Bit 13 */
1718 #define CA_R3ATT       0x00008000	/* Bit 15 */
1719 #define CA_MBATT       0x40000000	/* Bit 30 */
1720 
1721 /* Host Status Register */
1722 
1723 #define HS_REG_OFFSET  8	/* Byte offset from register base address */
1724 
1725 #define HS_MBRDY       0x00400000	/* Bit 22 */
1726 #define HS_FFRDY       0x00800000	/* Bit 23 */
1727 #define HS_FFER8       0x01000000	/* Bit 24 */
1728 #define HS_FFER7       0x02000000	/* Bit 25 */
1729 #define HS_FFER6       0x04000000	/* Bit 26 */
1730 #define HS_FFER5       0x08000000	/* Bit 27 */
1731 #define HS_FFER4       0x10000000	/* Bit 28 */
1732 #define HS_FFER3       0x20000000	/* Bit 29 */
1733 #define HS_FFER2       0x40000000	/* Bit 30 */
1734 #define HS_FFER1       0x80000000	/* Bit 31 */
1735 #define HS_CRIT_TEMP   0x00000100	/* Bit 8  */
1736 #define HS_FFERM       0xFF000100	/* Mask for error bits 31:24 and 8 */
1737 #define UNPLUG_ERR     0x00000001	/* Indicate pci hot unplug */
1738 /* Host Control Register */
1739 
1740 #define HC_REG_OFFSET  12	/* Byte offset from register base address */
1741 
1742 #define HC_MBINT_ENA   0x00000001	/* Bit  0 */
1743 #define HC_R0INT_ENA   0x00000002	/* Bit  1 */
1744 #define HC_R1INT_ENA   0x00000004	/* Bit  2 */
1745 #define HC_R2INT_ENA   0x00000008	/* Bit  3 */
1746 #define HC_R3INT_ENA   0x00000010	/* Bit  4 */
1747 #define HC_INITHBI     0x02000000	/* Bit 25 */
1748 #define HC_INITMB      0x04000000	/* Bit 26 */
1749 #define HC_INITFF      0x08000000	/* Bit 27 */
1750 #define HC_LAINT_ENA   0x20000000	/* Bit 29 */
1751 #define HC_ERINT_ENA   0x80000000	/* Bit 31 */
1752 
1753 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1754 #define MSIX_DFLT_ID	0
1755 #define MSIX_RNG0_ID	0
1756 #define MSIX_RNG1_ID	1
1757 #define MSIX_RNG2_ID	2
1758 #define MSIX_RNG3_ID	3
1759 
1760 #define MSIX_LINK_ID	4
1761 #define MSIX_MBOX_ID	5
1762 
1763 #define MSIX_SPARE0_ID	6
1764 #define MSIX_SPARE1_ID	7
1765 
1766 /* Mailbox Commands */
1767 #define MBX_SHUTDOWN        0x00	/* terminate testing */
1768 #define MBX_LOAD_SM         0x01
1769 #define MBX_READ_NV         0x02
1770 #define MBX_WRITE_NV        0x03
1771 #define MBX_RUN_BIU_DIAG    0x04
1772 #define MBX_INIT_LINK       0x05
1773 #define MBX_DOWN_LINK       0x06
1774 #define MBX_CONFIG_LINK     0x07
1775 #define MBX_CONFIG_RING     0x09
1776 #define MBX_RESET_RING      0x0A
1777 #define MBX_READ_CONFIG     0x0B
1778 #define MBX_READ_RCONFIG    0x0C
1779 #define MBX_READ_SPARM      0x0D
1780 #define MBX_READ_STATUS     0x0E
1781 #define MBX_READ_RPI        0x0F
1782 #define MBX_READ_XRI        0x10
1783 #define MBX_READ_REV        0x11
1784 #define MBX_READ_LNK_STAT   0x12
1785 #define MBX_REG_LOGIN       0x13
1786 #define MBX_UNREG_LOGIN     0x14
1787 #define MBX_CLEAR_LA        0x16
1788 #define MBX_DUMP_MEMORY     0x17
1789 #define MBX_DUMP_CONTEXT    0x18
1790 #define MBX_RUN_DIAGS       0x19
1791 #define MBX_RESTART         0x1A
1792 #define MBX_UPDATE_CFG      0x1B
1793 #define MBX_DOWN_LOAD       0x1C
1794 #define MBX_DEL_LD_ENTRY    0x1D
1795 #define MBX_RUN_PROGRAM     0x1E
1796 #define MBX_SET_MASK        0x20
1797 #define MBX_SET_VARIABLE    0x21
1798 #define MBX_UNREG_D_ID      0x23
1799 #define MBX_KILL_BOARD      0x24
1800 #define MBX_CONFIG_FARP     0x25
1801 #define MBX_BEACON          0x2A
1802 #define MBX_CONFIG_MSI      0x30
1803 #define MBX_HEARTBEAT       0x31
1804 #define MBX_WRITE_VPARMS    0x32
1805 #define MBX_ASYNCEVT_ENABLE 0x33
1806 #define MBX_READ_EVENT_LOG_STATUS 0x37
1807 #define MBX_READ_EVENT_LOG  0x38
1808 #define MBX_WRITE_EVENT_LOG 0x39
1809 
1810 #define MBX_PORT_CAPABILITIES 0x3B
1811 #define MBX_PORT_IOV_CONTROL 0x3C
1812 
1813 #define MBX_CONFIG_HBQ	    0x7C
1814 #define MBX_LOAD_AREA       0x81
1815 #define MBX_RUN_BIU_DIAG64  0x84
1816 #define MBX_CONFIG_PORT     0x88
1817 #define MBX_READ_SPARM64    0x8D
1818 #define MBX_READ_RPI64      0x8F
1819 #define MBX_REG_LOGIN64     0x93
1820 #define MBX_READ_TOPOLOGY   0x95
1821 #define MBX_REG_VPI	    0x96
1822 #define MBX_UNREG_VPI	    0x97
1823 
1824 #define MBX_WRITE_WWN       0x98
1825 #define MBX_SET_DEBUG       0x99
1826 #define MBX_LOAD_EXP_ROM    0x9C
1827 #define MBX_SLI4_CONFIG	    0x9B
1828 #define MBX_SLI4_REQ_FTRS   0x9D
1829 #define MBX_MAX_CMDS        0x9E
1830 #define MBX_RESUME_RPI      0x9E
1831 #define MBX_SLI2_CMD_MASK   0x80
1832 #define MBX_REG_VFI         0x9F
1833 #define MBX_REG_FCFI        0xA0
1834 #define MBX_UNREG_VFI       0xA1
1835 #define MBX_UNREG_FCFI	    0xA2
1836 #define MBX_INIT_VFI        0xA3
1837 #define MBX_INIT_VPI        0xA4
1838 #define MBX_ACCESS_VDATA    0xA5
1839 #define MBX_REG_FCFI_MRQ    0xAF
1840 
1841 #define MBX_AUTH_PORT       0xF8
1842 #define MBX_SECURITY_MGMT   0xF9
1843 
1844 /* IOCB Commands */
1845 
1846 #define CMD_RCV_SEQUENCE_CX     0x01
1847 #define CMD_XMIT_SEQUENCE_CR    0x02
1848 #define CMD_XMIT_SEQUENCE_CX    0x03
1849 #define CMD_XMIT_BCAST_CN       0x04
1850 #define CMD_XMIT_BCAST_CX       0x05
1851 #define CMD_QUE_RING_BUF_CN     0x06
1852 #define CMD_QUE_XRI_BUF_CX      0x07
1853 #define CMD_IOCB_CONTINUE_CN    0x08
1854 #define CMD_RET_XRI_BUF_CX      0x09
1855 #define CMD_ELS_REQUEST_CR      0x0A
1856 #define CMD_ELS_REQUEST_CX      0x0B
1857 #define CMD_RCV_ELS_REQ_CX      0x0D
1858 #define CMD_ABORT_XRI_CN        0x0E
1859 #define CMD_ABORT_XRI_CX        0x0F
1860 #define CMD_CLOSE_XRI_CN        0x10
1861 #define CMD_CLOSE_XRI_CX        0x11
1862 #define CMD_CREATE_XRI_CR       0x12
1863 #define CMD_CREATE_XRI_CX       0x13
1864 #define CMD_GET_RPI_CN          0x14
1865 #define CMD_XMIT_ELS_RSP_CX     0x15
1866 #define CMD_GET_RPI_CR          0x16
1867 #define CMD_XRI_ABORTED_CX      0x17
1868 #define CMD_FCP_IWRITE_CR       0x18
1869 #define CMD_FCP_IWRITE_CX       0x19
1870 #define CMD_FCP_IREAD_CR        0x1A
1871 #define CMD_FCP_IREAD_CX        0x1B
1872 #define CMD_FCP_ICMND_CR        0x1C
1873 #define CMD_FCP_ICMND_CX        0x1D
1874 #define CMD_FCP_TSEND_CX        0x1F
1875 #define CMD_FCP_TRECEIVE_CX     0x21
1876 #define CMD_FCP_TRSP_CX	        0x23
1877 #define CMD_FCP_AUTO_TRSP_CX    0x29
1878 
1879 #define CMD_ADAPTER_MSG         0x20
1880 #define CMD_ADAPTER_DUMP        0x22
1881 
1882 /*  SLI_2 IOCB Command Set */
1883 
1884 #define CMD_ASYNC_STATUS        0x7C
1885 #define CMD_RCV_SEQUENCE64_CX   0x81
1886 #define CMD_XMIT_SEQUENCE64_CR  0x82
1887 #define CMD_XMIT_SEQUENCE64_CX  0x83
1888 #define CMD_XMIT_BCAST64_CN     0x84
1889 #define CMD_XMIT_BCAST64_CX     0x85
1890 #define CMD_QUE_RING_BUF64_CN   0x86
1891 #define CMD_QUE_XRI_BUF64_CX    0x87
1892 #define CMD_IOCB_CONTINUE64_CN  0x88
1893 #define CMD_RET_XRI_BUF64_CX    0x89
1894 #define CMD_ELS_REQUEST64_CR    0x8A
1895 #define CMD_ELS_REQUEST64_CX    0x8B
1896 #define CMD_ABORT_MXRI64_CN     0x8C
1897 #define CMD_RCV_ELS_REQ64_CX    0x8D
1898 #define CMD_XMIT_ELS_RSP64_CX   0x95
1899 #define CMD_XMIT_BLS_RSP64_CX   0x97
1900 #define CMD_FCP_IWRITE64_CR     0x98
1901 #define CMD_FCP_IWRITE64_CX     0x99
1902 #define CMD_FCP_IREAD64_CR      0x9A
1903 #define CMD_FCP_IREAD64_CX      0x9B
1904 #define CMD_FCP_ICMND64_CR      0x9C
1905 #define CMD_FCP_ICMND64_CX      0x9D
1906 #define CMD_FCP_TSEND64_CX      0x9F
1907 #define CMD_FCP_TRECEIVE64_CX   0xA1
1908 #define CMD_FCP_TRSP64_CX       0xA3
1909 
1910 #define CMD_QUE_XRI64_CX	0xB3
1911 #define CMD_IOCB_RCV_SEQ64_CX	0xB5
1912 #define CMD_IOCB_RCV_ELS64_CX	0xB7
1913 #define CMD_IOCB_RET_XRI64_CX	0xB9
1914 #define CMD_IOCB_RCV_CONT64_CX	0xBB
1915 
1916 #define CMD_GEN_REQUEST64_CR    0xC2
1917 #define CMD_GEN_REQUEST64_CX    0xC3
1918 
1919 /* Unhandled SLI-3 Commands */
1920 #define CMD_IOCB_XMIT_MSEQ64_CR		0xB0
1921 #define CMD_IOCB_XMIT_MSEQ64_CX		0xB1
1922 #define CMD_IOCB_RCV_SEQ_LIST64_CX	0xC1
1923 #define CMD_IOCB_RCV_ELS_LIST64_CX	0xCD
1924 #define CMD_IOCB_CLOSE_EXTENDED_CN	0xB6
1925 #define CMD_IOCB_ABORT_EXTENDED_CN	0xBA
1926 #define CMD_IOCB_RET_HBQE64_CN		0xCA
1927 #define CMD_IOCB_FCP_IBIDIR64_CR	0xAC
1928 #define CMD_IOCB_FCP_IBIDIR64_CX	0xAD
1929 #define CMD_IOCB_FCP_ITASKMGT64_CX	0xAF
1930 #define CMD_IOCB_LOGENTRY_CN		0x94
1931 #define CMD_IOCB_LOGENTRY_ASYNC_CN	0x96
1932 
1933 /* Data Security SLI Commands */
1934 #define DSSCMD_IWRITE64_CR		0xF8
1935 #define DSSCMD_IWRITE64_CX		0xF9
1936 #define DSSCMD_IREAD64_CR		0xFA
1937 #define DSSCMD_IREAD64_CX		0xFB
1938 
1939 #define CMD_MAX_IOCB_CMD        0xFB
1940 #define CMD_IOCB_MASK           0xff
1941 
1942 #define MAX_MSG_DATA            28	/* max msg data in CMD_ADAPTER_MSG
1943 					   iocb */
1944 #define LPFC_MAX_ADPTMSG         32	/* max msg data */
1945 /*
1946  *  Define Status
1947  */
1948 #define MBX_SUCCESS                 0
1949 #define MBXERR_NUM_RINGS            1
1950 #define MBXERR_NUM_IOCBS            2
1951 #define MBXERR_IOCBS_EXCEEDED       3
1952 #define MBXERR_BAD_RING_NUMBER      4
1953 #define MBXERR_MASK_ENTRIES_RANGE   5
1954 #define MBXERR_MASKS_EXCEEDED       6
1955 #define MBXERR_BAD_PROFILE          7
1956 #define MBXERR_BAD_DEF_CLASS        8
1957 #define MBXERR_BAD_MAX_RESPONDER    9
1958 #define MBXERR_BAD_MAX_ORIGINATOR   10
1959 #define MBXERR_RPI_REGISTERED       11
1960 #define MBXERR_RPI_FULL             12
1961 #define MBXERR_NO_RESOURCES         13
1962 #define MBXERR_BAD_RCV_LENGTH       14
1963 #define MBXERR_DMA_ERROR            15
1964 #define MBXERR_ERROR                16
1965 #define MBXERR_LINK_DOWN            0x33
1966 #define MBXERR_SEC_NO_PERMISSION    0xF02
1967 #define MBX_NOT_FINISHED            255
1968 
1969 #define MBX_BUSY                   0xffffff /* Attempted cmd to busy Mailbox */
1970 #define MBX_TIMEOUT                0xfffffe /* time-out expired waiting for */
1971 
1972 #define TEMPERATURE_OFFSET 0xB0	/* Slim offset for critical temperature event */
1973 
1974 /*
1975  * return code Fail
1976  */
1977 #define FAILURE 1
1978 
1979 /*
1980  *    Begin Structure Definitions for Mailbox Commands
1981  */
1982 
1983 typedef struct {
1984 #ifdef __BIG_ENDIAN_BITFIELD
1985 	uint8_t tval;
1986 	uint8_t tmask;
1987 	uint8_t rval;
1988 	uint8_t rmask;
1989 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1990 	uint8_t rmask;
1991 	uint8_t rval;
1992 	uint8_t tmask;
1993 	uint8_t tval;
1994 #endif
1995 } RR_REG;
1996 
1997 struct ulp_bde {
1998 	uint32_t bdeAddress;
1999 #ifdef __BIG_ENDIAN_BITFIELD
2000 	uint32_t bdeReserved:4;
2001 	uint32_t bdeAddrHigh:4;
2002 	uint32_t bdeSize:24;
2003 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2004 	uint32_t bdeSize:24;
2005 	uint32_t bdeAddrHigh:4;
2006 	uint32_t bdeReserved:4;
2007 #endif
2008 };
2009 
2010 typedef struct ULP_BDL {	/* SLI-2 */
2011 #ifdef __BIG_ENDIAN_BITFIELD
2012 	uint32_t bdeFlags:8;	/* BDL Flags */
2013 	uint32_t bdeSize:24;	/* Size of BDL array in host memory (bytes) */
2014 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2015 	uint32_t bdeSize:24;	/* Size of BDL array in host memory (bytes) */
2016 	uint32_t bdeFlags:8;	/* BDL Flags */
2017 #endif
2018 
2019 	uint32_t addrLow;	/* Address 0:31 */
2020 	uint32_t addrHigh;	/* Address 32:63 */
2021 	uint32_t ulpIoTag32;	/* Can be used for 32 bit I/O Tag */
2022 } ULP_BDL;
2023 
2024 /*
2025  * BlockGuard Definitions
2026  */
2027 
2028 enum lpfc_protgrp_type {
2029 	LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors                  */
2030 	LPFC_PG_TYPE_NO_DIF,	  /* no DIF data pointed to by prot grp       */
2031 	LPFC_PG_TYPE_EMBD_DIF,	  /* DIF is embedded (inline) with data       */
2032 	LPFC_PG_TYPE_DIF_BUF	  /* DIF has its own scatter/gather list      */
2033 };
2034 
2035 /* PDE Descriptors */
2036 #define LPFC_PDE5_DESCRIPTOR		0x85
2037 #define LPFC_PDE6_DESCRIPTOR		0x86
2038 #define LPFC_PDE7_DESCRIPTOR		0x87
2039 
2040 /* BlockGuard Opcodes */
2041 #define BG_OP_IN_NODIF_OUT_CRC		0x0
2042 #define	BG_OP_IN_CRC_OUT_NODIF		0x1
2043 #define	BG_OP_IN_NODIF_OUT_CSUM		0x2
2044 #define	BG_OP_IN_CSUM_OUT_NODIF		0x3
2045 #define	BG_OP_IN_CRC_OUT_CRC		0x4
2046 #define	BG_OP_IN_CSUM_OUT_CSUM		0x5
2047 #define	BG_OP_IN_CRC_OUT_CSUM		0x6
2048 #define	BG_OP_IN_CSUM_OUT_CRC		0x7
2049 #define	BG_OP_RAW_MODE			0x8
2050 
2051 struct lpfc_pde5 {
2052 	uint32_t word0;
2053 #define pde5_type_SHIFT		24
2054 #define pde5_type_MASK		0x000000ff
2055 #define pde5_type_WORD		word0
2056 #define pde5_rsvd0_SHIFT	0
2057 #define pde5_rsvd0_MASK		0x00ffffff
2058 #define pde5_rsvd0_WORD		word0
2059 	uint32_t reftag;	/* Reference Tag Value			*/
2060 	uint32_t reftagtr;	/* Reference Tag Translation Value 	*/
2061 };
2062 
2063 struct lpfc_pde6 {
2064 	uint32_t word0;
2065 #define pde6_type_SHIFT		24
2066 #define pde6_type_MASK		0x000000ff
2067 #define pde6_type_WORD		word0
2068 #define pde6_rsvd0_SHIFT	0
2069 #define pde6_rsvd0_MASK		0x00ffffff
2070 #define pde6_rsvd0_WORD		word0
2071 	uint32_t word1;
2072 #define pde6_rsvd1_SHIFT	26
2073 #define pde6_rsvd1_MASK		0x0000003f
2074 #define pde6_rsvd1_WORD		word1
2075 #define pde6_na_SHIFT		25
2076 #define pde6_na_MASK		0x00000001
2077 #define pde6_na_WORD		word1
2078 #define pde6_rsvd2_SHIFT	16
2079 #define pde6_rsvd2_MASK		0x000001FF
2080 #define pde6_rsvd2_WORD		word1
2081 #define pde6_apptagtr_SHIFT	0
2082 #define pde6_apptagtr_MASK	0x0000ffff
2083 #define pde6_apptagtr_WORD	word1
2084 	uint32_t word2;
2085 #define pde6_optx_SHIFT		28
2086 #define pde6_optx_MASK		0x0000000f
2087 #define pde6_optx_WORD		word2
2088 #define pde6_oprx_SHIFT		24
2089 #define pde6_oprx_MASK		0x0000000f
2090 #define pde6_oprx_WORD		word2
2091 #define pde6_nr_SHIFT		23
2092 #define pde6_nr_MASK		0x00000001
2093 #define pde6_nr_WORD		word2
2094 #define pde6_ce_SHIFT		22
2095 #define pde6_ce_MASK		0x00000001
2096 #define pde6_ce_WORD		word2
2097 #define pde6_re_SHIFT		21
2098 #define pde6_re_MASK		0x00000001
2099 #define pde6_re_WORD		word2
2100 #define pde6_ae_SHIFT		20
2101 #define pde6_ae_MASK		0x00000001
2102 #define pde6_ae_WORD		word2
2103 #define pde6_ai_SHIFT		19
2104 #define pde6_ai_MASK		0x00000001
2105 #define pde6_ai_WORD		word2
2106 #define pde6_bs_SHIFT		16
2107 #define pde6_bs_MASK		0x00000007
2108 #define pde6_bs_WORD		word2
2109 #define pde6_apptagval_SHIFT	0
2110 #define pde6_apptagval_MASK	0x0000ffff
2111 #define pde6_apptagval_WORD	word2
2112 };
2113 
2114 struct lpfc_pde7 {
2115 	uint32_t word0;
2116 #define pde7_type_SHIFT		24
2117 #define pde7_type_MASK		0x000000ff
2118 #define pde7_type_WORD		word0
2119 #define pde7_rsvd0_SHIFT	0
2120 #define pde7_rsvd0_MASK		0x00ffffff
2121 #define pde7_rsvd0_WORD		word0
2122 	uint32_t addrHigh;
2123 	uint32_t addrLow;
2124 };
2125 
2126 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
2127 
2128 typedef struct {
2129 #ifdef __BIG_ENDIAN_BITFIELD
2130 	uint32_t rsvd2:25;
2131 	uint32_t acknowledgment:1;
2132 	uint32_t version:1;
2133 	uint32_t erase_or_prog:1;
2134 	uint32_t update_flash:1;
2135 	uint32_t update_ram:1;
2136 	uint32_t method:1;
2137 	uint32_t load_cmplt:1;
2138 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2139 	uint32_t load_cmplt:1;
2140 	uint32_t method:1;
2141 	uint32_t update_ram:1;
2142 	uint32_t update_flash:1;
2143 	uint32_t erase_or_prog:1;
2144 	uint32_t version:1;
2145 	uint32_t acknowledgment:1;
2146 	uint32_t rsvd2:25;
2147 #endif
2148 
2149 	uint32_t dl_to_adr_low;
2150 	uint32_t dl_to_adr_high;
2151 	uint32_t dl_len;
2152 	union {
2153 		uint32_t dl_from_mbx_offset;
2154 		struct ulp_bde dl_from_bde;
2155 		struct ulp_bde64 dl_from_bde64;
2156 	} un;
2157 
2158 } LOAD_SM_VAR;
2159 
2160 /* Structure for MB Command READ_NVPARM (02) */
2161 
2162 typedef struct {
2163 	uint32_t rsvd1[3];	/* Read as all one's */
2164 	uint32_t rsvd2;		/* Read as all zero's */
2165 	uint32_t portname[2];	/* N_PORT name */
2166 	uint32_t nodename[2];	/* NODE name */
2167 
2168 #ifdef __BIG_ENDIAN_BITFIELD
2169 	uint32_t pref_DID:24;
2170 	uint32_t hardAL_PA:8;
2171 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2172 	uint32_t hardAL_PA:8;
2173 	uint32_t pref_DID:24;
2174 #endif
2175 
2176 	uint32_t rsvd3[21];	/* Read as all one's */
2177 } READ_NV_VAR;
2178 
2179 /* Structure for MB Command WRITE_NVPARMS (03) */
2180 
2181 typedef struct {
2182 	uint32_t rsvd1[3];	/* Must be all one's */
2183 	uint32_t rsvd2;		/* Must be all zero's */
2184 	uint32_t portname[2];	/* N_PORT name */
2185 	uint32_t nodename[2];	/* NODE name */
2186 
2187 #ifdef __BIG_ENDIAN_BITFIELD
2188 	uint32_t pref_DID:24;
2189 	uint32_t hardAL_PA:8;
2190 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2191 	uint32_t hardAL_PA:8;
2192 	uint32_t pref_DID:24;
2193 #endif
2194 
2195 	uint32_t rsvd3[21];	/* Must be all one's */
2196 } WRITE_NV_VAR;
2197 
2198 /* Structure for MB Command RUN_BIU_DIAG (04) */
2199 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2200 
2201 typedef struct {
2202 	uint32_t rsvd1;
2203 	union {
2204 		struct {
2205 			struct ulp_bde xmit_bde;
2206 			struct ulp_bde rcv_bde;
2207 		} s1;
2208 		struct {
2209 			struct ulp_bde64 xmit_bde64;
2210 			struct ulp_bde64 rcv_bde64;
2211 		} s2;
2212 	} un;
2213 } BIU_DIAG_VAR;
2214 
2215 /* Structure for MB command READ_EVENT_LOG (0x38) */
2216 struct READ_EVENT_LOG_VAR {
2217 	uint32_t word1;
2218 #define lpfc_event_log_SHIFT	29
2219 #define lpfc_event_log_MASK	0x00000001
2220 #define lpfc_event_log_WORD	word1
2221 #define USE_MAILBOX_RESPONSE	1
2222 	uint32_t offset;
2223 	struct ulp_bde64 rcv_bde64;
2224 };
2225 
2226 /* Structure for MB Command INIT_LINK (05) */
2227 
2228 typedef struct {
2229 #ifdef __BIG_ENDIAN_BITFIELD
2230 	uint32_t rsvd1:24;
2231 	uint32_t lipsr_AL_PA:8;	/* AL_PA to issue Lip Selective Reset to */
2232 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2233 	uint32_t lipsr_AL_PA:8;	/* AL_PA to issue Lip Selective Reset to */
2234 	uint32_t rsvd1:24;
2235 #endif
2236 
2237 #ifdef __BIG_ENDIAN_BITFIELD
2238 	uint8_t fabric_AL_PA;	/* If using a Fabric Assigned AL_PA */
2239 	uint8_t rsvd2;
2240 	uint16_t link_flags;
2241 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2242 	uint16_t link_flags;
2243 	uint8_t rsvd2;
2244 	uint8_t fabric_AL_PA;	/* If using a Fabric Assigned AL_PA */
2245 #endif
2246 
2247 #define FLAGS_TOPOLOGY_MODE_LOOP_PT  0x00 /* Attempt loop then pt-pt */
2248 #define FLAGS_LOCAL_LB               0x01 /* link_flags (=1) ENDEC loopback */
2249 #define FLAGS_TOPOLOGY_MODE_PT_PT    0x02 /* Attempt pt-pt only */
2250 #define FLAGS_TOPOLOGY_MODE_LOOP     0x04 /* Attempt loop only */
2251 #define FLAGS_TOPOLOGY_MODE_PT_LOOP  0x06 /* Attempt pt-pt then loop */
2252 #define	FLAGS_UNREG_LOGIN_ALL	     0x08 /* UNREG_LOGIN all on link down */
2253 #define FLAGS_LIRP_LILP              0x80 /* LIRP / LILP is disabled */
2254 
2255 #define FLAGS_TOPOLOGY_FAILOVER      0x0400	/* Bit 10 */
2256 #define FLAGS_LINK_SPEED             0x0800	/* Bit 11 */
2257 #define FLAGS_IMED_ABORT             0x04000	/* Bit 14 */
2258 
2259 	uint32_t link_speed;
2260 #define LINK_SPEED_AUTO 0x0     /* Auto selection */
2261 #define LINK_SPEED_1G   0x1     /* 1 Gigabaud */
2262 #define LINK_SPEED_2G   0x2     /* 2 Gigabaud */
2263 #define LINK_SPEED_4G   0x4     /* 4 Gigabaud */
2264 #define LINK_SPEED_8G   0x8     /* 8 Gigabaud */
2265 #define LINK_SPEED_10G  0x10    /* 10 Gigabaud */
2266 #define LINK_SPEED_16G  0x11    /* 16 Gigabaud */
2267 #define LINK_SPEED_32G  0x14    /* 32 Gigabaud */
2268 #define LINK_SPEED_64G  0x17    /* 64 Gigabaud */
2269 #define LINK_SPEED_128G 0x1A    /* 128 Gigabaud */
2270 #define LINK_SPEED_256G 0x1D    /* 256 Gigabaud */
2271 
2272 } INIT_LINK_VAR;
2273 
2274 /* Structure for MB Command DOWN_LINK (06) */
2275 
2276 typedef struct {
2277 	uint32_t rsvd1;
2278 } DOWN_LINK_VAR;
2279 
2280 /* Structure for MB Command CONFIG_LINK (07) */
2281 
2282 typedef struct {
2283 #ifdef __BIG_ENDIAN_BITFIELD
2284 	uint32_t cr:1;
2285 	uint32_t ci:1;
2286 	uint32_t cr_delay:6;
2287 	uint32_t cr_count:8;
2288 	uint32_t rsvd1:8;
2289 	uint32_t MaxBBC:8;
2290 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2291 	uint32_t MaxBBC:8;
2292 	uint32_t rsvd1:8;
2293 	uint32_t cr_count:8;
2294 	uint32_t cr_delay:6;
2295 	uint32_t ci:1;
2296 	uint32_t cr:1;
2297 #endif
2298 
2299 	uint32_t myId;
2300 	uint32_t rsvd2;
2301 	uint32_t edtov;
2302 	uint32_t arbtov;
2303 	uint32_t ratov;
2304 	uint32_t rttov;
2305 	uint32_t altov;
2306 	uint32_t crtov;
2307 
2308 #ifdef __BIG_ENDIAN_BITFIELD
2309 	uint32_t rsvd4:19;
2310 	uint32_t cscn:1;
2311 	uint32_t bbscn:4;
2312 	uint32_t rsvd3:8;
2313 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2314 	uint32_t rsvd3:8;
2315 	uint32_t bbscn:4;
2316 	uint32_t cscn:1;
2317 	uint32_t rsvd4:19;
2318 #endif
2319 
2320 #ifdef __BIG_ENDIAN_BITFIELD
2321 	uint32_t rrq_enable:1;
2322 	uint32_t rrq_immed:1;
2323 	uint32_t rsvd5:29;
2324 	uint32_t ack0_enable:1;
2325 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2326 	uint32_t ack0_enable:1;
2327 	uint32_t rsvd5:29;
2328 	uint32_t rrq_immed:1;
2329 	uint32_t rrq_enable:1;
2330 #endif
2331 } CONFIG_LINK;
2332 
2333 /* Structure for MB Command PART_SLIM (08)
2334  * will be removed since SLI1 is no longer supported!
2335  */
2336 typedef struct {
2337 #ifdef __BIG_ENDIAN_BITFIELD
2338 	uint16_t offCiocb;
2339 	uint16_t numCiocb;
2340 	uint16_t offRiocb;
2341 	uint16_t numRiocb;
2342 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2343 	uint16_t numCiocb;
2344 	uint16_t offCiocb;
2345 	uint16_t numRiocb;
2346 	uint16_t offRiocb;
2347 #endif
2348 } RING_DEF;
2349 
2350 typedef struct {
2351 #ifdef __BIG_ENDIAN_BITFIELD
2352 	uint32_t unused1:24;
2353 	uint32_t numRing:8;
2354 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2355 	uint32_t numRing:8;
2356 	uint32_t unused1:24;
2357 #endif
2358 
2359 	RING_DEF ringdef[4];
2360 	uint32_t hbainit;
2361 } PART_SLIM_VAR;
2362 
2363 /* Structure for MB Command CONFIG_RING (09) */
2364 
2365 typedef struct {
2366 #ifdef __BIG_ENDIAN_BITFIELD
2367 	uint32_t unused2:6;
2368 	uint32_t recvSeq:1;
2369 	uint32_t recvNotify:1;
2370 	uint32_t numMask:8;
2371 	uint32_t profile:8;
2372 	uint32_t unused1:4;
2373 	uint32_t ring:4;
2374 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2375 	uint32_t ring:4;
2376 	uint32_t unused1:4;
2377 	uint32_t profile:8;
2378 	uint32_t numMask:8;
2379 	uint32_t recvNotify:1;
2380 	uint32_t recvSeq:1;
2381 	uint32_t unused2:6;
2382 #endif
2383 
2384 #ifdef __BIG_ENDIAN_BITFIELD
2385 	uint16_t maxRespXchg;
2386 	uint16_t maxOrigXchg;
2387 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2388 	uint16_t maxOrigXchg;
2389 	uint16_t maxRespXchg;
2390 #endif
2391 
2392 	RR_REG rrRegs[6];
2393 } CONFIG_RING_VAR;
2394 
2395 /* Structure for MB Command RESET_RING (10) */
2396 
2397 typedef struct {
2398 	uint32_t ring_no;
2399 } RESET_RING_VAR;
2400 
2401 /* Structure for MB Command READ_CONFIG (11) */
2402 
2403 typedef struct {
2404 #ifdef __BIG_ENDIAN_BITFIELD
2405 	uint32_t cr:1;
2406 	uint32_t ci:1;
2407 	uint32_t cr_delay:6;
2408 	uint32_t cr_count:8;
2409 	uint32_t InitBBC:8;
2410 	uint32_t MaxBBC:8;
2411 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2412 	uint32_t MaxBBC:8;
2413 	uint32_t InitBBC:8;
2414 	uint32_t cr_count:8;
2415 	uint32_t cr_delay:6;
2416 	uint32_t ci:1;
2417 	uint32_t cr:1;
2418 #endif
2419 
2420 #ifdef __BIG_ENDIAN_BITFIELD
2421 	uint32_t topology:8;
2422 	uint32_t myDid:24;
2423 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2424 	uint32_t myDid:24;
2425 	uint32_t topology:8;
2426 #endif
2427 
2428 	/* Defines for topology (defined previously) */
2429 #ifdef __BIG_ENDIAN_BITFIELD
2430 	uint32_t AR:1;
2431 	uint32_t IR:1;
2432 	uint32_t rsvd1:29;
2433 	uint32_t ack0:1;
2434 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2435 	uint32_t ack0:1;
2436 	uint32_t rsvd1:29;
2437 	uint32_t IR:1;
2438 	uint32_t AR:1;
2439 #endif
2440 
2441 	uint32_t edtov;
2442 	uint32_t arbtov;
2443 	uint32_t ratov;
2444 	uint32_t rttov;
2445 	uint32_t altov;
2446 	uint32_t lmt;
2447 #define LMT_RESERVED  0x000    /* Not used */
2448 #define LMT_1Gb       0x004
2449 #define LMT_2Gb       0x008
2450 #define LMT_4Gb       0x040
2451 #define LMT_8Gb       0x080
2452 #define LMT_10Gb      0x100
2453 #define LMT_16Gb      0x200
2454 #define LMT_32Gb      0x400
2455 #define LMT_64Gb      0x800
2456 #define LMT_128Gb     0x1000
2457 #define LMT_256Gb     0x2000
2458 	uint32_t rsvd2;
2459 	uint32_t rsvd3;
2460 	uint32_t max_xri;
2461 	uint32_t max_iocb;
2462 	uint32_t max_rpi;
2463 	uint32_t avail_xri;
2464 	uint32_t avail_iocb;
2465 	uint32_t avail_rpi;
2466 	uint32_t max_vpi;
2467 	uint32_t rsvd4;
2468 	uint32_t rsvd5;
2469 	uint32_t avail_vpi;
2470 } READ_CONFIG_VAR;
2471 
2472 /* Structure for MB Command READ_RCONFIG (12) */
2473 
2474 typedef struct {
2475 #ifdef __BIG_ENDIAN_BITFIELD
2476 	uint32_t rsvd2:7;
2477 	uint32_t recvNotify:1;
2478 	uint32_t numMask:8;
2479 	uint32_t profile:8;
2480 	uint32_t rsvd1:4;
2481 	uint32_t ring:4;
2482 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2483 	uint32_t ring:4;
2484 	uint32_t rsvd1:4;
2485 	uint32_t profile:8;
2486 	uint32_t numMask:8;
2487 	uint32_t recvNotify:1;
2488 	uint32_t rsvd2:7;
2489 #endif
2490 
2491 #ifdef __BIG_ENDIAN_BITFIELD
2492 	uint16_t maxResp;
2493 	uint16_t maxOrig;
2494 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2495 	uint16_t maxOrig;
2496 	uint16_t maxResp;
2497 #endif
2498 
2499 	RR_REG rrRegs[6];
2500 
2501 #ifdef __BIG_ENDIAN_BITFIELD
2502 	uint16_t cmdRingOffset;
2503 	uint16_t cmdEntryCnt;
2504 	uint16_t rspRingOffset;
2505 	uint16_t rspEntryCnt;
2506 	uint16_t nextCmdOffset;
2507 	uint16_t rsvd3;
2508 	uint16_t nextRspOffset;
2509 	uint16_t rsvd4;
2510 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2511 	uint16_t cmdEntryCnt;
2512 	uint16_t cmdRingOffset;
2513 	uint16_t rspEntryCnt;
2514 	uint16_t rspRingOffset;
2515 	uint16_t rsvd3;
2516 	uint16_t nextCmdOffset;
2517 	uint16_t rsvd4;
2518 	uint16_t nextRspOffset;
2519 #endif
2520 } READ_RCONF_VAR;
2521 
2522 /* Structure for MB Command READ_SPARM (13) */
2523 /* Structure for MB Command READ_SPARM64 (0x8D) */
2524 
2525 typedef struct {
2526 	uint32_t rsvd1;
2527 	uint32_t rsvd2;
2528 	union {
2529 		struct ulp_bde sp; /* This BDE points to struct serv_parm
2530 				      structure */
2531 		struct ulp_bde64 sp64;
2532 	} un;
2533 #ifdef __BIG_ENDIAN_BITFIELD
2534 	uint16_t rsvd3;
2535 	uint16_t vpi;
2536 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2537 	uint16_t vpi;
2538 	uint16_t rsvd3;
2539 #endif
2540 } READ_SPARM_VAR;
2541 
2542 /* Structure for MB Command READ_STATUS (14) */
2543 
2544 typedef struct {
2545 #ifdef __BIG_ENDIAN_BITFIELD
2546 	uint32_t rsvd1:31;
2547 	uint32_t clrCounters:1;
2548 	uint16_t activeXriCnt;
2549 	uint16_t activeRpiCnt;
2550 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2551 	uint32_t clrCounters:1;
2552 	uint32_t rsvd1:31;
2553 	uint16_t activeRpiCnt;
2554 	uint16_t activeXriCnt;
2555 #endif
2556 
2557 	uint32_t xmitByteCnt;
2558 	uint32_t rcvByteCnt;
2559 	uint32_t xmitFrameCnt;
2560 	uint32_t rcvFrameCnt;
2561 	uint32_t xmitSeqCnt;
2562 	uint32_t rcvSeqCnt;
2563 	uint32_t totalOrigExchanges;
2564 	uint32_t totalRespExchanges;
2565 	uint32_t rcvPbsyCnt;
2566 	uint32_t rcvFbsyCnt;
2567 } READ_STATUS_VAR;
2568 
2569 /* Structure for MB Command READ_RPI (15) */
2570 /* Structure for MB Command READ_RPI64 (0x8F) */
2571 
2572 typedef struct {
2573 #ifdef __BIG_ENDIAN_BITFIELD
2574 	uint16_t nextRpi;
2575 	uint16_t reqRpi;
2576 	uint32_t rsvd2:8;
2577 	uint32_t DID:24;
2578 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2579 	uint16_t reqRpi;
2580 	uint16_t nextRpi;
2581 	uint32_t DID:24;
2582 	uint32_t rsvd2:8;
2583 #endif
2584 
2585 	union {
2586 		struct ulp_bde sp;
2587 		struct ulp_bde64 sp64;
2588 	} un;
2589 
2590 } READ_RPI_VAR;
2591 
2592 /* Structure for MB Command READ_XRI (16) */
2593 
2594 typedef struct {
2595 #ifdef __BIG_ENDIAN_BITFIELD
2596 	uint16_t nextXri;
2597 	uint16_t reqXri;
2598 	uint16_t rsvd1;
2599 	uint16_t rpi;
2600 	uint32_t rsvd2:8;
2601 	uint32_t DID:24;
2602 	uint32_t rsvd3:8;
2603 	uint32_t SID:24;
2604 	uint32_t rsvd4;
2605 	uint8_t seqId;
2606 	uint8_t rsvd5;
2607 	uint16_t seqCount;
2608 	uint16_t oxId;
2609 	uint16_t rxId;
2610 	uint32_t rsvd6:30;
2611 	uint32_t si:1;
2612 	uint32_t exchOrig:1;
2613 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2614 	uint16_t reqXri;
2615 	uint16_t nextXri;
2616 	uint16_t rpi;
2617 	uint16_t rsvd1;
2618 	uint32_t DID:24;
2619 	uint32_t rsvd2:8;
2620 	uint32_t SID:24;
2621 	uint32_t rsvd3:8;
2622 	uint32_t rsvd4;
2623 	uint16_t seqCount;
2624 	uint8_t rsvd5;
2625 	uint8_t seqId;
2626 	uint16_t rxId;
2627 	uint16_t oxId;
2628 	uint32_t exchOrig:1;
2629 	uint32_t si:1;
2630 	uint32_t rsvd6:30;
2631 #endif
2632 } READ_XRI_VAR;
2633 
2634 /* Structure for MB Command READ_REV (17) */
2635 
2636 typedef struct {
2637 #ifdef __BIG_ENDIAN_BITFIELD
2638 	uint32_t cv:1;
2639 	uint32_t rr:1;
2640 	uint32_t rsvd2:2;
2641 	uint32_t v3req:1;
2642 	uint32_t v3rsp:1;
2643 	uint32_t rsvd1:25;
2644 	uint32_t rv:1;
2645 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2646 	uint32_t rv:1;
2647 	uint32_t rsvd1:25;
2648 	uint32_t v3rsp:1;
2649 	uint32_t v3req:1;
2650 	uint32_t rsvd2:2;
2651 	uint32_t rr:1;
2652 	uint32_t cv:1;
2653 #endif
2654 
2655 	uint32_t biuRev;
2656 	uint32_t smRev;
2657 	union {
2658 		uint32_t smFwRev;
2659 		struct {
2660 #ifdef __BIG_ENDIAN_BITFIELD
2661 			uint8_t ProgType;
2662 			uint8_t ProgId;
2663 			uint16_t ProgVer:4;
2664 			uint16_t ProgRev:4;
2665 			uint16_t ProgFixLvl:2;
2666 			uint16_t ProgDistType:2;
2667 			uint16_t DistCnt:4;
2668 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2669 			uint16_t DistCnt:4;
2670 			uint16_t ProgDistType:2;
2671 			uint16_t ProgFixLvl:2;
2672 			uint16_t ProgRev:4;
2673 			uint16_t ProgVer:4;
2674 			uint8_t ProgId;
2675 			uint8_t ProgType;
2676 #endif
2677 
2678 		} b;
2679 	} un;
2680 	uint32_t endecRev;
2681 #ifdef __BIG_ENDIAN_BITFIELD
2682 	uint8_t feaLevelHigh;
2683 	uint8_t feaLevelLow;
2684 	uint8_t fcphHigh;
2685 	uint8_t fcphLow;
2686 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2687 	uint8_t fcphLow;
2688 	uint8_t fcphHigh;
2689 	uint8_t feaLevelLow;
2690 	uint8_t feaLevelHigh;
2691 #endif
2692 
2693 	uint32_t postKernRev;
2694 	uint32_t opFwRev;
2695 	uint8_t opFwName[16];
2696 	uint32_t sli1FwRev;
2697 	uint8_t sli1FwName[16];
2698 	uint32_t sli2FwRev;
2699 	uint8_t sli2FwName[16];
2700 	uint32_t sli3Feat;
2701 	uint32_t RandomData[6];
2702 } READ_REV_VAR;
2703 
2704 /* Structure for MB Command READ_LINK_STAT (18) */
2705 
2706 typedef struct {
2707 	uint32_t word0;
2708 
2709 #define lpfc_read_link_stat_rec_SHIFT   0
2710 #define lpfc_read_link_stat_rec_MASK   0x1
2711 #define lpfc_read_link_stat_rec_WORD   word0
2712 
2713 #define lpfc_read_link_stat_gec_SHIFT	1
2714 #define lpfc_read_link_stat_gec_MASK   0x1
2715 #define lpfc_read_link_stat_gec_WORD   word0
2716 
2717 #define lpfc_read_link_stat_w02oftow23of_SHIFT	2
2718 #define lpfc_read_link_stat_w02oftow23of_MASK   0x3FFFFF
2719 #define lpfc_read_link_stat_w02oftow23of_WORD   word0
2720 
2721 #define lpfc_read_link_stat_rsvd_SHIFT	24
2722 #define lpfc_read_link_stat_rsvd_MASK   0x1F
2723 #define lpfc_read_link_stat_rsvd_WORD   word0
2724 
2725 #define lpfc_read_link_stat_gec2_SHIFT  29
2726 #define lpfc_read_link_stat_gec2_MASK   0x1
2727 #define lpfc_read_link_stat_gec2_WORD   word0
2728 
2729 #define lpfc_read_link_stat_clrc_SHIFT  30
2730 #define lpfc_read_link_stat_clrc_MASK   0x1
2731 #define lpfc_read_link_stat_clrc_WORD   word0
2732 
2733 #define lpfc_read_link_stat_clof_SHIFT  31
2734 #define lpfc_read_link_stat_clof_MASK   0x1
2735 #define lpfc_read_link_stat_clof_WORD   word0
2736 
2737 	uint32_t linkFailureCnt;
2738 	uint32_t lossSyncCnt;
2739 	uint32_t lossSignalCnt;
2740 	uint32_t primSeqErrCnt;
2741 	uint32_t invalidXmitWord;
2742 	uint32_t crcCnt;
2743 	uint32_t primSeqTimeout;
2744 	uint32_t elasticOverrun;
2745 	uint32_t arbTimeout;
2746 	uint32_t advRecBufCredit;
2747 	uint32_t curRecBufCredit;
2748 	uint32_t advTransBufCredit;
2749 	uint32_t curTransBufCredit;
2750 	uint32_t recEofCount;
2751 	uint32_t recEofdtiCount;
2752 	uint32_t recEofniCount;
2753 	uint32_t recSofcount;
2754 	uint32_t rsvd1;
2755 	uint32_t rsvd2;
2756 	uint32_t recDrpXriCount;
2757 	uint32_t fecCorrBlkCount;
2758 	uint32_t fecUncorrBlkCount;
2759 } READ_LNK_VAR;
2760 
2761 /* Structure for MB Command REG_LOGIN (19) */
2762 /* Structure for MB Command REG_LOGIN64 (0x93) */
2763 
2764 typedef struct {
2765 #ifdef __BIG_ENDIAN_BITFIELD
2766 	uint16_t rsvd1;
2767 	uint16_t rpi;
2768 	uint32_t rsvd2:8;
2769 	uint32_t did:24;
2770 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2771 	uint16_t rpi;
2772 	uint16_t rsvd1;
2773 	uint32_t did:24;
2774 	uint32_t rsvd2:8;
2775 #endif
2776 
2777 	union {
2778 		struct ulp_bde sp;
2779 		struct ulp_bde64 sp64;
2780 	} un;
2781 
2782 #ifdef __BIG_ENDIAN_BITFIELD
2783 	uint16_t rsvd6;
2784 	uint16_t vpi;
2785 #else /* __LITTLE_ENDIAN_BITFIELD */
2786 	uint16_t vpi;
2787 	uint16_t rsvd6;
2788 #endif
2789 
2790 } REG_LOGIN_VAR;
2791 
2792 /* Word 30 contents for REG_LOGIN */
2793 typedef union {
2794 	struct {
2795 #ifdef __BIG_ENDIAN_BITFIELD
2796 		uint16_t rsvd1:12;
2797 		uint16_t wd30_class:4;
2798 		uint16_t xri;
2799 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2800 		uint16_t xri;
2801 		uint16_t wd30_class:4;
2802 		uint16_t rsvd1:12;
2803 #endif
2804 	} f;
2805 	uint32_t word;
2806 } REG_WD30;
2807 
2808 /* Structure for MB Command UNREG_LOGIN (20) */
2809 
2810 typedef struct {
2811 #ifdef __BIG_ENDIAN_BITFIELD
2812 	uint16_t rsvd1;
2813 	uint16_t rpi;
2814 	uint32_t rsvd2;
2815 	uint32_t rsvd3;
2816 	uint32_t rsvd4;
2817 	uint32_t rsvd5;
2818 	uint16_t rsvd6;
2819 	uint16_t vpi;
2820 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2821 	uint16_t rpi;
2822 	uint16_t rsvd1;
2823 	uint32_t rsvd2;
2824 	uint32_t rsvd3;
2825 	uint32_t rsvd4;
2826 	uint32_t rsvd5;
2827 	uint16_t vpi;
2828 	uint16_t rsvd6;
2829 #endif
2830 } UNREG_LOGIN_VAR;
2831 
2832 /* Structure for MB Command REG_VPI (0x96) */
2833 typedef struct {
2834 #ifdef __BIG_ENDIAN_BITFIELD
2835 	uint32_t rsvd1;
2836 	uint32_t rsvd2:7;
2837 	uint32_t upd:1;
2838 	uint32_t sid:24;
2839 	uint32_t wwn[2];
2840 	uint32_t rsvd5;
2841 	uint16_t vfi;
2842 	uint16_t vpi;
2843 #else	/*  __LITTLE_ENDIAN */
2844 	uint32_t rsvd1;
2845 	uint32_t sid:24;
2846 	uint32_t upd:1;
2847 	uint32_t rsvd2:7;
2848 	uint32_t wwn[2];
2849 	uint32_t rsvd5;
2850 	uint16_t vpi;
2851 	uint16_t vfi;
2852 #endif
2853 } REG_VPI_VAR;
2854 
2855 /* Structure for MB Command UNREG_VPI (0x97) */
2856 typedef struct {
2857 	uint32_t rsvd1;
2858 #ifdef __BIG_ENDIAN_BITFIELD
2859 	uint16_t rsvd2;
2860 	uint16_t sli4_vpi;
2861 #else	/*  __LITTLE_ENDIAN */
2862 	uint16_t sli4_vpi;
2863 	uint16_t rsvd2;
2864 #endif
2865 	uint32_t rsvd3;
2866 	uint32_t rsvd4;
2867 	uint32_t rsvd5;
2868 #ifdef __BIG_ENDIAN_BITFIELD
2869 	uint16_t rsvd6;
2870 	uint16_t vpi;
2871 #else	/*  __LITTLE_ENDIAN */
2872 	uint16_t vpi;
2873 	uint16_t rsvd6;
2874 #endif
2875 } UNREG_VPI_VAR;
2876 
2877 /* Structure for MB Command UNREG_D_ID (0x23) */
2878 
2879 typedef struct {
2880 	uint32_t did;
2881 	uint32_t rsvd2;
2882 	uint32_t rsvd3;
2883 	uint32_t rsvd4;
2884 	uint32_t rsvd5;
2885 #ifdef __BIG_ENDIAN_BITFIELD
2886 	uint16_t rsvd6;
2887 	uint16_t vpi;
2888 #else
2889 	uint16_t vpi;
2890 	uint16_t rsvd6;
2891 #endif
2892 } UNREG_D_ID_VAR;
2893 
2894 /* Structure for MB Command READ_TOPOLOGY (0x95) */
2895 struct lpfc_mbx_read_top {
2896 	uint32_t eventTag;	/* Event tag */
2897 	uint32_t word2;
2898 #define lpfc_mbx_read_top_fa_SHIFT		12
2899 #define lpfc_mbx_read_top_fa_MASK		0x00000001
2900 #define lpfc_mbx_read_top_fa_WORD		word2
2901 #define lpfc_mbx_read_top_mm_SHIFT		11
2902 #define lpfc_mbx_read_top_mm_MASK		0x00000001
2903 #define lpfc_mbx_read_top_mm_WORD		word2
2904 #define lpfc_mbx_read_top_pb_SHIFT		9
2905 #define lpfc_mbx_read_top_pb_MASK		0X00000001
2906 #define lpfc_mbx_read_top_pb_WORD		word2
2907 #define lpfc_mbx_read_top_il_SHIFT		8
2908 #define lpfc_mbx_read_top_il_MASK		0x00000001
2909 #define lpfc_mbx_read_top_il_WORD		word2
2910 #define lpfc_mbx_read_top_att_type_SHIFT	0
2911 #define lpfc_mbx_read_top_att_type_MASK		0x000000FF
2912 #define lpfc_mbx_read_top_att_type_WORD		word2
2913 #define LPFC_ATT_RESERVED    0x00	/* Reserved - attType */
2914 #define LPFC_ATT_LINK_UP     0x01	/* Link is up */
2915 #define LPFC_ATT_LINK_DOWN   0x02	/* Link is down */
2916 #define LPFC_ATT_UNEXP_WWPN  0x06	/* Link is down Unexpected WWWPN */
2917 	uint32_t word3;
2918 #define lpfc_mbx_read_top_alpa_granted_SHIFT	24
2919 #define lpfc_mbx_read_top_alpa_granted_MASK	0x000000FF
2920 #define lpfc_mbx_read_top_alpa_granted_WORD	word3
2921 #define lpfc_mbx_read_top_lip_alps_SHIFT	16
2922 #define lpfc_mbx_read_top_lip_alps_MASK		0x000000FF
2923 #define lpfc_mbx_read_top_lip_alps_WORD		word3
2924 #define lpfc_mbx_read_top_lip_type_SHIFT	8
2925 #define lpfc_mbx_read_top_lip_type_MASK		0x000000FF
2926 #define lpfc_mbx_read_top_lip_type_WORD		word3
2927 #define lpfc_mbx_read_top_topology_SHIFT	0
2928 #define lpfc_mbx_read_top_topology_MASK		0x000000FF
2929 #define lpfc_mbx_read_top_topology_WORD		word3
2930 #define LPFC_TOPOLOGY_PT_PT 0x01	/* Topology is pt-pt / pt-fabric */
2931 #define LPFC_TOPOLOGY_LOOP  0x02	/* Topology is FC-AL */
2932 #define LPFC_TOPOLOGY_MM    0x05	/* maint mode zephtr to menlo */
2933 	/* store the LILP AL_PA position map into */
2934 	struct ulp_bde64 lilpBde64;
2935 #define LPFC_ALPA_MAP_SIZE	128
2936 	uint32_t word7;
2937 #define lpfc_mbx_read_top_ld_lu_SHIFT		31
2938 #define lpfc_mbx_read_top_ld_lu_MASK		0x00000001
2939 #define lpfc_mbx_read_top_ld_lu_WORD		word7
2940 #define lpfc_mbx_read_top_ld_tf_SHIFT		30
2941 #define lpfc_mbx_read_top_ld_tf_MASK		0x00000001
2942 #define lpfc_mbx_read_top_ld_tf_WORD		word7
2943 #define lpfc_mbx_read_top_ld_link_spd_SHIFT	8
2944 #define lpfc_mbx_read_top_ld_link_spd_MASK	0x000000FF
2945 #define lpfc_mbx_read_top_ld_link_spd_WORD	word7
2946 #define lpfc_mbx_read_top_ld_nl_port_SHIFT	4
2947 #define lpfc_mbx_read_top_ld_nl_port_MASK	0x0000000F
2948 #define lpfc_mbx_read_top_ld_nl_port_WORD	word7
2949 #define lpfc_mbx_read_top_ld_tx_SHIFT		2
2950 #define lpfc_mbx_read_top_ld_tx_MASK		0x00000003
2951 #define lpfc_mbx_read_top_ld_tx_WORD		word7
2952 #define lpfc_mbx_read_top_ld_rx_SHIFT		0
2953 #define lpfc_mbx_read_top_ld_rx_MASK		0x00000003
2954 #define lpfc_mbx_read_top_ld_rx_WORD		word7
2955 	uint32_t word8;
2956 #define lpfc_mbx_read_top_lu_SHIFT		31
2957 #define lpfc_mbx_read_top_lu_MASK		0x00000001
2958 #define lpfc_mbx_read_top_lu_WORD		word8
2959 #define lpfc_mbx_read_top_tf_SHIFT		30
2960 #define lpfc_mbx_read_top_tf_MASK		0x00000001
2961 #define lpfc_mbx_read_top_tf_WORD		word8
2962 #define lpfc_mbx_read_top_link_spd_SHIFT	8
2963 #define lpfc_mbx_read_top_link_spd_MASK		0x000000FF
2964 #define lpfc_mbx_read_top_link_spd_WORD		word8
2965 #define lpfc_mbx_read_top_nl_port_SHIFT		4
2966 #define lpfc_mbx_read_top_nl_port_MASK		0x0000000F
2967 #define lpfc_mbx_read_top_nl_port_WORD		word8
2968 #define lpfc_mbx_read_top_tx_SHIFT		2
2969 #define lpfc_mbx_read_top_tx_MASK		0x00000003
2970 #define lpfc_mbx_read_top_tx_WORD		word8
2971 #define lpfc_mbx_read_top_rx_SHIFT		0
2972 #define lpfc_mbx_read_top_rx_MASK		0x00000003
2973 #define lpfc_mbx_read_top_rx_WORD		word8
2974 #define LPFC_LINK_SPEED_UNKNOWN	0x0
2975 #define LPFC_LINK_SPEED_1GHZ	0x04
2976 #define LPFC_LINK_SPEED_2GHZ	0x08
2977 #define LPFC_LINK_SPEED_4GHZ	0x10
2978 #define LPFC_LINK_SPEED_8GHZ	0x20
2979 #define LPFC_LINK_SPEED_10GHZ	0x40
2980 #define LPFC_LINK_SPEED_16GHZ	0x80
2981 #define LPFC_LINK_SPEED_32GHZ	0x90
2982 #define LPFC_LINK_SPEED_64GHZ	0xA0
2983 #define LPFC_LINK_SPEED_128GHZ	0xB0
2984 #define LPFC_LINK_SPEED_256GHZ	0xC0
2985 };
2986 
2987 /* Structure for MB Command CLEAR_LA (22) */
2988 
2989 typedef struct {
2990 	uint32_t eventTag;	/* Event tag */
2991 	uint32_t rsvd1;
2992 } CLEAR_LA_VAR;
2993 
2994 /* Structure for MB Command DUMP */
2995 
2996 typedef struct {
2997 #ifdef __BIG_ENDIAN_BITFIELD
2998 	uint32_t rsvd:25;
2999 	uint32_t ra:1;
3000 	uint32_t co:1;
3001 	uint32_t cv:1;
3002 	uint32_t type:4;
3003 	uint32_t entry_index:16;
3004 	uint32_t region_id:16;
3005 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3006 	uint32_t type:4;
3007 	uint32_t cv:1;
3008 	uint32_t co:1;
3009 	uint32_t ra:1;
3010 	uint32_t rsvd:25;
3011 	uint32_t region_id:16;
3012 	uint32_t entry_index:16;
3013 #endif
3014 
3015 	uint32_t sli4_length;
3016 	uint32_t word_cnt;
3017 	uint32_t resp_offset;
3018 } DUMP_VAR;
3019 
3020 #define  DMP_MEM_REG             0x1
3021 #define  DMP_NV_PARAMS           0x2
3022 #define  DMP_LMSD                0x3 /* Link Module Serial Data */
3023 #define  DMP_WELL_KNOWN          0x4
3024 
3025 #define  DMP_REGION_VPD          0xe
3026 #define  DMP_VPD_SIZE            0x400  /* maximum amount of VPD */
3027 #define  DMP_RSP_OFFSET          0x14   /* word 5 contains first word of rsp */
3028 #define  DMP_RSP_SIZE            0x6C   /* maximum of 27 words of rsp data */
3029 
3030 #define  DMP_REGION_VPORT	 0x16   /* VPort info region */
3031 #define  DMP_VPORT_REGION_SIZE	 0x200
3032 #define  DMP_MBOX_OFFSET_WORD	 0x5
3033 
3034 #define  DMP_REGION_23		 0x17   /* fcoe param  and port state region */
3035 #define  DMP_RGN23_SIZE		 0x400
3036 
3037 #define  WAKE_UP_PARMS_REGION_ID    4
3038 #define  WAKE_UP_PARMS_WORD_SIZE   15
3039 
3040 struct vport_rec {
3041 	uint8_t wwpn[8];
3042 	uint8_t wwnn[8];
3043 };
3044 
3045 #define VPORT_INFO_SIG 0x32324752
3046 #define VPORT_INFO_REV_MASK 0xff
3047 #define VPORT_INFO_REV 0x1
3048 #define MAX_STATIC_VPORT_COUNT 16
3049 struct static_vport_info {
3050 	uint32_t		signature;
3051 	uint32_t		rev;
3052 	struct vport_rec	vport_list[MAX_STATIC_VPORT_COUNT];
3053 	uint32_t		resvd[66];
3054 };
3055 
3056 /* Option rom version structure */
3057 struct prog_id {
3058 #ifdef __BIG_ENDIAN_BITFIELD
3059 	uint8_t  type;
3060 	uint8_t  id;
3061 	uint32_t ver:4;  /* Major Version */
3062 	uint32_t rev:4;  /* Revision */
3063 	uint32_t lev:2;  /* Level */
3064 	uint32_t dist:2; /* Dist Type */
3065 	uint32_t num:4;  /* number after dist type */
3066 #else /*  __LITTLE_ENDIAN_BITFIELD */
3067 	uint32_t num:4;  /* number after dist type */
3068 	uint32_t dist:2; /* Dist Type */
3069 	uint32_t lev:2;  /* Level */
3070 	uint32_t rev:4;  /* Revision */
3071 	uint32_t ver:4;  /* Major Version */
3072 	uint8_t  id;
3073 	uint8_t  type;
3074 #endif
3075 };
3076 
3077 /* Structure for MB Command UPDATE_CFG (0x1B) */
3078 
3079 struct update_cfg_var {
3080 #ifdef __BIG_ENDIAN_BITFIELD
3081 	uint32_t rsvd2:16;
3082 	uint32_t type:8;
3083 	uint32_t rsvd:1;
3084 	uint32_t ra:1;
3085 	uint32_t co:1;
3086 	uint32_t cv:1;
3087 	uint32_t req:4;
3088 	uint32_t entry_length:16;
3089 	uint32_t region_id:16;
3090 #else  /*  __LITTLE_ENDIAN_BITFIELD */
3091 	uint32_t req:4;
3092 	uint32_t cv:1;
3093 	uint32_t co:1;
3094 	uint32_t ra:1;
3095 	uint32_t rsvd:1;
3096 	uint32_t type:8;
3097 	uint32_t rsvd2:16;
3098 	uint32_t region_id:16;
3099 	uint32_t entry_length:16;
3100 #endif
3101 
3102 	uint32_t resp_info;
3103 	uint32_t byte_cnt;
3104 	uint32_t data_offset;
3105 };
3106 
3107 struct hbq_mask {
3108 #ifdef __BIG_ENDIAN_BITFIELD
3109 	uint8_t tmatch;
3110 	uint8_t tmask;
3111 	uint8_t rctlmatch;
3112 	uint8_t rctlmask;
3113 #else	/*  __LITTLE_ENDIAN */
3114 	uint8_t rctlmask;
3115 	uint8_t rctlmatch;
3116 	uint8_t tmask;
3117 	uint8_t tmatch;
3118 #endif
3119 };
3120 
3121 
3122 /* Structure for MB Command CONFIG_HBQ (7c) */
3123 
3124 struct config_hbq_var {
3125 #ifdef __BIG_ENDIAN_BITFIELD
3126 	uint32_t rsvd1      :7;
3127 	uint32_t recvNotify :1;     /* Receive Notification */
3128 	uint32_t numMask    :8;     /* # Mask Entries       */
3129 	uint32_t profile    :8;     /* Selection Profile    */
3130 	uint32_t rsvd2      :8;
3131 #else	/*  __LITTLE_ENDIAN */
3132 	uint32_t rsvd2      :8;
3133 	uint32_t profile    :8;     /* Selection Profile    */
3134 	uint32_t numMask    :8;     /* # Mask Entries       */
3135 	uint32_t recvNotify :1;     /* Receive Notification */
3136 	uint32_t rsvd1      :7;
3137 #endif
3138 
3139 #ifdef __BIG_ENDIAN_BITFIELD
3140 	uint32_t hbqId      :16;
3141 	uint32_t rsvd3      :12;
3142 	uint32_t ringMask   :4;
3143 #else	/*  __LITTLE_ENDIAN */
3144 	uint32_t ringMask   :4;
3145 	uint32_t rsvd3      :12;
3146 	uint32_t hbqId      :16;
3147 #endif
3148 
3149 #ifdef __BIG_ENDIAN_BITFIELD
3150 	uint32_t entry_count :16;
3151 	uint32_t rsvd4        :8;
3152 	uint32_t headerLen    :8;
3153 #else	/*  __LITTLE_ENDIAN */
3154 	uint32_t headerLen    :8;
3155 	uint32_t rsvd4        :8;
3156 	uint32_t entry_count :16;
3157 #endif
3158 
3159 	uint32_t hbqaddrLow;
3160 	uint32_t hbqaddrHigh;
3161 
3162 #ifdef __BIG_ENDIAN_BITFIELD
3163 	uint32_t rsvd5      :31;
3164 	uint32_t logEntry   :1;
3165 #else	/*  __LITTLE_ENDIAN */
3166 	uint32_t logEntry   :1;
3167 	uint32_t rsvd5      :31;
3168 #endif
3169 
3170 	uint32_t rsvd6;    /* w7 */
3171 	uint32_t rsvd7;    /* w8 */
3172 	uint32_t rsvd8;    /* w9 */
3173 
3174 	struct hbq_mask hbqMasks[6];
3175 
3176 
3177 	union {
3178 		uint32_t allprofiles[12];
3179 
3180 		struct {
3181 			#ifdef __BIG_ENDIAN_BITFIELD
3182 				uint32_t	seqlenoff	:16;
3183 				uint32_t	maxlen		:16;
3184 			#else	/*  __LITTLE_ENDIAN */
3185 				uint32_t	maxlen		:16;
3186 				uint32_t	seqlenoff	:16;
3187 			#endif
3188 			#ifdef __BIG_ENDIAN_BITFIELD
3189 				uint32_t	rsvd1		:28;
3190 				uint32_t	seqlenbcnt	:4;
3191 			#else	/*  __LITTLE_ENDIAN */
3192 				uint32_t	seqlenbcnt	:4;
3193 				uint32_t	rsvd1		:28;
3194 			#endif
3195 			uint32_t rsvd[10];
3196 		} profile2;
3197 
3198 		struct {
3199 			#ifdef __BIG_ENDIAN_BITFIELD
3200 				uint32_t	seqlenoff	:16;
3201 				uint32_t	maxlen		:16;
3202 			#else	/*  __LITTLE_ENDIAN */
3203 				uint32_t	maxlen		:16;
3204 				uint32_t	seqlenoff	:16;
3205 			#endif
3206 			#ifdef __BIG_ENDIAN_BITFIELD
3207 				uint32_t	cmdcodeoff	:28;
3208 				uint32_t	rsvd1		:12;
3209 				uint32_t	seqlenbcnt	:4;
3210 			#else	/*  __LITTLE_ENDIAN */
3211 				uint32_t	seqlenbcnt	:4;
3212 				uint32_t	rsvd1		:12;
3213 				uint32_t	cmdcodeoff	:28;
3214 			#endif
3215 			uint32_t cmdmatch[8];
3216 
3217 			uint32_t rsvd[2];
3218 		} profile3;
3219 
3220 		struct {
3221 			#ifdef __BIG_ENDIAN_BITFIELD
3222 				uint32_t	seqlenoff	:16;
3223 				uint32_t	maxlen		:16;
3224 			#else	/*  __LITTLE_ENDIAN */
3225 				uint32_t	maxlen		:16;
3226 				uint32_t	seqlenoff	:16;
3227 			#endif
3228 			#ifdef __BIG_ENDIAN_BITFIELD
3229 				uint32_t	cmdcodeoff	:28;
3230 				uint32_t	rsvd1		:12;
3231 				uint32_t	seqlenbcnt	:4;
3232 			#else	/*  __LITTLE_ENDIAN */
3233 				uint32_t	seqlenbcnt	:4;
3234 				uint32_t	rsvd1		:12;
3235 				uint32_t	cmdcodeoff	:28;
3236 			#endif
3237 			uint32_t cmdmatch[8];
3238 
3239 			uint32_t rsvd[2];
3240 		} profile5;
3241 
3242 	} profiles;
3243 
3244 };
3245 
3246 
3247 
3248 /* Structure for MB Command CONFIG_PORT (0x88) */
3249 typedef struct {
3250 #ifdef __BIG_ENDIAN_BITFIELD
3251 	uint32_t cBE       :  1;
3252 	uint32_t cET       :  1;
3253 	uint32_t cHpcb     :  1;
3254 	uint32_t cMA       :  1;
3255 	uint32_t sli_mode  :  4;
3256 	uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
3257 					* config block */
3258 #else	/*  __LITTLE_ENDIAN */
3259 	uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
3260 					* config block */
3261 	uint32_t sli_mode  :  4;
3262 	uint32_t cMA       :  1;
3263 	uint32_t cHpcb     :  1;
3264 	uint32_t cET       :  1;
3265 	uint32_t cBE       :  1;
3266 #endif
3267 
3268 	uint32_t pcbLow;       /* bit 31:0  of memory based port config block */
3269 	uint32_t pcbHigh;      /* bit 63:32 of memory based port config block */
3270 	uint32_t hbainit[5];
3271 #ifdef __BIG_ENDIAN_BITFIELD
3272 	uint32_t hps	   :  1; /* bit 31 word9 Host Pointer in slim */
3273 	uint32_t rsvd	   : 31; /* least significant 31 bits of word 9 */
3274 #else   /*  __LITTLE_ENDIAN */
3275 	uint32_t rsvd      : 31; /* least significant 31 bits of word 9 */
3276 	uint32_t hps	   :  1; /* bit 31 word9 Host Pointer in slim */
3277 #endif
3278 
3279 #ifdef __BIG_ENDIAN_BITFIELD
3280 	uint32_t rsvd1     : 19;  /* Reserved                             */
3281 	uint32_t cdss      :  1;  /* Configure Data Security SLI          */
3282 	uint32_t casabt    :  1;  /* Configure async abts status notice   */
3283 	uint32_t rsvd2     :  2;  /* Reserved                             */
3284 	uint32_t cbg       :  1;  /* Configure BlockGuard                 */
3285 	uint32_t cmv       :  1;  /* Configure Max VPIs                   */
3286 	uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
3287 	uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
3288 	uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
3289 	uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
3290 	uint32_t cerbm	   :  1;  /* Configure Enhanced Receive Buf Mgmt  */
3291 	uint32_t cmx	   :  1;  /* Configure Max XRIs                   */
3292 	uint32_t cmr	   :  1;  /* Configure Max RPIs                   */
3293 #else	/*  __LITTLE_ENDIAN */
3294 	uint32_t cmr	   :  1;  /* Configure Max RPIs                   */
3295 	uint32_t cmx	   :  1;  /* Configure Max XRIs                   */
3296 	uint32_t cerbm	   :  1;  /* Configure Enhanced Receive Buf Mgmt  */
3297 	uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
3298 	uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
3299 	uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
3300 	uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
3301 	uint32_t cmv	   :  1;  /* Configure Max VPIs                   */
3302 	uint32_t cbg       :  1;  /* Configure BlockGuard                 */
3303 	uint32_t rsvd2     :  2;  /* Reserved                             */
3304 	uint32_t casabt    :  1;  /* Configure async abts status notice   */
3305 	uint32_t cdss      :  1;  /* Configure Data Security SLI          */
3306 	uint32_t rsvd1     : 19;  /* Reserved                             */
3307 #endif
3308 #ifdef __BIG_ENDIAN_BITFIELD
3309 	uint32_t rsvd3     : 19;  /* Reserved                             */
3310 	uint32_t gdss      :  1;  /* Configure Data Security SLI          */
3311 	uint32_t gasabt    :  1;  /* Grant async abts status notice       */
3312 	uint32_t rsvd4     :  2;  /* Reserved                             */
3313 	uint32_t gbg       :  1;  /* Grant BlockGuard                     */
3314 	uint32_t gmv	   :  1;  /* Grant Max VPIs                       */
3315 	uint32_t gcrp	   :  1;  /* Grant Command Ring Polling           */
3316 	uint32_t gsah	   :  1;  /* Grant Synchronous Abort Handling     */
3317 	uint32_t ghbs	   :  1;  /* Grant Host Backing Store             */
3318 	uint32_t ginb	   :  1;  /* Grant Interrupt Notification Block   */
3319 	uint32_t gerbm	   :  1;  /* Grant ERBM Request                   */
3320 	uint32_t gmx	   :  1;  /* Grant Max XRIs                       */
3321 	uint32_t gmr	   :  1;  /* Grant Max RPIs                       */
3322 #else	/*  __LITTLE_ENDIAN */
3323 	uint32_t gmr	   :  1;  /* Grant Max RPIs                       */
3324 	uint32_t gmx	   :  1;  /* Grant Max XRIs                       */
3325 	uint32_t gerbm	   :  1;  /* Grant ERBM Request                   */
3326 	uint32_t ginb	   :  1;  /* Grant Interrupt Notification Block   */
3327 	uint32_t ghbs	   :  1;  /* Grant Host Backing Store             */
3328 	uint32_t gsah	   :  1;  /* Grant Synchronous Abort Handling     */
3329 	uint32_t gcrp	   :  1;  /* Grant Command Ring Polling           */
3330 	uint32_t gmv	   :  1;  /* Grant Max VPIs                       */
3331 	uint32_t gbg       :  1;  /* Grant BlockGuard                     */
3332 	uint32_t rsvd4     :  2;  /* Reserved                             */
3333 	uint32_t gasabt    :  1;  /* Grant async abts status notice       */
3334 	uint32_t gdss      :  1;  /* Configure Data Security SLI          */
3335 	uint32_t rsvd3     : 19;  /* Reserved                             */
3336 #endif
3337 
3338 #ifdef __BIG_ENDIAN_BITFIELD
3339 	uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
3340 	uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
3341 #else	/*  __LITTLE_ENDIAN */
3342 	uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
3343 	uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
3344 #endif
3345 
3346 #ifdef __BIG_ENDIAN_BITFIELD
3347 	uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
3348 	uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
3349 #else	/*  __LITTLE_ENDIAN */
3350 	uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
3351 	uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
3352 #endif
3353 
3354 	uint32_t rsvd6;           /* Reserved                             */
3355 
3356 #ifdef __BIG_ENDIAN_BITFIELD
3357 	uint32_t fips_rev   : 3;   /* FIPS Spec Revision                   */
3358 	uint32_t fips_level : 4;   /* FIPS Level                           */
3359 	uint32_t sec_err    : 9;   /* security crypto error                */
3360 	uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
3361 #else	/*  __LITTLE_ENDIAN */
3362 	uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
3363 	uint32_t sec_err    : 9;   /* security crypto error                */
3364 	uint32_t fips_level : 4;   /* FIPS Level                           */
3365 	uint32_t fips_rev   : 3;   /* FIPS Spec Revision                   */
3366 #endif
3367 
3368 } CONFIG_PORT_VAR;
3369 
3370 /* Structure for MB Command CONFIG_MSI (0x30) */
3371 struct config_msi_var {
3372 #ifdef __BIG_ENDIAN_BITFIELD
3373 	uint32_t dfltMsgNum:8;	/* Default message number            */
3374 	uint32_t rsvd1:11;	/* Reserved                          */
3375 	uint32_t NID:5;		/* Number of secondary attention IDs */
3376 	uint32_t rsvd2:5;	/* Reserved                          */
3377 	uint32_t dfltPresent:1;	/* Default message number present    */
3378 	uint32_t addFlag:1;	/* Add association flag              */
3379 	uint32_t reportFlag:1;	/* Report association flag           */
3380 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3381 	uint32_t reportFlag:1;	/* Report association flag           */
3382 	uint32_t addFlag:1;	/* Add association flag              */
3383 	uint32_t dfltPresent:1;	/* Default message number present    */
3384 	uint32_t rsvd2:5;	/* Reserved                          */
3385 	uint32_t NID:5;		/* Number of secondary attention IDs */
3386 	uint32_t rsvd1:11;	/* Reserved                          */
3387 	uint32_t dfltMsgNum:8;	/* Default message number            */
3388 #endif
3389 	uint32_t attentionConditions[2];
3390 	uint8_t  attentionId[16];
3391 	uint8_t  messageNumberByHA[64];
3392 	uint8_t  messageNumberByID[16];
3393 	uint32_t autoClearHA[2];
3394 #ifdef __BIG_ENDIAN_BITFIELD
3395 	uint32_t rsvd3:16;
3396 	uint32_t autoClearID:16;
3397 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3398 	uint32_t autoClearID:16;
3399 	uint32_t rsvd3:16;
3400 #endif
3401 	uint32_t rsvd4;
3402 };
3403 
3404 /* SLI-2 Port Control Block */
3405 
3406 /* SLIM POINTER */
3407 #define SLIMOFF 0x30		/* WORD */
3408 
3409 typedef struct _SLI2_RDSC {
3410 	uint32_t cmdEntries;
3411 	uint32_t cmdAddrLow;
3412 	uint32_t cmdAddrHigh;
3413 
3414 	uint32_t rspEntries;
3415 	uint32_t rspAddrLow;
3416 	uint32_t rspAddrHigh;
3417 } SLI2_RDSC;
3418 
3419 typedef struct _PCB {
3420 #ifdef __BIG_ENDIAN_BITFIELD
3421 	uint32_t type:8;
3422 #define TYPE_NATIVE_SLI2       0x01
3423 	uint32_t feature:8;
3424 #define FEATURE_INITIAL_SLI2   0x01
3425 	uint32_t rsvd:12;
3426 	uint32_t maxRing:4;
3427 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3428 	uint32_t maxRing:4;
3429 	uint32_t rsvd:12;
3430 	uint32_t feature:8;
3431 #define FEATURE_INITIAL_SLI2   0x01
3432 	uint32_t type:8;
3433 #define TYPE_NATIVE_SLI2       0x01
3434 #endif
3435 
3436 	uint32_t mailBoxSize;
3437 	uint32_t mbAddrLow;
3438 	uint32_t mbAddrHigh;
3439 
3440 	uint32_t hgpAddrLow;
3441 	uint32_t hgpAddrHigh;
3442 
3443 	uint32_t pgpAddrLow;
3444 	uint32_t pgpAddrHigh;
3445 	SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3446 } PCB_t;
3447 
3448 /* NEW_FEATURE */
3449 typedef struct {
3450 #ifdef __BIG_ENDIAN_BITFIELD
3451 	uint32_t rsvd0:27;
3452 	uint32_t discardFarp:1;
3453 	uint32_t IPEnable:1;
3454 	uint32_t nodeName:1;
3455 	uint32_t portName:1;
3456 	uint32_t filterEnable:1;
3457 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3458 	uint32_t filterEnable:1;
3459 	uint32_t portName:1;
3460 	uint32_t nodeName:1;
3461 	uint32_t IPEnable:1;
3462 	uint32_t discardFarp:1;
3463 	uint32_t rsvd:27;
3464 #endif
3465 
3466 	uint8_t portname[8];	/* Used to be struct lpfc_name */
3467 	uint8_t nodename[8];
3468 	uint32_t rsvd1;
3469 	uint32_t rsvd2;
3470 	uint32_t rsvd3;
3471 	uint32_t IPAddress;
3472 } CONFIG_FARP_VAR;
3473 
3474 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3475 
3476 typedef struct {
3477 #ifdef __BIG_ENDIAN_BITFIELD
3478 	uint32_t rsvd:30;
3479 	uint32_t ring:2;	/* Ring for ASYNC_EVENT iocb Bits 0-1*/
3480 #else /*  __LITTLE_ENDIAN */
3481 	uint32_t ring:2;	/* Ring for ASYNC_EVENT iocb Bits 0-1*/
3482 	uint32_t rsvd:30;
3483 #endif
3484 } ASYNCEVT_ENABLE_VAR;
3485 
3486 /* Union of all Mailbox Command types */
3487 #define MAILBOX_CMD_WSIZE	32
3488 #define MAILBOX_CMD_SIZE	(MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3489 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3490 #define MAILBOX_EXT_WSIZE	512
3491 #define MAILBOX_EXT_SIZE	(MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3492 #define MAILBOX_HBA_EXT_OFFSET  0x100
3493 /* max mbox xmit size is a page size for sysfs IO operations */
3494 #define MAILBOX_SYSFS_MAX	4096
3495 
3496 typedef union {
3497 	uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3498 						    * feature/max ring number
3499 						    */
3500 	LOAD_SM_VAR varLdSM;		/* cmd =  1 (LOAD_SM)        */
3501 	READ_NV_VAR varRDnvp;		/* cmd =  2 (READ_NVPARMS)   */
3502 	WRITE_NV_VAR varWTnvp;		/* cmd =  3 (WRITE_NVPARMS)  */
3503 	BIU_DIAG_VAR varBIUdiag;	/* cmd =  4 (RUN_BIU_DIAG)   */
3504 	INIT_LINK_VAR varInitLnk;	/* cmd =  5 (INIT_LINK)      */
3505 	DOWN_LINK_VAR varDwnLnk;	/* cmd =  6 (DOWN_LINK)      */
3506 	CONFIG_LINK varCfgLnk;		/* cmd =  7 (CONFIG_LINK)    */
3507 	PART_SLIM_VAR varSlim;		/* cmd =  8 (PART_SLIM)      */
3508 	CONFIG_RING_VAR varCfgRing;	/* cmd =  9 (CONFIG_RING)    */
3509 	RESET_RING_VAR varRstRing;	/* cmd = 10 (RESET_RING)     */
3510 	READ_CONFIG_VAR varRdConfig;	/* cmd = 11 (READ_CONFIG)    */
3511 	READ_RCONF_VAR varRdRConfig;	/* cmd = 12 (READ_RCONFIG)   */
3512 	READ_SPARM_VAR varRdSparm;	/* cmd = 13 (READ_SPARM(64)) */
3513 	READ_STATUS_VAR varRdStatus;	/* cmd = 14 (READ_STATUS)    */
3514 	READ_RPI_VAR varRdRPI;		/* cmd = 15 (READ_RPI(64))   */
3515 	READ_XRI_VAR varRdXRI;		/* cmd = 16 (READ_XRI)       */
3516 	READ_REV_VAR varRdRev;		/* cmd = 17 (READ_REV)       */
3517 	READ_LNK_VAR varRdLnk;		/* cmd = 18 (READ_LNK_STAT)  */
3518 	REG_LOGIN_VAR varRegLogin;	/* cmd = 19 (REG_LOGIN(64))  */
3519 	UNREG_LOGIN_VAR varUnregLogin;	/* cmd = 20 (UNREG_LOGIN)    */
3520 	CLEAR_LA_VAR varClearLA;	/* cmd = 22 (CLEAR_LA)       */
3521 	DUMP_VAR varDmp;		/* Warm Start DUMP mbx cmd   */
3522 	UNREG_D_ID_VAR varUnregDID;	/* cmd = 0x23 (UNREG_D_ID)   */
3523 	CONFIG_FARP_VAR varCfgFarp;	/* cmd = 0x25 (CONFIG_FARP)
3524 					 * NEW_FEATURE
3525 					 */
3526 	struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ)  */
3527 	struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3528 	CONFIG_PORT_VAR varCfgPort;	/* cmd = 0x88 (CONFIG_PORT)  */
3529 	struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3530 	REG_VPI_VAR varRegVpi;		/* cmd = 0x96 (REG_VPI) */
3531 	UNREG_VPI_VAR varUnregVpi;	/* cmd = 0x97 (UNREG_VPI) */
3532 	ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3533 	struct READ_EVENT_LOG_VAR varRdEventLog;	/* cmd = 0x38
3534 							 * (READ_EVENT_LOG)
3535 							 */
3536 	struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI)     */
3537 } MAILVARIANTS;
3538 
3539 /*
3540  * SLI-2 specific structures
3541  */
3542 
3543 struct lpfc_hgp {
3544 	__le32 cmdPutInx;
3545 	__le32 rspGetInx;
3546 };
3547 
3548 struct lpfc_pgp {
3549 	__le32 cmdGetInx;
3550 	__le32 rspPutInx;
3551 };
3552 
3553 struct sli2_desc {
3554 	uint32_t unused1[16];
3555 	struct lpfc_hgp host[MAX_SLI3_RINGS];
3556 	struct lpfc_pgp port[MAX_SLI3_RINGS];
3557 };
3558 
3559 struct sli3_desc {
3560 	struct lpfc_hgp host[MAX_SLI3_RINGS];
3561 	uint32_t reserved[8];
3562 	uint32_t hbq_put[16];
3563 };
3564 
3565 struct sli3_pgp {
3566 	struct lpfc_pgp port[MAX_SLI3_RINGS];
3567 	uint32_t hbq_get[16];
3568 };
3569 
3570 union sli_var {
3571 	struct sli2_desc	s2;
3572 	struct sli3_desc	s3;
3573 	struct sli3_pgp		s3_pgp;
3574 };
3575 
3576 typedef struct {
3577 #ifdef __BIG_ENDIAN_BITFIELD
3578 	uint16_t mbxStatus;
3579 	uint8_t mbxCommand;
3580 	uint8_t mbxReserved:6;
3581 	uint8_t mbxHc:1;
3582 	uint8_t mbxOwner:1;	/* Low order bit first word */
3583 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3584 	uint8_t mbxOwner:1;	/* Low order bit first word */
3585 	uint8_t mbxHc:1;
3586 	uint8_t mbxReserved:6;
3587 	uint8_t mbxCommand;
3588 	uint16_t mbxStatus;
3589 #endif
3590 
3591 	MAILVARIANTS un;
3592 	union sli_var us;
3593 } MAILBOX_t;
3594 
3595 /*
3596  *    Begin Structure Definitions for IOCB Commands
3597  */
3598 
3599 typedef struct {
3600 #ifdef __BIG_ENDIAN_BITFIELD
3601 	uint8_t statAction;
3602 	uint8_t statRsn;
3603 	uint8_t statBaExp;
3604 	uint8_t statLocalError;
3605 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3606 	uint8_t statLocalError;
3607 	uint8_t statBaExp;
3608 	uint8_t statRsn;
3609 	uint8_t statAction;
3610 #endif
3611 	/* statRsn  P/F_RJT reason codes */
3612 #define RJT_BAD_D_ID       0x01	/* Invalid D_ID field */
3613 #define RJT_BAD_S_ID       0x02	/* Invalid S_ID field */
3614 #define RJT_UNAVAIL_TEMP   0x03	/* N_Port unavailable temp. */
3615 #define RJT_UNAVAIL_PERM   0x04	/* N_Port unavailable perm. */
3616 #define RJT_UNSUP_CLASS    0x05	/* Class not supported */
3617 #define RJT_DELIM_ERR      0x06	/* Delimiter usage error */
3618 #define RJT_UNSUP_TYPE     0x07	/* Type not supported */
3619 #define RJT_BAD_CONTROL    0x08	/* Invalid link conrtol */
3620 #define RJT_BAD_RCTL       0x09	/* R_CTL invalid */
3621 #define RJT_BAD_FCTL       0x0A	/* F_CTL invalid */
3622 #define RJT_BAD_OXID       0x0B	/* OX_ID invalid */
3623 #define RJT_BAD_RXID       0x0C	/* RX_ID invalid */
3624 #define RJT_BAD_SEQID      0x0D	/* SEQ_ID invalid */
3625 #define RJT_BAD_DFCTL      0x0E	/* DF_CTL invalid */
3626 #define RJT_BAD_SEQCNT     0x0F	/* SEQ_CNT invalid */
3627 #define RJT_BAD_PARM       0x10	/* Param. field invalid */
3628 #define RJT_XCHG_ERR       0x11	/* Exchange error */
3629 #define RJT_PROT_ERR       0x12	/* Protocol error */
3630 #define RJT_BAD_LENGTH     0x13	/* Invalid Length */
3631 #define RJT_UNEXPECTED_ACK 0x14	/* Unexpected ACK */
3632 #define RJT_LOGIN_REQUIRED 0x16	/* Login required */
3633 #define RJT_TOO_MANY_SEQ   0x17	/* Excessive sequences */
3634 #define RJT_XCHG_NOT_STRT  0x18	/* Exchange not started */
3635 #define RJT_UNSUP_SEC_HDR  0x19	/* Security hdr not supported */
3636 #define RJT_UNAVAIL_PATH   0x1A	/* Fabric Path not available */
3637 #define RJT_VENDOR_UNIQUE  0xFF	/* Vendor unique error */
3638 
3639 #define IOERR_SUCCESS                 0x00	/* statLocalError */
3640 #define IOERR_MISSING_CONTINUE        0x01
3641 #define IOERR_SEQUENCE_TIMEOUT        0x02
3642 #define IOERR_INTERNAL_ERROR          0x03
3643 #define IOERR_INVALID_RPI             0x04
3644 #define IOERR_NO_XRI                  0x05
3645 #define IOERR_ILLEGAL_COMMAND         0x06
3646 #define IOERR_XCHG_DROPPED            0x07
3647 #define IOERR_ILLEGAL_FIELD           0x08
3648 #define IOERR_BAD_CONTINUE            0x09
3649 #define IOERR_TOO_MANY_BUFFERS        0x0A
3650 #define IOERR_RCV_BUFFER_WAITING      0x0B
3651 #define IOERR_NO_CONNECTION           0x0C
3652 #define IOERR_TX_DMA_FAILED           0x0D
3653 #define IOERR_RX_DMA_FAILED           0x0E
3654 #define IOERR_ILLEGAL_FRAME           0x0F
3655 #define IOERR_EXTRA_DATA              0x10
3656 #define IOERR_NO_RESOURCES            0x11
3657 #define IOERR_RESERVED                0x12
3658 #define IOERR_ILLEGAL_LENGTH          0x13
3659 #define IOERR_UNSUPPORTED_FEATURE     0x14
3660 #define IOERR_ABORT_IN_PROGRESS       0x15
3661 #define IOERR_ABORT_REQUESTED         0x16
3662 #define IOERR_RECEIVE_BUFFER_TIMEOUT  0x17
3663 #define IOERR_LOOP_OPEN_FAILURE       0x18
3664 #define IOERR_RING_RESET              0x19
3665 #define IOERR_LINK_DOWN               0x1A
3666 #define IOERR_CORRUPTED_DATA          0x1B
3667 #define IOERR_CORRUPTED_RPI           0x1C
3668 #define IOERR_OUT_OF_ORDER_DATA       0x1D
3669 #define IOERR_OUT_OF_ORDER_ACK        0x1E
3670 #define IOERR_DUP_FRAME               0x1F
3671 #define IOERR_LINK_CONTROL_FRAME      0x20	/* ACK_N received */
3672 #define IOERR_BAD_HOST_ADDRESS        0x21
3673 #define IOERR_RCV_HDRBUF_WAITING      0x22
3674 #define IOERR_MISSING_HDR_BUFFER      0x23
3675 #define IOERR_MSEQ_CHAIN_CORRUPTED    0x24
3676 #define IOERR_ABORTMULT_REQUESTED     0x25
3677 #define IOERR_BUFFER_SHORTAGE         0x28
3678 #define IOERR_DEFAULT                 0x29
3679 #define IOERR_CNT                     0x2A
3680 #define IOERR_SLER_FAILURE            0x46
3681 #define IOERR_SLER_CMD_RCV_FAILURE    0x47
3682 #define IOERR_SLER_REC_RJT_ERR        0x48
3683 #define IOERR_SLER_REC_SRR_RETRY_ERR  0x49
3684 #define IOERR_SLER_SRR_RJT_ERR        0x4A
3685 #define IOERR_SLER_RRQ_RJT_ERR        0x4C
3686 #define IOERR_SLER_RRQ_RETRY_ERR      0x4D
3687 #define IOERR_SLER_ABTS_ERR           0x4E
3688 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR		0xF0
3689 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR	0xF1
3690 #define IOERR_ELXSEC_CRYPTO_ERROR		0xF2
3691 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR	0xF3
3692 #define IOERR_DRVR_MASK               0x100
3693 #define IOERR_SLI_DOWN                0x101  /* ulpStatus  - Driver defined */
3694 #define IOERR_SLI_BRESET              0x102
3695 #define IOERR_SLI_ABORTED             0x103
3696 #define IOERR_PARAM_MASK              0x1ff
3697 } PARM_ERR;
3698 
3699 typedef union {
3700 	struct {
3701 #ifdef __BIG_ENDIAN_BITFIELD
3702 		uint8_t Rctl;	/* R_CTL field */
3703 		uint8_t Type;	/* TYPE field */
3704 		uint8_t Dfctl;	/* DF_CTL field */
3705 		uint8_t Fctl;	/* Bits 0-7 of IOCB word 5 */
3706 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3707 		uint8_t Fctl;	/* Bits 0-7 of IOCB word 5 */
3708 		uint8_t Dfctl;	/* DF_CTL field */
3709 		uint8_t Type;	/* TYPE field */
3710 		uint8_t Rctl;	/* R_CTL field */
3711 #endif
3712 
3713 #define BC      0x02		/* Broadcast Received  - Fctl */
3714 #define SI      0x04		/* Sequence Initiative */
3715 #define LA      0x08		/* Ignore Link Attention state */
3716 #define LS      0x80		/* Last Sequence */
3717 	} hcsw;
3718 	uint32_t reserved;
3719 } WORD5;
3720 
3721 /* IOCB Command template for a generic response */
3722 typedef struct {
3723 	uint32_t reserved[4];
3724 	PARM_ERR perr;
3725 } GENERIC_RSP;
3726 
3727 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3728 typedef struct {
3729 	struct ulp_bde xrsqbde[2];
3730 	uint32_t xrsqRo;	/* Starting Relative Offset */
3731 	WORD5 w5;		/* Header control/status word */
3732 } XR_SEQ_FIELDS;
3733 
3734 /* IOCB Command template for ELS_REQUEST */
3735 typedef struct {
3736 	struct ulp_bde elsReq;
3737 	struct ulp_bde elsRsp;
3738 
3739 #ifdef __BIG_ENDIAN_BITFIELD
3740 	uint32_t word4Rsvd:7;
3741 	uint32_t fl:1;
3742 	uint32_t myID:24;
3743 	uint32_t word5Rsvd:8;
3744 	uint32_t remoteID:24;
3745 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3746 	uint32_t myID:24;
3747 	uint32_t fl:1;
3748 	uint32_t word4Rsvd:7;
3749 	uint32_t remoteID:24;
3750 	uint32_t word5Rsvd:8;
3751 #endif
3752 } ELS_REQUEST;
3753 
3754 /* IOCB Command template for RCV_ELS_REQ */
3755 typedef struct {
3756 	struct ulp_bde elsReq[2];
3757 	uint32_t parmRo;
3758 
3759 #ifdef __BIG_ENDIAN_BITFIELD
3760 	uint32_t word5Rsvd:8;
3761 	uint32_t remoteID:24;
3762 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3763 	uint32_t remoteID:24;
3764 	uint32_t word5Rsvd:8;
3765 #endif
3766 } RCV_ELS_REQ;
3767 
3768 /* IOCB Command template for ABORT / CLOSE_XRI */
3769 typedef struct {
3770 	uint32_t rsvd[3];
3771 	uint32_t abortType;
3772 #define ABORT_TYPE_ABTX  0x00000000
3773 #define ABORT_TYPE_ABTS  0x00000001
3774 	uint32_t parm;
3775 #ifdef __BIG_ENDIAN_BITFIELD
3776 	uint16_t abortContextTag; /* ulpContext from command to abort/close */
3777 	uint16_t abortIoTag;	/* ulpIoTag from command to abort/close */
3778 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3779 	uint16_t abortIoTag;	/* ulpIoTag from command to abort/close */
3780 	uint16_t abortContextTag; /* ulpContext from command to abort/close */
3781 #endif
3782 } AC_XRI;
3783 
3784 /* IOCB Command template for ABORT_MXRI64 */
3785 typedef struct {
3786 	uint32_t rsvd[3];
3787 	uint32_t abortType;
3788 	uint32_t parm;
3789 	uint32_t iotag32;
3790 } A_MXRI64;
3791 
3792 /* IOCB Command template for GET_RPI */
3793 typedef struct {
3794 	uint32_t rsvd[4];
3795 	uint32_t parmRo;
3796 #ifdef __BIG_ENDIAN_BITFIELD
3797 	uint32_t word5Rsvd:8;
3798 	uint32_t remoteID:24;
3799 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3800 	uint32_t remoteID:24;
3801 	uint32_t word5Rsvd:8;
3802 #endif
3803 } GET_RPI;
3804 
3805 /* IOCB Command template for all FCP Initiator commands */
3806 typedef struct {
3807 	struct ulp_bde fcpi_cmnd;	/* FCP_CMND payload descriptor */
3808 	struct ulp_bde fcpi_rsp;	/* Rcv buffer */
3809 	uint32_t fcpi_parm;
3810 	uint32_t fcpi_XRdy;	/* transfer ready for IWRITE */
3811 } FCPI_FIELDS;
3812 
3813 /* IOCB Command template for all FCP Target commands */
3814 typedef struct {
3815 	struct ulp_bde fcpt_Buffer[2];	/* FCP_CMND payload descriptor */
3816 	uint32_t fcpt_Offset;
3817 	uint32_t fcpt_Length;	/* transfer ready for IWRITE */
3818 } FCPT_FIELDS;
3819 
3820 /* SLI-2 IOCB structure definitions */
3821 
3822 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3823 typedef struct {
3824 	ULP_BDL bdl;
3825 	uint32_t xrsqRo;	/* Starting Relative Offset */
3826 	WORD5 w5;		/* Header control/status word */
3827 } XMT_SEQ_FIELDS64;
3828 
3829 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3830 #define xmit_els_remoteID xrsqRo
3831 
3832 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3833 typedef struct {
3834 	struct ulp_bde64 rcvBde;
3835 	uint32_t rsvd1;
3836 	uint32_t xrsqRo;	/* Starting Relative Offset */
3837 	WORD5 w5;		/* Header control/status word */
3838 } RCV_SEQ_FIELDS64;
3839 
3840 /* IOCB Command template for ELS_REQUEST64 */
3841 typedef struct {
3842 	ULP_BDL bdl;
3843 #ifdef __BIG_ENDIAN_BITFIELD
3844 	uint32_t word4Rsvd:7;
3845 	uint32_t fl:1;
3846 	uint32_t myID:24;
3847 	uint32_t word5Rsvd:8;
3848 	uint32_t remoteID:24;
3849 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3850 	uint32_t myID:24;
3851 	uint32_t fl:1;
3852 	uint32_t word4Rsvd:7;
3853 	uint32_t remoteID:24;
3854 	uint32_t word5Rsvd:8;
3855 #endif
3856 } ELS_REQUEST64;
3857 
3858 /* IOCB Command template for GEN_REQUEST64 */
3859 typedef struct {
3860 	ULP_BDL bdl;
3861 	uint32_t xrsqRo;	/* Starting Relative Offset */
3862 	WORD5 w5;		/* Header control/status word */
3863 } GEN_REQUEST64;
3864 
3865 /* IOCB Command template for RCV_ELS_REQ64 */
3866 typedef struct {
3867 	struct ulp_bde64 elsReq;
3868 	uint32_t rcvd1;
3869 	uint32_t parmRo;
3870 
3871 #ifdef __BIG_ENDIAN_BITFIELD
3872 	uint32_t word5Rsvd:8;
3873 	uint32_t remoteID:24;
3874 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3875 	uint32_t remoteID:24;
3876 	uint32_t word5Rsvd:8;
3877 #endif
3878 } RCV_ELS_REQ64;
3879 
3880 /* IOCB Command template for RCV_SEQ64 */
3881 struct rcv_seq64 {
3882 	struct ulp_bde64 elsReq;
3883 	uint32_t hbq_1;
3884 	uint32_t parmRo;
3885 #ifdef __BIG_ENDIAN_BITFIELD
3886 	uint32_t rctl:8;
3887 	uint32_t type:8;
3888 	uint32_t dfctl:8;
3889 	uint32_t ls:1;
3890 	uint32_t fs:1;
3891 	uint32_t rsvd2:3;
3892 	uint32_t si:1;
3893 	uint32_t bc:1;
3894 	uint32_t rsvd3:1;
3895 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3896 	uint32_t rsvd3:1;
3897 	uint32_t bc:1;
3898 	uint32_t si:1;
3899 	uint32_t rsvd2:3;
3900 	uint32_t fs:1;
3901 	uint32_t ls:1;
3902 	uint32_t dfctl:8;
3903 	uint32_t type:8;
3904 	uint32_t rctl:8;
3905 #endif
3906 };
3907 
3908 /* IOCB Command template for all 64 bit FCP Initiator commands */
3909 typedef struct {
3910 	ULP_BDL bdl;
3911 	uint32_t fcpi_parm;
3912 	uint32_t fcpi_XRdy;	/* transfer ready for IWRITE */
3913 } FCPI_FIELDS64;
3914 
3915 /* IOCB Command template for all 64 bit FCP Target commands */
3916 typedef struct {
3917 	ULP_BDL bdl;
3918 	uint32_t fcpt_Offset;
3919 	uint32_t fcpt_Length;	/* transfer ready for IWRITE */
3920 } FCPT_FIELDS64;
3921 
3922 /* IOCB Command template for Async Status iocb commands */
3923 typedef struct {
3924 	uint32_t rsvd[4];
3925 	uint32_t param;
3926 #ifdef __BIG_ENDIAN_BITFIELD
3927 	uint16_t evt_code;		/* High order bits word 5 */
3928 	uint16_t sub_ctxt_tag;		/* Low  order bits word 5 */
3929 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3930 	uint16_t sub_ctxt_tag;		/* High order bits word 5 */
3931 	uint16_t evt_code;		/* Low  order bits word 5 */
3932 #endif
3933 } ASYNCSTAT_FIELDS;
3934 #define ASYNC_TEMP_WARN		0x100
3935 #define ASYNC_TEMP_SAFE		0x101
3936 #define ASYNC_STATUS_CN		0x102
3937 
3938 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3939    or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3940 
3941 struct rcv_sli3 {
3942 #ifdef __BIG_ENDIAN_BITFIELD
3943 	uint16_t ox_id;
3944 	uint16_t seq_cnt;
3945 
3946 	uint16_t vpi;
3947 	uint16_t word9Rsvd;
3948 #else  /*  __LITTLE_ENDIAN */
3949 	uint16_t seq_cnt;
3950 	uint16_t ox_id;
3951 
3952 	uint16_t word9Rsvd;
3953 	uint16_t vpi;
3954 #endif
3955 	uint32_t word10Rsvd;
3956 	uint32_t acc_len;      /* accumulated length */
3957 	struct ulp_bde64 bde2;
3958 };
3959 
3960 /* Structure used for a single HBQ entry */
3961 struct lpfc_hbq_entry {
3962 	struct ulp_bde64 bde;
3963 	uint32_t buffer_tag;
3964 };
3965 
3966 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3967 typedef struct {
3968 	struct lpfc_hbq_entry   buff;
3969 	uint32_t                rsvd;
3970 	uint32_t		rsvd1;
3971 } QUE_XRI64_CX_FIELDS;
3972 
3973 struct que_xri64cx_ext_fields {
3974 	uint32_t	iotag64_low;
3975 	uint32_t	iotag64_high;
3976 	uint32_t	ebde_count;
3977 	uint32_t	rsvd;
3978 	struct lpfc_hbq_entry	buff[5];
3979 };
3980 
3981 struct sli3_bg_fields {
3982 	uint32_t filler[6];	/* word 8-13 in IOCB */
3983 	uint32_t bghm;		/* word 14 - BlockGuard High Water Mark */
3984 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3985 #define BGS_BIDIR_BG_PROF_MASK		0xff000000
3986 #define BGS_BIDIR_BG_PROF_SHIFT		24
3987 #define BGS_BIDIR_ERR_COND_FLAGS_MASK	0x003f0000
3988 #define BGS_BIDIR_ERR_COND_SHIFT	16
3989 #define BGS_BG_PROFILE_MASK		0x0000ff00
3990 #define BGS_BG_PROFILE_SHIFT		8
3991 #define BGS_INVALID_PROF_MASK		0x00000020
3992 #define BGS_INVALID_PROF_SHIFT		5
3993 #define BGS_UNINIT_DIF_BLOCK_MASK	0x00000010
3994 #define BGS_UNINIT_DIF_BLOCK_SHIFT	4
3995 #define BGS_HI_WATER_MARK_PRESENT_MASK	0x00000008
3996 #define BGS_HI_WATER_MARK_PRESENT_SHIFT	3
3997 #define BGS_REFTAG_ERR_MASK		0x00000004
3998 #define BGS_REFTAG_ERR_SHIFT		2
3999 #define BGS_APPTAG_ERR_MASK		0x00000002
4000 #define BGS_APPTAG_ERR_SHIFT		1
4001 #define BGS_GUARD_ERR_MASK		0x00000001
4002 #define BGS_GUARD_ERR_SHIFT		0
4003 	uint32_t bgstat;	/* word 15 - BlockGuard Status */
4004 };
4005 
4006 static inline uint32_t
lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)4007 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
4008 {
4009 	return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
4010 				BGS_BIDIR_BG_PROF_SHIFT;
4011 }
4012 
4013 static inline uint32_t
lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)4014 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
4015 {
4016 	return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
4017 				BGS_BIDIR_ERR_COND_SHIFT;
4018 }
4019 
4020 static inline uint32_t
lpfc_bgs_get_bg_prof(uint32_t bgstat)4021 lpfc_bgs_get_bg_prof(uint32_t bgstat)
4022 {
4023 	return (bgstat & BGS_BG_PROFILE_MASK) >>
4024 				BGS_BG_PROFILE_SHIFT;
4025 }
4026 
4027 static inline uint32_t
lpfc_bgs_get_invalid_prof(uint32_t bgstat)4028 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
4029 {
4030 	return (bgstat & BGS_INVALID_PROF_MASK) >>
4031 				BGS_INVALID_PROF_SHIFT;
4032 }
4033 
4034 static inline uint32_t
lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)4035 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
4036 {
4037 	return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
4038 				BGS_UNINIT_DIF_BLOCK_SHIFT;
4039 }
4040 
4041 static inline uint32_t
lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)4042 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
4043 {
4044 	return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
4045 				BGS_HI_WATER_MARK_PRESENT_SHIFT;
4046 }
4047 
4048 static inline uint32_t
lpfc_bgs_get_reftag_err(uint32_t bgstat)4049 lpfc_bgs_get_reftag_err(uint32_t bgstat)
4050 {
4051 	return (bgstat & BGS_REFTAG_ERR_MASK) >>
4052 				BGS_REFTAG_ERR_SHIFT;
4053 }
4054 
4055 static inline uint32_t
lpfc_bgs_get_apptag_err(uint32_t bgstat)4056 lpfc_bgs_get_apptag_err(uint32_t bgstat)
4057 {
4058 	return (bgstat & BGS_APPTAG_ERR_MASK) >>
4059 				BGS_APPTAG_ERR_SHIFT;
4060 }
4061 
4062 static inline uint32_t
lpfc_bgs_get_guard_err(uint32_t bgstat)4063 lpfc_bgs_get_guard_err(uint32_t bgstat)
4064 {
4065 	return (bgstat & BGS_GUARD_ERR_MASK) >>
4066 				BGS_GUARD_ERR_SHIFT;
4067 }
4068 
4069 #define LPFC_EXT_DATA_BDE_COUNT 3
4070 struct fcp_irw_ext {
4071 	uint32_t	io_tag64_low;
4072 	uint32_t	io_tag64_high;
4073 #ifdef __BIG_ENDIAN_BITFIELD
4074 	uint8_t		reserved1;
4075 	uint8_t		reserved2;
4076 	uint8_t		reserved3;
4077 	uint8_t		ebde_count;
4078 #else  /* __LITTLE_ENDIAN */
4079 	uint8_t		ebde_count;
4080 	uint8_t		reserved3;
4081 	uint8_t		reserved2;
4082 	uint8_t		reserved1;
4083 #endif
4084 	uint32_t	reserved4;
4085 	struct ulp_bde64 rbde;		/* response bde */
4086 	struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT];	/* data BDE or BPL */
4087 	uint8_t icd[32];		/* immediate command data (32 bytes) */
4088 };
4089 
4090 typedef struct _IOCB {	/* IOCB structure */
4091 	union {
4092 		GENERIC_RSP grsp;	/* Generic response */
4093 		XR_SEQ_FIELDS xrseq;	/* XMIT / BCAST / RCV_SEQUENCE cmd */
4094 		struct ulp_bde cont[3];	/* up to 3 continuation bdes */
4095 		RCV_ELS_REQ rcvels;	/* RCV_ELS_REQ template */
4096 		AC_XRI acxri;	/* ABORT / CLOSE_XRI template */
4097 		A_MXRI64 amxri;	/* abort multiple xri command overlay */
4098 		GET_RPI getrpi;	/* GET_RPI template */
4099 		FCPI_FIELDS fcpi;	/* FCP Initiator template */
4100 		FCPT_FIELDS fcpt;	/* FCP target template */
4101 
4102 		/* SLI-2 structures */
4103 
4104 		struct ulp_bde64 cont64[2];  /* up to 2 64 bit continuation
4105 					      * bde_64s */
4106 		ELS_REQUEST64 elsreq64;	/* ELS_REQUEST template */
4107 		GEN_REQUEST64 genreq64;	/* GEN_REQUEST template */
4108 		RCV_ELS_REQ64 rcvels64;	/* RCV_ELS_REQ template */
4109 		XMT_SEQ_FIELDS64 xseq64;	/* XMIT / BCAST cmd */
4110 		FCPI_FIELDS64 fcpi64;	/* FCP 64 bit Initiator template */
4111 		FCPT_FIELDS64 fcpt64;	/* FCP 64 bit target template */
4112 		ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
4113 		QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
4114 		struct rcv_seq64 rcvseq64;	/* RCV_SEQ64 and RCV_CONT64 */
4115 		struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
4116 		uint32_t ulpWord[IOCB_WORD_SZ - 2];	/* generic 6 'words' */
4117 	} un;
4118 	union {
4119 		struct {
4120 #ifdef __BIG_ENDIAN_BITFIELD
4121 			uint16_t ulpContext;	/* High order bits word 6 */
4122 			uint16_t ulpIoTag;	/* Low  order bits word 6 */
4123 #else	/*  __LITTLE_ENDIAN_BITFIELD */
4124 			uint16_t ulpIoTag;	/* Low  order bits word 6 */
4125 			uint16_t ulpContext;	/* High order bits word 6 */
4126 #endif
4127 		} t1;
4128 		struct {
4129 #ifdef __BIG_ENDIAN_BITFIELD
4130 			uint16_t ulpContext;	/* High order bits word 6 */
4131 			uint16_t ulpIoTag1:2;	/* Low  order bits word 6 */
4132 			uint16_t ulpIoTag0:14;	/* Low  order bits word 6 */
4133 #else	/*  __LITTLE_ENDIAN_BITFIELD */
4134 			uint16_t ulpIoTag0:14;	/* Low  order bits word 6 */
4135 			uint16_t ulpIoTag1:2;	/* Low  order bits word 6 */
4136 			uint16_t ulpContext;	/* High order bits word 6 */
4137 #endif
4138 		} t2;
4139 	} un1;
4140 #define ulpContext un1.t1.ulpContext
4141 #define ulpIoTag   un1.t1.ulpIoTag
4142 #define ulpIoTag0  un1.t2.ulpIoTag0
4143 
4144 #ifdef __BIG_ENDIAN_BITFIELD
4145 	uint32_t ulpTimeout:8;
4146 	uint32_t ulpXS:1;
4147 	uint32_t ulpFCP2Rcvy:1;
4148 	uint32_t ulpPU:2;
4149 	uint32_t ulpIr:1;
4150 	uint32_t ulpClass:3;
4151 	uint32_t ulpCommand:8;
4152 	uint32_t ulpStatus:4;
4153 	uint32_t ulpBdeCount:2;
4154 	uint32_t ulpLe:1;
4155 	uint32_t ulpOwner:1;	/* Low order bit word 7 */
4156 #else	/*  __LITTLE_ENDIAN_BITFIELD */
4157 	uint32_t ulpOwner:1;	/* Low order bit word 7 */
4158 	uint32_t ulpLe:1;
4159 	uint32_t ulpBdeCount:2;
4160 	uint32_t ulpStatus:4;
4161 	uint32_t ulpCommand:8;
4162 	uint32_t ulpClass:3;
4163 	uint32_t ulpIr:1;
4164 	uint32_t ulpPU:2;
4165 	uint32_t ulpFCP2Rcvy:1;
4166 	uint32_t ulpXS:1;
4167 	uint32_t ulpTimeout:8;
4168 #endif
4169 
4170 	union {
4171 		struct rcv_sli3 rcvsli3; /* words 8 - 15 */
4172 
4173 		/* words 8-31 used for que_xri_cx iocb */
4174 		struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4175 		struct fcp_irw_ext fcp_ext;
4176 		uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
4177 
4178 		/* words 8-15 for BlockGuard */
4179 		struct sli3_bg_fields sli3_bg;
4180 	} unsli3;
4181 
4182 #define ulpCt_h ulpXS
4183 #define ulpCt_l ulpFCP2Rcvy
4184 
4185 #define IOCB_FCP	   1	/* IOCB is used for FCP ELS cmds-ulpRsvByte */
4186 #define IOCB_IP		   2	/* IOCB is used for IP ELS cmds */
4187 #define PARM_UNUSED        0	/* PU field (Word 4) not used */
4188 #define PARM_REL_OFF       1	/* PU field (Word 4) = R. O. */
4189 #define PARM_READ_CHECK    2	/* PU field (Word 4) = Data Transfer Length */
4190 #define PARM_NPIV_DID	   3
4191 #define CLASS1             0	/* Class 1 */
4192 #define CLASS2             1	/* Class 2 */
4193 #define CLASS3             2	/* Class 3 */
4194 #define CLASS_FCP_INTERMIX 7	/* FCP Data->Cls 1, all else->Cls 2 */
4195 
4196 #define IOSTAT_SUCCESS         0x0	/* ulpStatus  - HBA defined */
4197 #define IOSTAT_FCP_RSP_ERROR   0x1
4198 #define IOSTAT_REMOTE_STOP     0x2
4199 #define IOSTAT_LOCAL_REJECT    0x3
4200 #define IOSTAT_NPORT_RJT       0x4
4201 #define IOSTAT_FABRIC_RJT      0x5
4202 #define IOSTAT_NPORT_BSY       0x6
4203 #define IOSTAT_FABRIC_BSY      0x7
4204 #define IOSTAT_INTERMED_RSP    0x8
4205 #define IOSTAT_LS_RJT          0x9
4206 #define IOSTAT_BA_RJT          0xA
4207 #define IOSTAT_RSVD1           0xB
4208 #define IOSTAT_RSVD2           0xC
4209 #define IOSTAT_RSVD3           0xD
4210 #define IOSTAT_RSVD4           0xE
4211 #define IOSTAT_NEED_BUFFER     0xF
4212 #define IOSTAT_DRIVER_REJECT   0x10   /* ulpStatus  - Driver defined */
4213 #define IOSTAT_DEFAULT         0xF    /* Same as rsvd5 for now */
4214 #define IOSTAT_CNT             0x11
4215 
4216 } IOCB_t;
4217 
4218 
4219 #define SLI1_SLIM_SIZE   (4 * 1024)
4220 
4221 /* Up to 498 IOCBs will fit into 16k
4222  * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
4223  */
4224 #define SLI2_SLIM_SIZE   (64 * 1024)
4225 
4226 /* Maximum IOCBs that will fit in SLI2 slim */
4227 #define MAX_SLI2_IOCB    498
4228 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4229 			    (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4230 			    sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4231 
4232 /* HBQ entries are 4 words each = 4k */
4233 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) *  \
4234 			     lpfc_sli_hbq_count())
4235 
4236 struct lpfc_sli2_slim {
4237 	MAILBOX_t mbx;
4238 	uint32_t  mbx_ext_words[MAILBOX_EXT_WSIZE];
4239 	PCB_t pcb;
4240 	IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4241 };
4242 
4243 /*
4244  * This function checks PCI device to allow special handling for LC HBAs.
4245  *
4246  * Parameters:
4247  * device : struct pci_dev 's device field
4248  *
4249  * return 1 => TRUE
4250  *        0 => FALSE
4251  */
4252 static inline int
lpfc_is_LC_HBA(unsigned short device)4253 lpfc_is_LC_HBA(unsigned short device)
4254 {
4255 	if ((device == PCI_DEVICE_ID_TFLY) ||
4256 	    (device == PCI_DEVICE_ID_PFLY) ||
4257 	    (device == PCI_DEVICE_ID_LP101) ||
4258 	    (device == PCI_DEVICE_ID_BMID) ||
4259 	    (device == PCI_DEVICE_ID_BSMB) ||
4260 	    (device == PCI_DEVICE_ID_ZMID) ||
4261 	    (device == PCI_DEVICE_ID_ZSMB) ||
4262 	    (device == PCI_DEVICE_ID_SAT_MID) ||
4263 	    (device == PCI_DEVICE_ID_SAT_SMB) ||
4264 	    (device == PCI_DEVICE_ID_RFLY))
4265 		return 1;
4266 	else
4267 		return 0;
4268 }
4269 
4270 /*
4271  * Determine if an IOCB failed because of a link event or firmware reset.
4272  */
4273 
4274 static inline int
lpfc_error_lost_link(IOCB_t * iocbp)4275 lpfc_error_lost_link(IOCB_t *iocbp)
4276 {
4277 	return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
4278 		(iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
4279 		 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
4280 		 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
4281 }
4282 
4283 #define MENLO_TRANSPORT_TYPE 0xfe
4284 #define MENLO_CONTEXT 0
4285 #define MENLO_PU 3
4286 #define MENLO_TIMEOUT 30
4287 #define SETVAR_MLOMNT 0x103107
4288 #define SETVAR_MLORST 0x103007
4289 
4290 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
4291