1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
4 *
5 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
6 * Author: Thomas Dahlmann
7 */
8
9 /*
10 * This file does the core driver implementation for the UDC that is based
11 * on Synopsys device controller IP (different than HS OTG IP) that is either
12 * connected through PCI bus or integrated to SoC platforms.
13 */
14
15 /* Driver strings */
16 #define UDC_MOD_DESCRIPTION "Synopsys USB Device Controller"
17 #define UDC_DRIVER_VERSION_STRING "01.00.0206"
18
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/kernel.h>
22 #include <linux/delay.h>
23 #include <linux/ioport.h>
24 #include <linux/sched.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/timer.h>
28 #include <linux/list.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioctl.h>
31 #include <linux/fs.h>
32 #include <linux/dmapool.h>
33 #include <linux/prefetch.h>
34 #include <linux/moduleparam.h>
35 #include <asm/byteorder.h>
36 #include <asm/unaligned.h>
37 #include "amd5536udc.h"
38
39 static void udc_tasklet_disconnect(unsigned long);
40 static void udc_setup_endpoints(struct udc *dev);
41 static void udc_soft_reset(struct udc *dev);
42 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
43 static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
44
45 /* description */
46 static const char mod_desc[] = UDC_MOD_DESCRIPTION;
47 static const char name[] = "udc";
48
49 /* structure to hold endpoint function pointers */
50 static const struct usb_ep_ops udc_ep_ops;
51
52 /* received setup data */
53 static union udc_setup_data setup_data;
54
55 /* pointer to device object */
56 static struct udc *udc;
57
58 /* irq spin lock for soft reset */
59 static DEFINE_SPINLOCK(udc_irq_spinlock);
60 /* stall spin lock */
61 static DEFINE_SPINLOCK(udc_stall_spinlock);
62
63 /*
64 * slave mode: pending bytes in rx fifo after nyet,
65 * used if EPIN irq came but no req was available
66 */
67 static unsigned int udc_rxfifo_pending;
68
69 /* count soft resets after suspend to avoid loop */
70 static int soft_reset_occured;
71 static int soft_reset_after_usbreset_occured;
72
73 /* timer */
74 static struct timer_list udc_timer;
75 static int stop_timer;
76
77 /* set_rde -- Is used to control enabling of RX DMA. Problem is
78 * that UDC has only one bit (RDE) to enable/disable RX DMA for
79 * all OUT endpoints. So we have to handle race conditions like
80 * when OUT data reaches the fifo but no request was queued yet.
81 * This cannot be solved by letting the RX DMA disabled until a
82 * request gets queued because there may be other OUT packets
83 * in the FIFO (important for not blocking control traffic).
84 * The value of set_rde controls the correspondig timer.
85 *
86 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
87 * set_rde 0 == do not touch RDE, do no start the RDE timer
88 * set_rde 1 == timer function will look whether FIFO has data
89 * set_rde 2 == set by timer function to enable RX DMA on next call
90 */
91 static int set_rde = -1;
92
93 static DECLARE_COMPLETION(on_exit);
94 static struct timer_list udc_pollstall_timer;
95 static int stop_pollstall_timer;
96 static DECLARE_COMPLETION(on_pollstall_exit);
97
98 /* tasklet for usb disconnect */
99 static DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
100 (unsigned long) &udc);
101
102
103 /* endpoint names used for print */
104 static const char ep0_string[] = "ep0in";
105 static const struct {
106 const char *name;
107 const struct usb_ep_caps caps;
108 } ep_info[] = {
109 #define EP_INFO(_name, _caps) \
110 { \
111 .name = _name, \
112 .caps = _caps, \
113 }
114
115 EP_INFO(ep0_string,
116 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_IN)),
117 EP_INFO("ep1in-int",
118 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
119 EP_INFO("ep2in-bulk",
120 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
121 EP_INFO("ep3in-bulk",
122 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
123 EP_INFO("ep4in-bulk",
124 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
125 EP_INFO("ep5in-bulk",
126 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
127 EP_INFO("ep6in-bulk",
128 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
129 EP_INFO("ep7in-bulk",
130 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
131 EP_INFO("ep8in-bulk",
132 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
133 EP_INFO("ep9in-bulk",
134 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
135 EP_INFO("ep10in-bulk",
136 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
137 EP_INFO("ep11in-bulk",
138 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
139 EP_INFO("ep12in-bulk",
140 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
141 EP_INFO("ep13in-bulk",
142 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
143 EP_INFO("ep14in-bulk",
144 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
145 EP_INFO("ep15in-bulk",
146 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
147 EP_INFO("ep0out",
148 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_OUT)),
149 EP_INFO("ep1out-bulk",
150 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
151 EP_INFO("ep2out-bulk",
152 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
153 EP_INFO("ep3out-bulk",
154 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
155 EP_INFO("ep4out-bulk",
156 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
157 EP_INFO("ep5out-bulk",
158 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
159 EP_INFO("ep6out-bulk",
160 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
161 EP_INFO("ep7out-bulk",
162 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
163 EP_INFO("ep8out-bulk",
164 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
165 EP_INFO("ep9out-bulk",
166 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
167 EP_INFO("ep10out-bulk",
168 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
169 EP_INFO("ep11out-bulk",
170 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
171 EP_INFO("ep12out-bulk",
172 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
173 EP_INFO("ep13out-bulk",
174 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
175 EP_INFO("ep14out-bulk",
176 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
177 EP_INFO("ep15out-bulk",
178 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
179
180 #undef EP_INFO
181 };
182
183 /* buffer fill mode */
184 static int use_dma_bufferfill_mode;
185 /* tx buffer size for high speed */
186 static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
187
188 /*---------------------------------------------------------------------------*/
189 /* Prints UDC device registers and endpoint irq registers */
print_regs(struct udc * dev)190 static void print_regs(struct udc *dev)
191 {
192 DBG(dev, "------- Device registers -------\n");
193 DBG(dev, "dev config = %08x\n", readl(&dev->regs->cfg));
194 DBG(dev, "dev control = %08x\n", readl(&dev->regs->ctl));
195 DBG(dev, "dev status = %08x\n", readl(&dev->regs->sts));
196 DBG(dev, "\n");
197 DBG(dev, "dev int's = %08x\n", readl(&dev->regs->irqsts));
198 DBG(dev, "dev intmask = %08x\n", readl(&dev->regs->irqmsk));
199 DBG(dev, "\n");
200 DBG(dev, "dev ep int's = %08x\n", readl(&dev->regs->ep_irqsts));
201 DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
202 DBG(dev, "\n");
203 DBG(dev, "USE DMA = %d\n", use_dma);
204 if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
205 DBG(dev, "DMA mode = PPBNDU (packet per buffer "
206 "WITHOUT desc. update)\n");
207 dev_info(dev->dev, "DMA mode (%s)\n", "PPBNDU");
208 } else if (use_dma && use_dma_ppb && use_dma_ppb_du) {
209 DBG(dev, "DMA mode = PPBDU (packet per buffer "
210 "WITH desc. update)\n");
211 dev_info(dev->dev, "DMA mode (%s)\n", "PPBDU");
212 }
213 if (use_dma && use_dma_bufferfill_mode) {
214 DBG(dev, "DMA mode = BF (buffer fill mode)\n");
215 dev_info(dev->dev, "DMA mode (%s)\n", "BF");
216 }
217 if (!use_dma)
218 dev_info(dev->dev, "FIFO mode\n");
219 DBG(dev, "-------------------------------------------------------\n");
220 }
221
222 /* Masks unused interrupts */
udc_mask_unused_interrupts(struct udc * dev)223 int udc_mask_unused_interrupts(struct udc *dev)
224 {
225 u32 tmp;
226
227 /* mask all dev interrupts */
228 tmp = AMD_BIT(UDC_DEVINT_SVC) |
229 AMD_BIT(UDC_DEVINT_ENUM) |
230 AMD_BIT(UDC_DEVINT_US) |
231 AMD_BIT(UDC_DEVINT_UR) |
232 AMD_BIT(UDC_DEVINT_ES) |
233 AMD_BIT(UDC_DEVINT_SI) |
234 AMD_BIT(UDC_DEVINT_SOF)|
235 AMD_BIT(UDC_DEVINT_SC);
236 writel(tmp, &dev->regs->irqmsk);
237
238 /* mask all ep interrupts */
239 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
240
241 return 0;
242 }
243 EXPORT_SYMBOL_GPL(udc_mask_unused_interrupts);
244
245 /* Enables endpoint 0 interrupts */
udc_enable_ep0_interrupts(struct udc * dev)246 static int udc_enable_ep0_interrupts(struct udc *dev)
247 {
248 u32 tmp;
249
250 DBG(dev, "udc_enable_ep0_interrupts()\n");
251
252 /* read irq mask */
253 tmp = readl(&dev->regs->ep_irqmsk);
254 /* enable ep0 irq's */
255 tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
256 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
257 writel(tmp, &dev->regs->ep_irqmsk);
258
259 return 0;
260 }
261
262 /* Enables device interrupts for SET_INTF and SET_CONFIG */
udc_enable_dev_setup_interrupts(struct udc * dev)263 int udc_enable_dev_setup_interrupts(struct udc *dev)
264 {
265 u32 tmp;
266
267 DBG(dev, "enable device interrupts for setup data\n");
268
269 /* read irq mask */
270 tmp = readl(&dev->regs->irqmsk);
271
272 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
273 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
274 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
275 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
276 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
277 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
278 writel(tmp, &dev->regs->irqmsk);
279
280 return 0;
281 }
282 EXPORT_SYMBOL_GPL(udc_enable_dev_setup_interrupts);
283
284 /* Calculates fifo start of endpoint based on preceding endpoints */
udc_set_txfifo_addr(struct udc_ep * ep)285 static int udc_set_txfifo_addr(struct udc_ep *ep)
286 {
287 struct udc *dev;
288 u32 tmp;
289 int i;
290
291 if (!ep || !(ep->in))
292 return -EINVAL;
293
294 dev = ep->dev;
295 ep->txfifo = dev->txfifo;
296
297 /* traverse ep's */
298 for (i = 0; i < ep->num; i++) {
299 if (dev->ep[i].regs) {
300 /* read fifo size */
301 tmp = readl(&dev->ep[i].regs->bufin_framenum);
302 tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
303 ep->txfifo += tmp;
304 }
305 }
306 return 0;
307 }
308
309 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
310 static u32 cnak_pending;
311
UDC_QUEUE_CNAK(struct udc_ep * ep,unsigned num)312 static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
313 {
314 if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
315 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
316 cnak_pending |= 1 << (num);
317 ep->naking = 1;
318 } else
319 cnak_pending = cnak_pending & (~(1 << (num)));
320 }
321
322
323 /* Enables endpoint, is called by gadget driver */
324 static int
udc_ep_enable(struct usb_ep * usbep,const struct usb_endpoint_descriptor * desc)325 udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
326 {
327 struct udc_ep *ep;
328 struct udc *dev;
329 u32 tmp;
330 unsigned long iflags;
331 u8 udc_csr_epix;
332 unsigned maxpacket;
333
334 if (!usbep
335 || usbep->name == ep0_string
336 || !desc
337 || desc->bDescriptorType != USB_DT_ENDPOINT)
338 return -EINVAL;
339
340 ep = container_of(usbep, struct udc_ep, ep);
341 dev = ep->dev;
342
343 DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
344
345 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
346 return -ESHUTDOWN;
347
348 spin_lock_irqsave(&dev->lock, iflags);
349 ep->ep.desc = desc;
350
351 ep->halted = 0;
352
353 /* set traffic type */
354 tmp = readl(&dev->ep[ep->num].regs->ctl);
355 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
356 writel(tmp, &dev->ep[ep->num].regs->ctl);
357
358 /* set max packet size */
359 maxpacket = usb_endpoint_maxp(desc);
360 tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
361 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
362 ep->ep.maxpacket = maxpacket;
363 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
364
365 /* IN ep */
366 if (ep->in) {
367
368 /* ep ix in UDC CSR register space */
369 udc_csr_epix = ep->num;
370
371 /* set buffer size (tx fifo entries) */
372 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
373 /* double buffering: fifo size = 2 x max packet size */
374 tmp = AMD_ADDBITS(
375 tmp,
376 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
377 / UDC_DWORD_BYTES,
378 UDC_EPIN_BUFF_SIZE);
379 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
380
381 /* calc. tx fifo base addr */
382 udc_set_txfifo_addr(ep);
383
384 /* flush fifo */
385 tmp = readl(&ep->regs->ctl);
386 tmp |= AMD_BIT(UDC_EPCTL_F);
387 writel(tmp, &ep->regs->ctl);
388
389 /* OUT ep */
390 } else {
391 /* ep ix in UDC CSR register space */
392 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
393
394 /* set max packet size UDC CSR */
395 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
396 tmp = AMD_ADDBITS(tmp, maxpacket,
397 UDC_CSR_NE_MAX_PKT);
398 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
399
400 if (use_dma && !ep->in) {
401 /* alloc and init BNA dummy request */
402 ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
403 ep->bna_occurred = 0;
404 }
405
406 if (ep->num != UDC_EP0OUT_IX)
407 dev->data_ep_enabled = 1;
408 }
409
410 /* set ep values */
411 tmp = readl(&dev->csr->ne[udc_csr_epix]);
412 /* max packet */
413 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
414 /* ep number */
415 tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
416 /* ep direction */
417 tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
418 /* ep type */
419 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
420 /* ep config */
421 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
422 /* ep interface */
423 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
424 /* ep alt */
425 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
426 /* write reg */
427 writel(tmp, &dev->csr->ne[udc_csr_epix]);
428
429 /* enable ep irq */
430 tmp = readl(&dev->regs->ep_irqmsk);
431 tmp &= AMD_UNMASK_BIT(ep->num);
432 writel(tmp, &dev->regs->ep_irqmsk);
433
434 /*
435 * clear NAK by writing CNAK
436 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
437 */
438 if (!use_dma || ep->in) {
439 tmp = readl(&ep->regs->ctl);
440 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
441 writel(tmp, &ep->regs->ctl);
442 ep->naking = 0;
443 UDC_QUEUE_CNAK(ep, ep->num);
444 }
445 tmp = desc->bEndpointAddress;
446 DBG(dev, "%s enabled\n", usbep->name);
447
448 spin_unlock_irqrestore(&dev->lock, iflags);
449 return 0;
450 }
451
452 /* Resets endpoint */
ep_init(struct udc_regs __iomem * regs,struct udc_ep * ep)453 static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
454 {
455 u32 tmp;
456
457 VDBG(ep->dev, "ep-%d reset\n", ep->num);
458 ep->ep.desc = NULL;
459 ep->ep.ops = &udc_ep_ops;
460 INIT_LIST_HEAD(&ep->queue);
461
462 usb_ep_set_maxpacket_limit(&ep->ep,(u16) ~0);
463 /* set NAK */
464 tmp = readl(&ep->regs->ctl);
465 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
466 writel(tmp, &ep->regs->ctl);
467 ep->naking = 1;
468
469 /* disable interrupt */
470 tmp = readl(®s->ep_irqmsk);
471 tmp |= AMD_BIT(ep->num);
472 writel(tmp, ®s->ep_irqmsk);
473
474 if (ep->in) {
475 /* unset P and IN bit of potential former DMA */
476 tmp = readl(&ep->regs->ctl);
477 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
478 writel(tmp, &ep->regs->ctl);
479
480 tmp = readl(&ep->regs->sts);
481 tmp |= AMD_BIT(UDC_EPSTS_IN);
482 writel(tmp, &ep->regs->sts);
483
484 /* flush the fifo */
485 tmp = readl(&ep->regs->ctl);
486 tmp |= AMD_BIT(UDC_EPCTL_F);
487 writel(tmp, &ep->regs->ctl);
488
489 }
490 /* reset desc pointer */
491 writel(0, &ep->regs->desptr);
492 }
493
494 /* Disables endpoint, is called by gadget driver */
udc_ep_disable(struct usb_ep * usbep)495 static int udc_ep_disable(struct usb_ep *usbep)
496 {
497 struct udc_ep *ep = NULL;
498 unsigned long iflags;
499
500 if (!usbep)
501 return -EINVAL;
502
503 ep = container_of(usbep, struct udc_ep, ep);
504 if (usbep->name == ep0_string || !ep->ep.desc)
505 return -EINVAL;
506
507 DBG(ep->dev, "Disable ep-%d\n", ep->num);
508
509 spin_lock_irqsave(&ep->dev->lock, iflags);
510 udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
511 empty_req_queue(ep);
512 ep_init(ep->dev->regs, ep);
513 spin_unlock_irqrestore(&ep->dev->lock, iflags);
514
515 return 0;
516 }
517
518 /* Allocates request packet, called by gadget driver */
519 static struct usb_request *
udc_alloc_request(struct usb_ep * usbep,gfp_t gfp)520 udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
521 {
522 struct udc_request *req;
523 struct udc_data_dma *dma_desc;
524 struct udc_ep *ep;
525
526 if (!usbep)
527 return NULL;
528
529 ep = container_of(usbep, struct udc_ep, ep);
530
531 VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
532 req = kzalloc(sizeof(struct udc_request), gfp);
533 if (!req)
534 return NULL;
535
536 req->req.dma = DMA_DONT_USE;
537 INIT_LIST_HEAD(&req->queue);
538
539 if (ep->dma) {
540 /* ep0 in requests are allocated from data pool here */
541 dma_desc = dma_pool_alloc(ep->dev->data_requests, gfp,
542 &req->td_phys);
543 if (!dma_desc) {
544 kfree(req);
545 return NULL;
546 }
547
548 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
549 "td_phys = %lx\n",
550 req, dma_desc,
551 (unsigned long)req->td_phys);
552 /* prevent from using desc. - set HOST BUSY */
553 dma_desc->status = AMD_ADDBITS(dma_desc->status,
554 UDC_DMA_STP_STS_BS_HOST_BUSY,
555 UDC_DMA_STP_STS_BS);
556 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
557 req->td_data = dma_desc;
558 req->td_data_last = NULL;
559 req->chain_len = 1;
560 }
561
562 return &req->req;
563 }
564
565 /* frees pci pool descriptors of a DMA chain */
udc_free_dma_chain(struct udc * dev,struct udc_request * req)566 static void udc_free_dma_chain(struct udc *dev, struct udc_request *req)
567 {
568 struct udc_data_dma *td = req->td_data;
569 unsigned int i;
570
571 dma_addr_t addr_next = 0x00;
572 dma_addr_t addr = (dma_addr_t)td->next;
573
574 DBG(dev, "free chain req = %p\n", req);
575
576 /* do not free first desc., will be done by free for request */
577 for (i = 1; i < req->chain_len; i++) {
578 td = phys_to_virt(addr);
579 addr_next = (dma_addr_t)td->next;
580 dma_pool_free(dev->data_requests, td, addr);
581 addr = addr_next;
582 }
583 }
584
585 /* Frees request packet, called by gadget driver */
586 static void
udc_free_request(struct usb_ep * usbep,struct usb_request * usbreq)587 udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
588 {
589 struct udc_ep *ep;
590 struct udc_request *req;
591
592 if (!usbep || !usbreq)
593 return;
594
595 ep = container_of(usbep, struct udc_ep, ep);
596 req = container_of(usbreq, struct udc_request, req);
597 VDBG(ep->dev, "free_req req=%p\n", req);
598 BUG_ON(!list_empty(&req->queue));
599 if (req->td_data) {
600 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
601
602 /* free dma chain if created */
603 if (req->chain_len > 1)
604 udc_free_dma_chain(ep->dev, req);
605
606 dma_pool_free(ep->dev->data_requests, req->td_data,
607 req->td_phys);
608 }
609 kfree(req);
610 }
611
612 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
udc_init_bna_dummy(struct udc_request * req)613 static void udc_init_bna_dummy(struct udc_request *req)
614 {
615 if (req) {
616 /* set last bit */
617 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
618 /* set next pointer to itself */
619 req->td_data->next = req->td_phys;
620 /* set HOST BUSY */
621 req->td_data->status
622 = AMD_ADDBITS(req->td_data->status,
623 UDC_DMA_STP_STS_BS_DMA_DONE,
624 UDC_DMA_STP_STS_BS);
625 #ifdef UDC_VERBOSE
626 pr_debug("bna desc = %p, sts = %08x\n",
627 req->td_data, req->td_data->status);
628 #endif
629 }
630 }
631
632 /* Allocate BNA dummy descriptor */
udc_alloc_bna_dummy(struct udc_ep * ep)633 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
634 {
635 struct udc_request *req = NULL;
636 struct usb_request *_req = NULL;
637
638 /* alloc the dummy request */
639 _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
640 if (_req) {
641 req = container_of(_req, struct udc_request, req);
642 ep->bna_dummy_req = req;
643 udc_init_bna_dummy(req);
644 }
645 return req;
646 }
647
648 /* Write data to TX fifo for IN packets */
649 static void
udc_txfifo_write(struct udc_ep * ep,struct usb_request * req)650 udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
651 {
652 u8 *req_buf;
653 u32 *buf;
654 int i, j;
655 unsigned bytes = 0;
656 unsigned remaining = 0;
657
658 if (!req || !ep)
659 return;
660
661 req_buf = req->buf + req->actual;
662 prefetch(req_buf);
663 remaining = req->length - req->actual;
664
665 buf = (u32 *) req_buf;
666
667 bytes = ep->ep.maxpacket;
668 if (bytes > remaining)
669 bytes = remaining;
670
671 /* dwords first */
672 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
673 writel(*(buf + i), ep->txfifo);
674
675 /* remaining bytes must be written by byte access */
676 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
677 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
678 ep->txfifo);
679 }
680
681 /* dummy write confirm */
682 writel(0, &ep->regs->confirm);
683 }
684
685 /* Read dwords from RX fifo for OUT transfers */
udc_rxfifo_read_dwords(struct udc * dev,u32 * buf,int dwords)686 static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
687 {
688 int i;
689
690 VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
691
692 for (i = 0; i < dwords; i++)
693 *(buf + i) = readl(dev->rxfifo);
694 return 0;
695 }
696
697 /* Read bytes from RX fifo for OUT transfers */
udc_rxfifo_read_bytes(struct udc * dev,u8 * buf,int bytes)698 static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
699 {
700 int i, j;
701 u32 tmp;
702
703 VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
704
705 /* dwords first */
706 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
707 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
708
709 /* remaining bytes must be read by byte access */
710 if (bytes % UDC_DWORD_BYTES) {
711 tmp = readl(dev->rxfifo);
712 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
713 *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
714 tmp = tmp >> UDC_BITS_PER_BYTE;
715 }
716 }
717
718 return 0;
719 }
720
721 /* Read data from RX fifo for OUT transfers */
722 static int
udc_rxfifo_read(struct udc_ep * ep,struct udc_request * req)723 udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
724 {
725 u8 *buf;
726 unsigned buf_space;
727 unsigned bytes = 0;
728 unsigned finished = 0;
729
730 /* received number bytes */
731 bytes = readl(&ep->regs->sts);
732 bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
733
734 buf_space = req->req.length - req->req.actual;
735 buf = req->req.buf + req->req.actual;
736 if (bytes > buf_space) {
737 if ((buf_space % ep->ep.maxpacket) != 0) {
738 DBG(ep->dev,
739 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
740 ep->ep.name, bytes, buf_space);
741 req->req.status = -EOVERFLOW;
742 }
743 bytes = buf_space;
744 }
745 req->req.actual += bytes;
746
747 /* last packet ? */
748 if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
749 || ((req->req.actual == req->req.length) && !req->req.zero))
750 finished = 1;
751
752 /* read rx fifo bytes */
753 VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
754 udc_rxfifo_read_bytes(ep->dev, buf, bytes);
755
756 return finished;
757 }
758
759 /* Creates or re-inits a DMA chain */
udc_create_dma_chain(struct udc_ep * ep,struct udc_request * req,unsigned long buf_len,gfp_t gfp_flags)760 static int udc_create_dma_chain(
761 struct udc_ep *ep,
762 struct udc_request *req,
763 unsigned long buf_len, gfp_t gfp_flags
764 )
765 {
766 unsigned long bytes = req->req.length;
767 unsigned int i;
768 dma_addr_t dma_addr;
769 struct udc_data_dma *td = NULL;
770 struct udc_data_dma *last = NULL;
771 unsigned long txbytes;
772 unsigned create_new_chain = 0;
773 unsigned len;
774
775 VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
776 bytes, buf_len);
777 dma_addr = DMA_DONT_USE;
778
779 /* unset L bit in first desc for OUT */
780 if (!ep->in)
781 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
782
783 /* alloc only new desc's if not already available */
784 len = req->req.length / ep->ep.maxpacket;
785 if (req->req.length % ep->ep.maxpacket)
786 len++;
787
788 if (len > req->chain_len) {
789 /* shorter chain already allocated before */
790 if (req->chain_len > 1)
791 udc_free_dma_chain(ep->dev, req);
792 req->chain_len = len;
793 create_new_chain = 1;
794 }
795
796 td = req->td_data;
797 /* gen. required number of descriptors and buffers */
798 for (i = buf_len; i < bytes; i += buf_len) {
799 /* create or determine next desc. */
800 if (create_new_chain) {
801 td = dma_pool_alloc(ep->dev->data_requests,
802 gfp_flags, &dma_addr);
803 if (!td)
804 return -ENOMEM;
805
806 td->status = 0;
807 } else if (i == buf_len) {
808 /* first td */
809 td = (struct udc_data_dma *)phys_to_virt(
810 req->td_data->next);
811 td->status = 0;
812 } else {
813 td = (struct udc_data_dma *)phys_to_virt(last->next);
814 td->status = 0;
815 }
816
817 if (td)
818 td->bufptr = req->req.dma + i; /* assign buffer */
819 else
820 break;
821
822 /* short packet ? */
823 if ((bytes - i) >= buf_len) {
824 txbytes = buf_len;
825 } else {
826 /* short packet */
827 txbytes = bytes - i;
828 }
829
830 /* link td and assign tx bytes */
831 if (i == buf_len) {
832 if (create_new_chain)
833 req->td_data->next = dma_addr;
834 /*
835 * else
836 * req->td_data->next = virt_to_phys(td);
837 */
838 /* write tx bytes */
839 if (ep->in) {
840 /* first desc */
841 req->td_data->status =
842 AMD_ADDBITS(req->td_data->status,
843 ep->ep.maxpacket,
844 UDC_DMA_IN_STS_TXBYTES);
845 /* second desc */
846 td->status = AMD_ADDBITS(td->status,
847 txbytes,
848 UDC_DMA_IN_STS_TXBYTES);
849 }
850 } else {
851 if (create_new_chain)
852 last->next = dma_addr;
853 /*
854 * else
855 * last->next = virt_to_phys(td);
856 */
857 if (ep->in) {
858 /* write tx bytes */
859 td->status = AMD_ADDBITS(td->status,
860 txbytes,
861 UDC_DMA_IN_STS_TXBYTES);
862 }
863 }
864 last = td;
865 }
866 /* set last bit */
867 if (td) {
868 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
869 /* last desc. points to itself */
870 req->td_data_last = td;
871 }
872
873 return 0;
874 }
875
876 /* create/re-init a DMA descriptor or a DMA descriptor chain */
prep_dma(struct udc_ep * ep,struct udc_request * req,gfp_t gfp)877 static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
878 {
879 int retval = 0;
880 u32 tmp;
881
882 VDBG(ep->dev, "prep_dma\n");
883 VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
884 ep->num, req->td_data);
885
886 /* set buffer pointer */
887 req->td_data->bufptr = req->req.dma;
888
889 /* set last bit */
890 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
891
892 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
893 if (use_dma_ppb) {
894
895 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
896 if (retval != 0) {
897 if (retval == -ENOMEM)
898 DBG(ep->dev, "Out of DMA memory\n");
899 return retval;
900 }
901 if (ep->in) {
902 if (req->req.length == ep->ep.maxpacket) {
903 /* write tx bytes */
904 req->td_data->status =
905 AMD_ADDBITS(req->td_data->status,
906 ep->ep.maxpacket,
907 UDC_DMA_IN_STS_TXBYTES);
908
909 }
910 }
911
912 }
913
914 if (ep->in) {
915 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
916 "maxpacket=%d ep%d\n",
917 use_dma_ppb, req->req.length,
918 ep->ep.maxpacket, ep->num);
919 /*
920 * if bytes < max packet then tx bytes must
921 * be written in packet per buffer mode
922 */
923 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
924 || ep->num == UDC_EP0OUT_IX
925 || ep->num == UDC_EP0IN_IX) {
926 /* write tx bytes */
927 req->td_data->status =
928 AMD_ADDBITS(req->td_data->status,
929 req->req.length,
930 UDC_DMA_IN_STS_TXBYTES);
931 /* reset frame num */
932 req->td_data->status =
933 AMD_ADDBITS(req->td_data->status,
934 0,
935 UDC_DMA_IN_STS_FRAMENUM);
936 }
937 /* set HOST BUSY */
938 req->td_data->status =
939 AMD_ADDBITS(req->td_data->status,
940 UDC_DMA_STP_STS_BS_HOST_BUSY,
941 UDC_DMA_STP_STS_BS);
942 } else {
943 VDBG(ep->dev, "OUT set host ready\n");
944 /* set HOST READY */
945 req->td_data->status =
946 AMD_ADDBITS(req->td_data->status,
947 UDC_DMA_STP_STS_BS_HOST_READY,
948 UDC_DMA_STP_STS_BS);
949
950
951 /* clear NAK by writing CNAK */
952 if (ep->naking) {
953 tmp = readl(&ep->regs->ctl);
954 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
955 writel(tmp, &ep->regs->ctl);
956 ep->naking = 0;
957 UDC_QUEUE_CNAK(ep, ep->num);
958 }
959
960 }
961
962 return retval;
963 }
964
965 /* Completes request packet ... caller MUST hold lock */
966 static void
complete_req(struct udc_ep * ep,struct udc_request * req,int sts)967 complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
968 __releases(ep->dev->lock)
969 __acquires(ep->dev->lock)
970 {
971 struct udc *dev;
972 unsigned halted;
973
974 VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
975
976 dev = ep->dev;
977 /* unmap DMA */
978 if (ep->dma)
979 usb_gadget_unmap_request(&dev->gadget, &req->req, ep->in);
980
981 halted = ep->halted;
982 ep->halted = 1;
983
984 /* set new status if pending */
985 if (req->req.status == -EINPROGRESS)
986 req->req.status = sts;
987
988 /* remove from ep queue */
989 list_del_init(&req->queue);
990
991 VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
992 &req->req, req->req.length, ep->ep.name, sts);
993
994 spin_unlock(&dev->lock);
995 usb_gadget_giveback_request(&ep->ep, &req->req);
996 spin_lock(&dev->lock);
997 ep->halted = halted;
998 }
999
1000 /* Iterates to the end of a DMA chain and returns last descriptor */
udc_get_last_dma_desc(struct udc_request * req)1001 static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
1002 {
1003 struct udc_data_dma *td;
1004
1005 td = req->td_data;
1006 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L)))
1007 td = phys_to_virt(td->next);
1008
1009 return td;
1010
1011 }
1012
1013 /* Iterates to the end of a DMA chain and counts bytes received */
udc_get_ppbdu_rxbytes(struct udc_request * req)1014 static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
1015 {
1016 struct udc_data_dma *td;
1017 u32 count;
1018
1019 td = req->td_data;
1020 /* received number bytes */
1021 count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
1022
1023 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
1024 td = phys_to_virt(td->next);
1025 /* received number bytes */
1026 if (td) {
1027 count += AMD_GETBITS(td->status,
1028 UDC_DMA_OUT_STS_RXBYTES);
1029 }
1030 }
1031
1032 return count;
1033
1034 }
1035
1036 /* Enabling RX DMA */
udc_set_rde(struct udc * dev)1037 static void udc_set_rde(struct udc *dev)
1038 {
1039 u32 tmp;
1040
1041 VDBG(dev, "udc_set_rde()\n");
1042 /* stop RDE timer */
1043 if (timer_pending(&udc_timer)) {
1044 set_rde = 0;
1045 mod_timer(&udc_timer, jiffies - 1);
1046 }
1047 /* set RDE */
1048 tmp = readl(&dev->regs->ctl);
1049 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1050 writel(tmp, &dev->regs->ctl);
1051 }
1052
1053 /* Queues a request packet, called by gadget driver */
1054 static int
udc_queue(struct usb_ep * usbep,struct usb_request * usbreq,gfp_t gfp)1055 udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1056 {
1057 int retval = 0;
1058 u8 open_rxfifo = 0;
1059 unsigned long iflags;
1060 struct udc_ep *ep;
1061 struct udc_request *req;
1062 struct udc *dev;
1063 u32 tmp;
1064
1065 /* check the inputs */
1066 req = container_of(usbreq, struct udc_request, req);
1067
1068 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1069 || !list_empty(&req->queue))
1070 return -EINVAL;
1071
1072 ep = container_of(usbep, struct udc_ep, ep);
1073 if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1074 return -EINVAL;
1075
1076 VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1077 dev = ep->dev;
1078
1079 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1080 return -ESHUTDOWN;
1081
1082 /* map dma (usually done before) */
1083 if (ep->dma) {
1084 VDBG(dev, "DMA map req %p\n", req);
1085 retval = usb_gadget_map_request(&udc->gadget, usbreq, ep->in);
1086 if (retval)
1087 return retval;
1088 }
1089
1090 VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1091 usbep->name, usbreq, usbreq->length,
1092 req->td_data, usbreq->buf);
1093
1094 spin_lock_irqsave(&dev->lock, iflags);
1095 usbreq->actual = 0;
1096 usbreq->status = -EINPROGRESS;
1097 req->dma_done = 0;
1098
1099 /* on empty queue just do first transfer */
1100 if (list_empty(&ep->queue)) {
1101 /* zlp */
1102 if (usbreq->length == 0) {
1103 /* IN zlp's are handled by hardware */
1104 complete_req(ep, req, 0);
1105 VDBG(dev, "%s: zlp\n", ep->ep.name);
1106 /*
1107 * if set_config or set_intf is waiting for ack by zlp
1108 * then set CSR_DONE
1109 */
1110 if (dev->set_cfg_not_acked) {
1111 tmp = readl(&dev->regs->ctl);
1112 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1113 writel(tmp, &dev->regs->ctl);
1114 dev->set_cfg_not_acked = 0;
1115 }
1116 /* setup command is ACK'ed now by zlp */
1117 if (dev->waiting_zlp_ack_ep0in) {
1118 /* clear NAK by writing CNAK in EP0_IN */
1119 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1120 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1121 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1122 dev->ep[UDC_EP0IN_IX].naking = 0;
1123 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1124 UDC_EP0IN_IX);
1125 dev->waiting_zlp_ack_ep0in = 0;
1126 }
1127 goto finished;
1128 }
1129 if (ep->dma) {
1130 retval = prep_dma(ep, req, GFP_ATOMIC);
1131 if (retval != 0)
1132 goto finished;
1133 /* write desc pointer to enable DMA */
1134 if (ep->in) {
1135 /* set HOST READY */
1136 req->td_data->status =
1137 AMD_ADDBITS(req->td_data->status,
1138 UDC_DMA_IN_STS_BS_HOST_READY,
1139 UDC_DMA_IN_STS_BS);
1140 }
1141
1142 /* disabled rx dma while descriptor update */
1143 if (!ep->in) {
1144 /* stop RDE timer */
1145 if (timer_pending(&udc_timer)) {
1146 set_rde = 0;
1147 mod_timer(&udc_timer, jiffies - 1);
1148 }
1149 /* clear RDE */
1150 tmp = readl(&dev->regs->ctl);
1151 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1152 writel(tmp, &dev->regs->ctl);
1153 open_rxfifo = 1;
1154
1155 /*
1156 * if BNA occurred then let BNA dummy desc.
1157 * point to current desc.
1158 */
1159 if (ep->bna_occurred) {
1160 VDBG(dev, "copy to BNA dummy desc.\n");
1161 memcpy(ep->bna_dummy_req->td_data,
1162 req->td_data,
1163 sizeof(struct udc_data_dma));
1164 }
1165 }
1166 /* write desc pointer */
1167 writel(req->td_phys, &ep->regs->desptr);
1168
1169 /* clear NAK by writing CNAK */
1170 if (ep->naking) {
1171 tmp = readl(&ep->regs->ctl);
1172 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1173 writel(tmp, &ep->regs->ctl);
1174 ep->naking = 0;
1175 UDC_QUEUE_CNAK(ep, ep->num);
1176 }
1177
1178 if (ep->in) {
1179 /* enable ep irq */
1180 tmp = readl(&dev->regs->ep_irqmsk);
1181 tmp &= AMD_UNMASK_BIT(ep->num);
1182 writel(tmp, &dev->regs->ep_irqmsk);
1183 }
1184 } else if (ep->in) {
1185 /* enable ep irq */
1186 tmp = readl(&dev->regs->ep_irqmsk);
1187 tmp &= AMD_UNMASK_BIT(ep->num);
1188 writel(tmp, &dev->regs->ep_irqmsk);
1189 }
1190
1191 } else if (ep->dma) {
1192
1193 /*
1194 * prep_dma not used for OUT ep's, this is not possible
1195 * for PPB modes, because of chain creation reasons
1196 */
1197 if (ep->in) {
1198 retval = prep_dma(ep, req, GFP_ATOMIC);
1199 if (retval != 0)
1200 goto finished;
1201 }
1202 }
1203 VDBG(dev, "list_add\n");
1204 /* add request to ep queue */
1205 if (req) {
1206
1207 list_add_tail(&req->queue, &ep->queue);
1208
1209 /* open rxfifo if out data queued */
1210 if (open_rxfifo) {
1211 /* enable DMA */
1212 req->dma_going = 1;
1213 udc_set_rde(dev);
1214 if (ep->num != UDC_EP0OUT_IX)
1215 dev->data_ep_queued = 1;
1216 }
1217 /* stop OUT naking */
1218 if (!ep->in) {
1219 if (!use_dma && udc_rxfifo_pending) {
1220 DBG(dev, "udc_queue(): pending bytes in "
1221 "rxfifo after nyet\n");
1222 /*
1223 * read pending bytes afer nyet:
1224 * referring to isr
1225 */
1226 if (udc_rxfifo_read(ep, req)) {
1227 /* finish */
1228 complete_req(ep, req, 0);
1229 }
1230 udc_rxfifo_pending = 0;
1231
1232 }
1233 }
1234 }
1235
1236 finished:
1237 spin_unlock_irqrestore(&dev->lock, iflags);
1238 return retval;
1239 }
1240
1241 /* Empty request queue of an endpoint; caller holds spinlock */
empty_req_queue(struct udc_ep * ep)1242 void empty_req_queue(struct udc_ep *ep)
1243 {
1244 struct udc_request *req;
1245
1246 ep->halted = 1;
1247 while (!list_empty(&ep->queue)) {
1248 req = list_entry(ep->queue.next,
1249 struct udc_request,
1250 queue);
1251 complete_req(ep, req, -ESHUTDOWN);
1252 }
1253 }
1254 EXPORT_SYMBOL_GPL(empty_req_queue);
1255
1256 /* Dequeues a request packet, called by gadget driver */
udc_dequeue(struct usb_ep * usbep,struct usb_request * usbreq)1257 static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1258 {
1259 struct udc_ep *ep;
1260 struct udc_request *req;
1261 unsigned halted;
1262 unsigned long iflags;
1263
1264 ep = container_of(usbep, struct udc_ep, ep);
1265 if (!usbep || !usbreq || (!ep->ep.desc && (ep->num != 0
1266 && ep->num != UDC_EP0OUT_IX)))
1267 return -EINVAL;
1268
1269 req = container_of(usbreq, struct udc_request, req);
1270
1271 spin_lock_irqsave(&ep->dev->lock, iflags);
1272 halted = ep->halted;
1273 ep->halted = 1;
1274 /* request in processing or next one */
1275 if (ep->queue.next == &req->queue) {
1276 if (ep->dma && req->dma_going) {
1277 if (ep->in)
1278 ep->cancel_transfer = 1;
1279 else {
1280 u32 tmp;
1281 u32 dma_sts;
1282 /* stop potential receive DMA */
1283 tmp = readl(&udc->regs->ctl);
1284 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1285 &udc->regs->ctl);
1286 /*
1287 * Cancel transfer later in ISR
1288 * if descriptor was touched.
1289 */
1290 dma_sts = AMD_GETBITS(req->td_data->status,
1291 UDC_DMA_OUT_STS_BS);
1292 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1293 ep->cancel_transfer = 1;
1294 else {
1295 udc_init_bna_dummy(ep->req);
1296 writel(ep->bna_dummy_req->td_phys,
1297 &ep->regs->desptr);
1298 }
1299 writel(tmp, &udc->regs->ctl);
1300 }
1301 }
1302 }
1303 complete_req(ep, req, -ECONNRESET);
1304 ep->halted = halted;
1305
1306 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1307 return 0;
1308 }
1309
1310 /* Halt or clear halt of endpoint */
1311 static int
udc_set_halt(struct usb_ep * usbep,int halt)1312 udc_set_halt(struct usb_ep *usbep, int halt)
1313 {
1314 struct udc_ep *ep;
1315 u32 tmp;
1316 unsigned long iflags;
1317 int retval = 0;
1318
1319 if (!usbep)
1320 return -EINVAL;
1321
1322 pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1323
1324 ep = container_of(usbep, struct udc_ep, ep);
1325 if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1326 return -EINVAL;
1327 if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1328 return -ESHUTDOWN;
1329
1330 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1331 /* halt or clear halt */
1332 if (halt) {
1333 if (ep->num == 0)
1334 ep->dev->stall_ep0in = 1;
1335 else {
1336 /*
1337 * set STALL
1338 * rxfifo empty not taken into acount
1339 */
1340 tmp = readl(&ep->regs->ctl);
1341 tmp |= AMD_BIT(UDC_EPCTL_S);
1342 writel(tmp, &ep->regs->ctl);
1343 ep->halted = 1;
1344
1345 /* setup poll timer */
1346 if (!timer_pending(&udc_pollstall_timer)) {
1347 udc_pollstall_timer.expires = jiffies +
1348 HZ * UDC_POLLSTALL_TIMER_USECONDS
1349 / (1000 * 1000);
1350 if (!stop_pollstall_timer) {
1351 DBG(ep->dev, "start polltimer\n");
1352 add_timer(&udc_pollstall_timer);
1353 }
1354 }
1355 }
1356 } else {
1357 /* ep is halted by set_halt() before */
1358 if (ep->halted) {
1359 tmp = readl(&ep->regs->ctl);
1360 /* clear stall bit */
1361 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1362 /* clear NAK by writing CNAK */
1363 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1364 writel(tmp, &ep->regs->ctl);
1365 ep->halted = 0;
1366 UDC_QUEUE_CNAK(ep, ep->num);
1367 }
1368 }
1369 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1370 return retval;
1371 }
1372
1373 /* gadget interface */
1374 static const struct usb_ep_ops udc_ep_ops = {
1375 .enable = udc_ep_enable,
1376 .disable = udc_ep_disable,
1377
1378 .alloc_request = udc_alloc_request,
1379 .free_request = udc_free_request,
1380
1381 .queue = udc_queue,
1382 .dequeue = udc_dequeue,
1383
1384 .set_halt = udc_set_halt,
1385 /* fifo ops not implemented */
1386 };
1387
1388 /*-------------------------------------------------------------------------*/
1389
1390 /* Get frame counter (not implemented) */
udc_get_frame(struct usb_gadget * gadget)1391 static int udc_get_frame(struct usb_gadget *gadget)
1392 {
1393 return -EOPNOTSUPP;
1394 }
1395
1396 /* Initiates a remote wakeup */
udc_remote_wakeup(struct udc * dev)1397 static int udc_remote_wakeup(struct udc *dev)
1398 {
1399 unsigned long flags;
1400 u32 tmp;
1401
1402 DBG(dev, "UDC initiates remote wakeup\n");
1403
1404 spin_lock_irqsave(&dev->lock, flags);
1405
1406 tmp = readl(&dev->regs->ctl);
1407 tmp |= AMD_BIT(UDC_DEVCTL_RES);
1408 writel(tmp, &dev->regs->ctl);
1409 tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
1410 writel(tmp, &dev->regs->ctl);
1411
1412 spin_unlock_irqrestore(&dev->lock, flags);
1413 return 0;
1414 }
1415
1416 /* Remote wakeup gadget interface */
udc_wakeup(struct usb_gadget * gadget)1417 static int udc_wakeup(struct usb_gadget *gadget)
1418 {
1419 struct udc *dev;
1420
1421 if (!gadget)
1422 return -EINVAL;
1423 dev = container_of(gadget, struct udc, gadget);
1424 udc_remote_wakeup(dev);
1425
1426 return 0;
1427 }
1428
1429 static int amd5536_udc_start(struct usb_gadget *g,
1430 struct usb_gadget_driver *driver);
1431 static int amd5536_udc_stop(struct usb_gadget *g);
1432
1433 static const struct usb_gadget_ops udc_ops = {
1434 .wakeup = udc_wakeup,
1435 .get_frame = udc_get_frame,
1436 .udc_start = amd5536_udc_start,
1437 .udc_stop = amd5536_udc_stop,
1438 };
1439
1440 /* Setups endpoint parameters, adds endpoints to linked list */
make_ep_lists(struct udc * dev)1441 static void make_ep_lists(struct udc *dev)
1442 {
1443 /* make gadget ep lists */
1444 INIT_LIST_HEAD(&dev->gadget.ep_list);
1445 list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1446 &dev->gadget.ep_list);
1447 list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1448 &dev->gadget.ep_list);
1449 list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1450 &dev->gadget.ep_list);
1451
1452 /* fifo config */
1453 dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1454 if (dev->gadget.speed == USB_SPEED_FULL)
1455 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1456 else if (dev->gadget.speed == USB_SPEED_HIGH)
1457 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1458 dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1459 }
1460
1461 /* Inits UDC context */
udc_basic_init(struct udc * dev)1462 void udc_basic_init(struct udc *dev)
1463 {
1464 u32 tmp;
1465
1466 DBG(dev, "udc_basic_init()\n");
1467
1468 dev->gadget.speed = USB_SPEED_UNKNOWN;
1469
1470 /* stop RDE timer */
1471 if (timer_pending(&udc_timer)) {
1472 set_rde = 0;
1473 mod_timer(&udc_timer, jiffies - 1);
1474 }
1475 /* stop poll stall timer */
1476 if (timer_pending(&udc_pollstall_timer))
1477 mod_timer(&udc_pollstall_timer, jiffies - 1);
1478 /* disable DMA */
1479 tmp = readl(&dev->regs->ctl);
1480 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1481 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1482 writel(tmp, &dev->regs->ctl);
1483
1484 /* enable dynamic CSR programming */
1485 tmp = readl(&dev->regs->cfg);
1486 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1487 /* set self powered */
1488 tmp |= AMD_BIT(UDC_DEVCFG_SP);
1489 /* set remote wakeupable */
1490 tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1491 writel(tmp, &dev->regs->cfg);
1492
1493 make_ep_lists(dev);
1494
1495 dev->data_ep_enabled = 0;
1496 dev->data_ep_queued = 0;
1497 }
1498 EXPORT_SYMBOL_GPL(udc_basic_init);
1499
1500 /* init registers at driver load time */
startup_registers(struct udc * dev)1501 static int startup_registers(struct udc *dev)
1502 {
1503 u32 tmp;
1504
1505 /* init controller by soft reset */
1506 udc_soft_reset(dev);
1507
1508 /* mask not needed interrupts */
1509 udc_mask_unused_interrupts(dev);
1510
1511 /* put into initial config */
1512 udc_basic_init(dev);
1513 /* link up all endpoints */
1514 udc_setup_endpoints(dev);
1515
1516 /* program speed */
1517 tmp = readl(&dev->regs->cfg);
1518 if (use_fullspeed)
1519 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1520 else
1521 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
1522 writel(tmp, &dev->regs->cfg);
1523
1524 return 0;
1525 }
1526
1527 /* Sets initial endpoint parameters */
udc_setup_endpoints(struct udc * dev)1528 static void udc_setup_endpoints(struct udc *dev)
1529 {
1530 struct udc_ep *ep;
1531 u32 tmp;
1532 u32 reg;
1533
1534 DBG(dev, "udc_setup_endpoints()\n");
1535
1536 /* read enum speed */
1537 tmp = readl(&dev->regs->sts);
1538 tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
1539 if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH)
1540 dev->gadget.speed = USB_SPEED_HIGH;
1541 else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL)
1542 dev->gadget.speed = USB_SPEED_FULL;
1543
1544 /* set basic ep parameters */
1545 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1546 ep = &dev->ep[tmp];
1547 ep->dev = dev;
1548 ep->ep.name = ep_info[tmp].name;
1549 ep->ep.caps = ep_info[tmp].caps;
1550 ep->num = tmp;
1551 /* txfifo size is calculated at enable time */
1552 ep->txfifo = dev->txfifo;
1553
1554 /* fifo size */
1555 if (tmp < UDC_EPIN_NUM) {
1556 ep->fifo_depth = UDC_TXFIFO_SIZE;
1557 ep->in = 1;
1558 } else {
1559 ep->fifo_depth = UDC_RXFIFO_SIZE;
1560 ep->in = 0;
1561
1562 }
1563 ep->regs = &dev->ep_regs[tmp];
1564 /*
1565 * ep will be reset only if ep was not enabled before to avoid
1566 * disabling ep interrupts when ENUM interrupt occurs but ep is
1567 * not enabled by gadget driver
1568 */
1569 if (!ep->ep.desc)
1570 ep_init(dev->regs, ep);
1571
1572 if (use_dma) {
1573 /*
1574 * ep->dma is not really used, just to indicate that
1575 * DMA is active: remove this
1576 * dma regs = dev control regs
1577 */
1578 ep->dma = &dev->regs->ctl;
1579
1580 /* nak OUT endpoints until enable - not for ep0 */
1581 if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1582 && tmp > UDC_EPIN_NUM) {
1583 /* set NAK */
1584 reg = readl(&dev->ep[tmp].regs->ctl);
1585 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1586 writel(reg, &dev->ep[tmp].regs->ctl);
1587 dev->ep[tmp].naking = 1;
1588
1589 }
1590 }
1591 }
1592 /* EP0 max packet */
1593 if (dev->gadget.speed == USB_SPEED_FULL) {
1594 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1595 UDC_FS_EP0IN_MAX_PKT_SIZE);
1596 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1597 UDC_FS_EP0OUT_MAX_PKT_SIZE);
1598 } else if (dev->gadget.speed == USB_SPEED_HIGH) {
1599 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1600 UDC_EP0IN_MAX_PKT_SIZE);
1601 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1602 UDC_EP0OUT_MAX_PKT_SIZE);
1603 }
1604
1605 /*
1606 * with suspend bug workaround, ep0 params for gadget driver
1607 * are set at gadget driver bind() call
1608 */
1609 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1610 dev->ep[UDC_EP0IN_IX].halted = 0;
1611 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1612
1613 /* init cfg/alt/int */
1614 dev->cur_config = 0;
1615 dev->cur_intf = 0;
1616 dev->cur_alt = 0;
1617 }
1618
1619 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
usb_connect(struct udc * dev)1620 static void usb_connect(struct udc *dev)
1621 {
1622 /* Return if already connected */
1623 if (dev->connected)
1624 return;
1625
1626 dev_info(dev->dev, "USB Connect\n");
1627
1628 dev->connected = 1;
1629
1630 /* put into initial config */
1631 udc_basic_init(dev);
1632
1633 /* enable device setup interrupts */
1634 udc_enable_dev_setup_interrupts(dev);
1635 }
1636
1637 /*
1638 * Calls gadget with disconnect event and resets the UDC and makes
1639 * initial bringup to be ready for ep0 events
1640 */
usb_disconnect(struct udc * dev)1641 static void usb_disconnect(struct udc *dev)
1642 {
1643 /* Return if already disconnected */
1644 if (!dev->connected)
1645 return;
1646
1647 dev_info(dev->dev, "USB Disconnect\n");
1648
1649 dev->connected = 0;
1650
1651 /* mask interrupts */
1652 udc_mask_unused_interrupts(dev);
1653
1654 /* REVISIT there doesn't seem to be a point to having this
1655 * talk to a tasklet ... do it directly, we already hold
1656 * the spinlock needed to process the disconnect.
1657 */
1658
1659 tasklet_schedule(&disconnect_tasklet);
1660 }
1661
1662 /* Tasklet for disconnect to be outside of interrupt context */
udc_tasklet_disconnect(unsigned long par)1663 static void udc_tasklet_disconnect(unsigned long par)
1664 {
1665 struct udc *dev = (struct udc *)(*((struct udc **) par));
1666 u32 tmp;
1667
1668 DBG(dev, "Tasklet disconnect\n");
1669 spin_lock_irq(&dev->lock);
1670
1671 if (dev->driver) {
1672 spin_unlock(&dev->lock);
1673 dev->driver->disconnect(&dev->gadget);
1674 spin_lock(&dev->lock);
1675
1676 /* empty queues */
1677 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1678 empty_req_queue(&dev->ep[tmp]);
1679
1680 }
1681
1682 /* disable ep0 */
1683 ep_init(dev->regs,
1684 &dev->ep[UDC_EP0IN_IX]);
1685
1686
1687 if (!soft_reset_occured) {
1688 /* init controller by soft reset */
1689 udc_soft_reset(dev);
1690 soft_reset_occured++;
1691 }
1692
1693 /* re-enable dev interrupts */
1694 udc_enable_dev_setup_interrupts(dev);
1695 /* back to full speed ? */
1696 if (use_fullspeed) {
1697 tmp = readl(&dev->regs->cfg);
1698 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1699 writel(tmp, &dev->regs->cfg);
1700 }
1701
1702 spin_unlock_irq(&dev->lock);
1703 }
1704
1705 /* Reset the UDC core */
udc_soft_reset(struct udc * dev)1706 static void udc_soft_reset(struct udc *dev)
1707 {
1708 unsigned long flags;
1709
1710 DBG(dev, "Soft reset\n");
1711 /*
1712 * reset possible waiting interrupts, because int.
1713 * status is lost after soft reset,
1714 * ep int. status reset
1715 */
1716 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1717 /* device int. status reset */
1718 writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1719
1720 /* Don't do this for Broadcom UDC since this is a reserved
1721 * bit.
1722 */
1723 if (dev->chiprev != UDC_BCM_REV) {
1724 spin_lock_irqsave(&udc_irq_spinlock, flags);
1725 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1726 readl(&dev->regs->cfg);
1727 spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1728 }
1729 }
1730
1731 /* RDE timer callback to set RDE bit */
udc_timer_function(struct timer_list * unused)1732 static void udc_timer_function(struct timer_list *unused)
1733 {
1734 u32 tmp;
1735
1736 spin_lock_irq(&udc_irq_spinlock);
1737
1738 if (set_rde > 0) {
1739 /*
1740 * open the fifo if fifo was filled on last timer call
1741 * conditionally
1742 */
1743 if (set_rde > 1) {
1744 /* set RDE to receive setup data */
1745 tmp = readl(&udc->regs->ctl);
1746 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1747 writel(tmp, &udc->regs->ctl);
1748 set_rde = -1;
1749 } else if (readl(&udc->regs->sts)
1750 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1751 /*
1752 * if fifo empty setup polling, do not just
1753 * open the fifo
1754 */
1755 udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
1756 if (!stop_timer)
1757 add_timer(&udc_timer);
1758 } else {
1759 /*
1760 * fifo contains data now, setup timer for opening
1761 * the fifo when timer expires to be able to receive
1762 * setup packets, when data packets gets queued by
1763 * gadget layer then timer will forced to expire with
1764 * set_rde=0 (RDE is set in udc_queue())
1765 */
1766 set_rde++;
1767 /* debug: lhadmot_timer_start = 221070 */
1768 udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
1769 if (!stop_timer)
1770 add_timer(&udc_timer);
1771 }
1772
1773 } else
1774 set_rde = -1; /* RDE was set by udc_queue() */
1775 spin_unlock_irq(&udc_irq_spinlock);
1776 if (stop_timer)
1777 complete(&on_exit);
1778
1779 }
1780
1781 /* Handle halt state, used in stall poll timer */
udc_handle_halt_state(struct udc_ep * ep)1782 static void udc_handle_halt_state(struct udc_ep *ep)
1783 {
1784 u32 tmp;
1785 /* set stall as long not halted */
1786 if (ep->halted == 1) {
1787 tmp = readl(&ep->regs->ctl);
1788 /* STALL cleared ? */
1789 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1790 /*
1791 * FIXME: MSC spec requires that stall remains
1792 * even on receivng of CLEAR_FEATURE HALT. So
1793 * we would set STALL again here to be compliant.
1794 * But with current mass storage drivers this does
1795 * not work (would produce endless host retries).
1796 * So we clear halt on CLEAR_FEATURE.
1797 *
1798 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1799 tmp |= AMD_BIT(UDC_EPCTL_S);
1800 writel(tmp, &ep->regs->ctl);*/
1801
1802 /* clear NAK by writing CNAK */
1803 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1804 writel(tmp, &ep->regs->ctl);
1805 ep->halted = 0;
1806 UDC_QUEUE_CNAK(ep, ep->num);
1807 }
1808 }
1809 }
1810
1811 /* Stall timer callback to poll S bit and set it again after */
udc_pollstall_timer_function(struct timer_list * unused)1812 static void udc_pollstall_timer_function(struct timer_list *unused)
1813 {
1814 struct udc_ep *ep;
1815 int halted = 0;
1816
1817 spin_lock_irq(&udc_stall_spinlock);
1818 /*
1819 * only one IN and OUT endpoints are handled
1820 * IN poll stall
1821 */
1822 ep = &udc->ep[UDC_EPIN_IX];
1823 udc_handle_halt_state(ep);
1824 if (ep->halted)
1825 halted = 1;
1826 /* OUT poll stall */
1827 ep = &udc->ep[UDC_EPOUT_IX];
1828 udc_handle_halt_state(ep);
1829 if (ep->halted)
1830 halted = 1;
1831
1832 /* setup timer again when still halted */
1833 if (!stop_pollstall_timer && halted) {
1834 udc_pollstall_timer.expires = jiffies +
1835 HZ * UDC_POLLSTALL_TIMER_USECONDS
1836 / (1000 * 1000);
1837 add_timer(&udc_pollstall_timer);
1838 }
1839 spin_unlock_irq(&udc_stall_spinlock);
1840
1841 if (stop_pollstall_timer)
1842 complete(&on_pollstall_exit);
1843 }
1844
1845 /* Inits endpoint 0 so that SETUP packets are processed */
activate_control_endpoints(struct udc * dev)1846 static void activate_control_endpoints(struct udc *dev)
1847 {
1848 u32 tmp;
1849
1850 DBG(dev, "activate_control_endpoints\n");
1851
1852 /* flush fifo */
1853 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1854 tmp |= AMD_BIT(UDC_EPCTL_F);
1855 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1856
1857 /* set ep0 directions */
1858 dev->ep[UDC_EP0IN_IX].in = 1;
1859 dev->ep[UDC_EP0OUT_IX].in = 0;
1860
1861 /* set buffer size (tx fifo entries) of EP0_IN */
1862 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1863 if (dev->gadget.speed == USB_SPEED_FULL)
1864 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1865 UDC_EPIN_BUFF_SIZE);
1866 else if (dev->gadget.speed == USB_SPEED_HIGH)
1867 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1868 UDC_EPIN_BUFF_SIZE);
1869 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1870
1871 /* set max packet size of EP0_IN */
1872 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1873 if (dev->gadget.speed == USB_SPEED_FULL)
1874 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1875 UDC_EP_MAX_PKT_SIZE);
1876 else if (dev->gadget.speed == USB_SPEED_HIGH)
1877 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1878 UDC_EP_MAX_PKT_SIZE);
1879 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1880
1881 /* set max packet size of EP0_OUT */
1882 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1883 if (dev->gadget.speed == USB_SPEED_FULL)
1884 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1885 UDC_EP_MAX_PKT_SIZE);
1886 else if (dev->gadget.speed == USB_SPEED_HIGH)
1887 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1888 UDC_EP_MAX_PKT_SIZE);
1889 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1890
1891 /* set max packet size of EP0 in UDC CSR */
1892 tmp = readl(&dev->csr->ne[0]);
1893 if (dev->gadget.speed == USB_SPEED_FULL)
1894 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1895 UDC_CSR_NE_MAX_PKT);
1896 else if (dev->gadget.speed == USB_SPEED_HIGH)
1897 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1898 UDC_CSR_NE_MAX_PKT);
1899 writel(tmp, &dev->csr->ne[0]);
1900
1901 if (use_dma) {
1902 dev->ep[UDC_EP0OUT_IX].td->status |=
1903 AMD_BIT(UDC_DMA_OUT_STS_L);
1904 /* write dma desc address */
1905 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1906 &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1907 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1908 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1909 /* stop RDE timer */
1910 if (timer_pending(&udc_timer)) {
1911 set_rde = 0;
1912 mod_timer(&udc_timer, jiffies - 1);
1913 }
1914 /* stop pollstall timer */
1915 if (timer_pending(&udc_pollstall_timer))
1916 mod_timer(&udc_pollstall_timer, jiffies - 1);
1917 /* enable DMA */
1918 tmp = readl(&dev->regs->ctl);
1919 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1920 | AMD_BIT(UDC_DEVCTL_RDE)
1921 | AMD_BIT(UDC_DEVCTL_TDE);
1922 if (use_dma_bufferfill_mode)
1923 tmp |= AMD_BIT(UDC_DEVCTL_BF);
1924 else if (use_dma_ppb_du)
1925 tmp |= AMD_BIT(UDC_DEVCTL_DU);
1926 writel(tmp, &dev->regs->ctl);
1927 }
1928
1929 /* clear NAK by writing CNAK for EP0IN */
1930 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1931 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1932 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1933 dev->ep[UDC_EP0IN_IX].naking = 0;
1934 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1935
1936 /* clear NAK by writing CNAK for EP0OUT */
1937 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1938 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1939 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1940 dev->ep[UDC_EP0OUT_IX].naking = 0;
1941 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1942 }
1943
1944 /* Make endpoint 0 ready for control traffic */
setup_ep0(struct udc * dev)1945 static int setup_ep0(struct udc *dev)
1946 {
1947 activate_control_endpoints(dev);
1948 /* enable ep0 interrupts */
1949 udc_enable_ep0_interrupts(dev);
1950 /* enable device setup interrupts */
1951 udc_enable_dev_setup_interrupts(dev);
1952
1953 return 0;
1954 }
1955
1956 /* Called by gadget driver to register itself */
amd5536_udc_start(struct usb_gadget * g,struct usb_gadget_driver * driver)1957 static int amd5536_udc_start(struct usb_gadget *g,
1958 struct usb_gadget_driver *driver)
1959 {
1960 struct udc *dev = to_amd5536_udc(g);
1961 u32 tmp;
1962
1963 driver->driver.bus = NULL;
1964 dev->driver = driver;
1965
1966 /* Some gadget drivers use both ep0 directions.
1967 * NOTE: to gadget driver, ep0 is just one endpoint...
1968 */
1969 dev->ep[UDC_EP0OUT_IX].ep.driver_data =
1970 dev->ep[UDC_EP0IN_IX].ep.driver_data;
1971
1972 /* get ready for ep0 traffic */
1973 setup_ep0(dev);
1974
1975 /* clear SD */
1976 tmp = readl(&dev->regs->ctl);
1977 tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
1978 writel(tmp, &dev->regs->ctl);
1979
1980 usb_connect(dev);
1981
1982 return 0;
1983 }
1984
1985 /* shutdown requests and disconnect from gadget */
1986 static void
shutdown(struct udc * dev,struct usb_gadget_driver * driver)1987 shutdown(struct udc *dev, struct usb_gadget_driver *driver)
1988 __releases(dev->lock)
1989 __acquires(dev->lock)
1990 {
1991 int tmp;
1992
1993 /* empty queues and init hardware */
1994 udc_basic_init(dev);
1995
1996 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1997 empty_req_queue(&dev->ep[tmp]);
1998
1999 udc_setup_endpoints(dev);
2000 }
2001
2002 /* Called by gadget driver to unregister itself */
amd5536_udc_stop(struct usb_gadget * g)2003 static int amd5536_udc_stop(struct usb_gadget *g)
2004 {
2005 struct udc *dev = to_amd5536_udc(g);
2006 unsigned long flags;
2007 u32 tmp;
2008
2009 spin_lock_irqsave(&dev->lock, flags);
2010 udc_mask_unused_interrupts(dev);
2011 shutdown(dev, NULL);
2012 spin_unlock_irqrestore(&dev->lock, flags);
2013
2014 dev->driver = NULL;
2015
2016 /* set SD */
2017 tmp = readl(&dev->regs->ctl);
2018 tmp |= AMD_BIT(UDC_DEVCTL_SD);
2019 writel(tmp, &dev->regs->ctl);
2020
2021 return 0;
2022 }
2023
2024 /* Clear pending NAK bits */
udc_process_cnak_queue(struct udc * dev)2025 static void udc_process_cnak_queue(struct udc *dev)
2026 {
2027 u32 tmp;
2028 u32 reg;
2029
2030 /* check epin's */
2031 DBG(dev, "CNAK pending queue processing\n");
2032 for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
2033 if (cnak_pending & (1 << tmp)) {
2034 DBG(dev, "CNAK pending for ep%d\n", tmp);
2035 /* clear NAK by writing CNAK */
2036 reg = readl(&dev->ep[tmp].regs->ctl);
2037 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2038 writel(reg, &dev->ep[tmp].regs->ctl);
2039 dev->ep[tmp].naking = 0;
2040 UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2041 }
2042 }
2043 /* ... and ep0out */
2044 if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2045 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2046 /* clear NAK by writing CNAK */
2047 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2048 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2049 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2050 dev->ep[UDC_EP0OUT_IX].naking = 0;
2051 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2052 dev->ep[UDC_EP0OUT_IX].num);
2053 }
2054 }
2055
2056 /* Enabling RX DMA after setup packet */
udc_ep0_set_rde(struct udc * dev)2057 static void udc_ep0_set_rde(struct udc *dev)
2058 {
2059 if (use_dma) {
2060 /*
2061 * only enable RXDMA when no data endpoint enabled
2062 * or data is queued
2063 */
2064 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2065 udc_set_rde(dev);
2066 } else {
2067 /*
2068 * setup timer for enabling RDE (to not enable
2069 * RXFIFO DMA for data endpoints to early)
2070 */
2071 if (set_rde != 0 && !timer_pending(&udc_timer)) {
2072 udc_timer.expires =
2073 jiffies + HZ/UDC_RDE_TIMER_DIV;
2074 set_rde = 1;
2075 if (!stop_timer)
2076 add_timer(&udc_timer);
2077 }
2078 }
2079 }
2080 }
2081
2082
2083 /* Interrupt handler for data OUT traffic */
udc_data_out_isr(struct udc * dev,int ep_ix)2084 static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2085 {
2086 irqreturn_t ret_val = IRQ_NONE;
2087 u32 tmp;
2088 struct udc_ep *ep;
2089 struct udc_request *req;
2090 unsigned int count;
2091 struct udc_data_dma *td = NULL;
2092 unsigned dma_done;
2093
2094 VDBG(dev, "ep%d irq\n", ep_ix);
2095 ep = &dev->ep[ep_ix];
2096
2097 tmp = readl(&ep->regs->sts);
2098 if (use_dma) {
2099 /* BNA event ? */
2100 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2101 DBG(dev, "BNA ep%dout occurred - DESPTR = %x\n",
2102 ep->num, readl(&ep->regs->desptr));
2103 /* clear BNA */
2104 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2105 if (!ep->cancel_transfer)
2106 ep->bna_occurred = 1;
2107 else
2108 ep->cancel_transfer = 0;
2109 ret_val = IRQ_HANDLED;
2110 goto finished;
2111 }
2112 }
2113 /* HE event ? */
2114 if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
2115 dev_err(dev->dev, "HE ep%dout occurred\n", ep->num);
2116
2117 /* clear HE */
2118 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2119 ret_val = IRQ_HANDLED;
2120 goto finished;
2121 }
2122
2123 if (!list_empty(&ep->queue)) {
2124
2125 /* next request */
2126 req = list_entry(ep->queue.next,
2127 struct udc_request, queue);
2128 } else {
2129 req = NULL;
2130 udc_rxfifo_pending = 1;
2131 }
2132 VDBG(dev, "req = %p\n", req);
2133 /* fifo mode */
2134 if (!use_dma) {
2135
2136 /* read fifo */
2137 if (req && udc_rxfifo_read(ep, req)) {
2138 ret_val = IRQ_HANDLED;
2139
2140 /* finish */
2141 complete_req(ep, req, 0);
2142 /* next request */
2143 if (!list_empty(&ep->queue) && !ep->halted) {
2144 req = list_entry(ep->queue.next,
2145 struct udc_request, queue);
2146 } else
2147 req = NULL;
2148 }
2149
2150 /* DMA */
2151 } else if (!ep->cancel_transfer && req) {
2152 ret_val = IRQ_HANDLED;
2153
2154 /* check for DMA done */
2155 if (!use_dma_ppb) {
2156 dma_done = AMD_GETBITS(req->td_data->status,
2157 UDC_DMA_OUT_STS_BS);
2158 /* packet per buffer mode - rx bytes */
2159 } else {
2160 /*
2161 * if BNA occurred then recover desc. from
2162 * BNA dummy desc.
2163 */
2164 if (ep->bna_occurred) {
2165 VDBG(dev, "Recover desc. from BNA dummy\n");
2166 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2167 sizeof(struct udc_data_dma));
2168 ep->bna_occurred = 0;
2169 udc_init_bna_dummy(ep->req);
2170 }
2171 td = udc_get_last_dma_desc(req);
2172 dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2173 }
2174 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2175 /* buffer fill mode - rx bytes */
2176 if (!use_dma_ppb) {
2177 /* received number bytes */
2178 count = AMD_GETBITS(req->td_data->status,
2179 UDC_DMA_OUT_STS_RXBYTES);
2180 VDBG(dev, "rx bytes=%u\n", count);
2181 /* packet per buffer mode - rx bytes */
2182 } else {
2183 VDBG(dev, "req->td_data=%p\n", req->td_data);
2184 VDBG(dev, "last desc = %p\n", td);
2185 /* received number bytes */
2186 if (use_dma_ppb_du) {
2187 /* every desc. counts bytes */
2188 count = udc_get_ppbdu_rxbytes(req);
2189 } else {
2190 /* last desc. counts bytes */
2191 count = AMD_GETBITS(td->status,
2192 UDC_DMA_OUT_STS_RXBYTES);
2193 if (!count && req->req.length
2194 == UDC_DMA_MAXPACKET) {
2195 /*
2196 * on 64k packets the RXBYTES
2197 * field is zero
2198 */
2199 count = UDC_DMA_MAXPACKET;
2200 }
2201 }
2202 VDBG(dev, "last desc rx bytes=%u\n", count);
2203 }
2204
2205 tmp = req->req.length - req->req.actual;
2206 if (count > tmp) {
2207 if ((tmp % ep->ep.maxpacket) != 0) {
2208 DBG(dev, "%s: rx %db, space=%db\n",
2209 ep->ep.name, count, tmp);
2210 req->req.status = -EOVERFLOW;
2211 }
2212 count = tmp;
2213 }
2214 req->req.actual += count;
2215 req->dma_going = 0;
2216 /* complete request */
2217 complete_req(ep, req, 0);
2218
2219 /* next request */
2220 if (!list_empty(&ep->queue) && !ep->halted) {
2221 req = list_entry(ep->queue.next,
2222 struct udc_request,
2223 queue);
2224 /*
2225 * DMA may be already started by udc_queue()
2226 * called by gadget drivers completion
2227 * routine. This happens when queue
2228 * holds one request only.
2229 */
2230 if (req->dma_going == 0) {
2231 /* next dma */
2232 if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2233 goto finished;
2234 /* write desc pointer */
2235 writel(req->td_phys,
2236 &ep->regs->desptr);
2237 req->dma_going = 1;
2238 /* enable DMA */
2239 udc_set_rde(dev);
2240 }
2241 } else {
2242 /*
2243 * implant BNA dummy descriptor to allow
2244 * RXFIFO opening by RDE
2245 */
2246 if (ep->bna_dummy_req) {
2247 /* write desc pointer */
2248 writel(ep->bna_dummy_req->td_phys,
2249 &ep->regs->desptr);
2250 ep->bna_occurred = 0;
2251 }
2252
2253 /*
2254 * schedule timer for setting RDE if queue
2255 * remains empty to allow ep0 packets pass
2256 * through
2257 */
2258 if (set_rde != 0
2259 && !timer_pending(&udc_timer)) {
2260 udc_timer.expires =
2261 jiffies
2262 + HZ*UDC_RDE_TIMER_SECONDS;
2263 set_rde = 1;
2264 if (!stop_timer)
2265 add_timer(&udc_timer);
2266 }
2267 if (ep->num != UDC_EP0OUT_IX)
2268 dev->data_ep_queued = 0;
2269 }
2270
2271 } else {
2272 /*
2273 * RX DMA must be reenabled for each desc in PPBDU mode
2274 * and must be enabled for PPBNDU mode in case of BNA
2275 */
2276 udc_set_rde(dev);
2277 }
2278
2279 } else if (ep->cancel_transfer) {
2280 ret_val = IRQ_HANDLED;
2281 ep->cancel_transfer = 0;
2282 }
2283
2284 /* check pending CNAKS */
2285 if (cnak_pending) {
2286 /* CNAk processing when rxfifo empty only */
2287 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2288 udc_process_cnak_queue(dev);
2289 }
2290
2291 /* clear OUT bits in ep status */
2292 writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2293 finished:
2294 return ret_val;
2295 }
2296
2297 /* Interrupt handler for data IN traffic */
udc_data_in_isr(struct udc * dev,int ep_ix)2298 static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2299 {
2300 irqreturn_t ret_val = IRQ_NONE;
2301 u32 tmp;
2302 u32 epsts;
2303 struct udc_ep *ep;
2304 struct udc_request *req;
2305 struct udc_data_dma *td;
2306 unsigned len;
2307
2308 ep = &dev->ep[ep_ix];
2309
2310 epsts = readl(&ep->regs->sts);
2311 if (use_dma) {
2312 /* BNA ? */
2313 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2314 dev_err(dev->dev,
2315 "BNA ep%din occurred - DESPTR = %08lx\n",
2316 ep->num,
2317 (unsigned long) readl(&ep->regs->desptr));
2318
2319 /* clear BNA */
2320 writel(epsts, &ep->regs->sts);
2321 ret_val = IRQ_HANDLED;
2322 goto finished;
2323 }
2324 }
2325 /* HE event ? */
2326 if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2327 dev_err(dev->dev,
2328 "HE ep%dn occurred - DESPTR = %08lx\n",
2329 ep->num, (unsigned long) readl(&ep->regs->desptr));
2330
2331 /* clear HE */
2332 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2333 ret_val = IRQ_HANDLED;
2334 goto finished;
2335 }
2336
2337 /* DMA completion */
2338 if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2339 VDBG(dev, "TDC set- completion\n");
2340 ret_val = IRQ_HANDLED;
2341 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2342 req = list_entry(ep->queue.next,
2343 struct udc_request, queue);
2344 /*
2345 * length bytes transferred
2346 * check dma done of last desc. in PPBDU mode
2347 */
2348 if (use_dma_ppb_du) {
2349 td = udc_get_last_dma_desc(req);
2350 if (td)
2351 req->req.actual = req->req.length;
2352 } else {
2353 /* assume all bytes transferred */
2354 req->req.actual = req->req.length;
2355 }
2356
2357 if (req->req.actual == req->req.length) {
2358 /* complete req */
2359 complete_req(ep, req, 0);
2360 req->dma_going = 0;
2361 /* further request available ? */
2362 if (list_empty(&ep->queue)) {
2363 /* disable interrupt */
2364 tmp = readl(&dev->regs->ep_irqmsk);
2365 tmp |= AMD_BIT(ep->num);
2366 writel(tmp, &dev->regs->ep_irqmsk);
2367 }
2368 }
2369 }
2370 ep->cancel_transfer = 0;
2371
2372 }
2373 /*
2374 * status reg has IN bit set and TDC not set (if TDC was handled,
2375 * IN must not be handled (UDC defect) ?
2376 */
2377 if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2378 && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2379 ret_val = IRQ_HANDLED;
2380 if (!list_empty(&ep->queue)) {
2381 /* next request */
2382 req = list_entry(ep->queue.next,
2383 struct udc_request, queue);
2384 /* FIFO mode */
2385 if (!use_dma) {
2386 /* write fifo */
2387 udc_txfifo_write(ep, &req->req);
2388 len = req->req.length - req->req.actual;
2389 if (len > ep->ep.maxpacket)
2390 len = ep->ep.maxpacket;
2391 req->req.actual += len;
2392 if (req->req.actual == req->req.length
2393 || (len != ep->ep.maxpacket)) {
2394 /* complete req */
2395 complete_req(ep, req, 0);
2396 }
2397 /* DMA */
2398 } else if (req && !req->dma_going) {
2399 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2400 req, req->td_data);
2401 if (req->td_data) {
2402
2403 req->dma_going = 1;
2404
2405 /*
2406 * unset L bit of first desc.
2407 * for chain
2408 */
2409 if (use_dma_ppb && req->req.length >
2410 ep->ep.maxpacket) {
2411 req->td_data->status &=
2412 AMD_CLEAR_BIT(
2413 UDC_DMA_IN_STS_L);
2414 }
2415
2416 /* write desc pointer */
2417 writel(req->td_phys, &ep->regs->desptr);
2418
2419 /* set HOST READY */
2420 req->td_data->status =
2421 AMD_ADDBITS(
2422 req->td_data->status,
2423 UDC_DMA_IN_STS_BS_HOST_READY,
2424 UDC_DMA_IN_STS_BS);
2425
2426 /* set poll demand bit */
2427 tmp = readl(&ep->regs->ctl);
2428 tmp |= AMD_BIT(UDC_EPCTL_P);
2429 writel(tmp, &ep->regs->ctl);
2430 }
2431 }
2432
2433 } else if (!use_dma && ep->in) {
2434 /* disable interrupt */
2435 tmp = readl(
2436 &dev->regs->ep_irqmsk);
2437 tmp |= AMD_BIT(ep->num);
2438 writel(tmp,
2439 &dev->regs->ep_irqmsk);
2440 }
2441 }
2442 /* clear status bits */
2443 writel(epsts, &ep->regs->sts);
2444
2445 finished:
2446 return ret_val;
2447
2448 }
2449
2450 /* Interrupt handler for Control OUT traffic */
udc_control_out_isr(struct udc * dev)2451 static irqreturn_t udc_control_out_isr(struct udc *dev)
2452 __releases(dev->lock)
2453 __acquires(dev->lock)
2454 {
2455 irqreturn_t ret_val = IRQ_NONE;
2456 u32 tmp;
2457 int setup_supported;
2458 u32 count;
2459 int set = 0;
2460 struct udc_ep *ep;
2461 struct udc_ep *ep_tmp;
2462
2463 ep = &dev->ep[UDC_EP0OUT_IX];
2464
2465 /* clear irq */
2466 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2467
2468 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2469 /* check BNA and clear if set */
2470 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2471 VDBG(dev, "ep0: BNA set\n");
2472 writel(AMD_BIT(UDC_EPSTS_BNA),
2473 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2474 ep->bna_occurred = 1;
2475 ret_val = IRQ_HANDLED;
2476 goto finished;
2477 }
2478
2479 /* type of data: SETUP or DATA 0 bytes */
2480 tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2481 VDBG(dev, "data_typ = %x\n", tmp);
2482
2483 /* setup data */
2484 if (tmp == UDC_EPSTS_OUT_SETUP) {
2485 ret_val = IRQ_HANDLED;
2486
2487 ep->dev->stall_ep0in = 0;
2488 dev->waiting_zlp_ack_ep0in = 0;
2489
2490 /* set NAK for EP0_IN */
2491 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2492 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2493 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2494 dev->ep[UDC_EP0IN_IX].naking = 1;
2495 /* get setup data */
2496 if (use_dma) {
2497
2498 /* clear OUT bits in ep status */
2499 writel(UDC_EPSTS_OUT_CLEAR,
2500 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2501
2502 setup_data.data[0] =
2503 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2504 setup_data.data[1] =
2505 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2506 /* set HOST READY */
2507 dev->ep[UDC_EP0OUT_IX].td_stp->status =
2508 UDC_DMA_STP_STS_BS_HOST_READY;
2509 } else {
2510 /* read fifo */
2511 udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2512 }
2513
2514 /* determine direction of control data */
2515 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2516 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2517 /* enable RDE */
2518 udc_ep0_set_rde(dev);
2519 set = 0;
2520 } else {
2521 dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2522 /*
2523 * implant BNA dummy descriptor to allow RXFIFO opening
2524 * by RDE
2525 */
2526 if (ep->bna_dummy_req) {
2527 /* write desc pointer */
2528 writel(ep->bna_dummy_req->td_phys,
2529 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2530 ep->bna_occurred = 0;
2531 }
2532
2533 set = 1;
2534 dev->ep[UDC_EP0OUT_IX].naking = 1;
2535 /*
2536 * setup timer for enabling RDE (to not enable
2537 * RXFIFO DMA for data to early)
2538 */
2539 set_rde = 1;
2540 if (!timer_pending(&udc_timer)) {
2541 udc_timer.expires = jiffies +
2542 HZ/UDC_RDE_TIMER_DIV;
2543 if (!stop_timer)
2544 add_timer(&udc_timer);
2545 }
2546 }
2547
2548 /*
2549 * mass storage reset must be processed here because
2550 * next packet may be a CLEAR_FEATURE HALT which would not
2551 * clear the stall bit when no STALL handshake was received
2552 * before (autostall can cause this)
2553 */
2554 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2555 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2556 DBG(dev, "MSC Reset\n");
2557 /*
2558 * clear stall bits
2559 * only one IN and OUT endpoints are handled
2560 */
2561 ep_tmp = &udc->ep[UDC_EPIN_IX];
2562 udc_set_halt(&ep_tmp->ep, 0);
2563 ep_tmp = &udc->ep[UDC_EPOUT_IX];
2564 udc_set_halt(&ep_tmp->ep, 0);
2565 }
2566
2567 /* call gadget with setup data received */
2568 spin_unlock(&dev->lock);
2569 setup_supported = dev->driver->setup(&dev->gadget,
2570 &setup_data.request);
2571 spin_lock(&dev->lock);
2572
2573 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2574 /* ep0 in returns data (not zlp) on IN phase */
2575 if (setup_supported >= 0 && setup_supported <
2576 UDC_EP0IN_MAXPACKET) {
2577 /* clear NAK by writing CNAK in EP0_IN */
2578 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2579 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2580 dev->ep[UDC_EP0IN_IX].naking = 0;
2581 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2582
2583 /* if unsupported request then stall */
2584 } else if (setup_supported < 0) {
2585 tmp |= AMD_BIT(UDC_EPCTL_S);
2586 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2587 } else
2588 dev->waiting_zlp_ack_ep0in = 1;
2589
2590
2591 /* clear NAK by writing CNAK in EP0_OUT */
2592 if (!set) {
2593 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2594 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2595 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2596 dev->ep[UDC_EP0OUT_IX].naking = 0;
2597 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2598 }
2599
2600 if (!use_dma) {
2601 /* clear OUT bits in ep status */
2602 writel(UDC_EPSTS_OUT_CLEAR,
2603 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2604 }
2605
2606 /* data packet 0 bytes */
2607 } else if (tmp == UDC_EPSTS_OUT_DATA) {
2608 /* clear OUT bits in ep status */
2609 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2610
2611 /* get setup data: only 0 packet */
2612 if (use_dma) {
2613 /* no req if 0 packet, just reactivate */
2614 if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2615 VDBG(dev, "ZLP\n");
2616
2617 /* set HOST READY */
2618 dev->ep[UDC_EP0OUT_IX].td->status =
2619 AMD_ADDBITS(
2620 dev->ep[UDC_EP0OUT_IX].td->status,
2621 UDC_DMA_OUT_STS_BS_HOST_READY,
2622 UDC_DMA_OUT_STS_BS);
2623 /* enable RDE */
2624 udc_ep0_set_rde(dev);
2625 ret_val = IRQ_HANDLED;
2626
2627 } else {
2628 /* control write */
2629 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2630 /* re-program desc. pointer for possible ZLPs */
2631 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2632 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2633 /* enable RDE */
2634 udc_ep0_set_rde(dev);
2635 }
2636 } else {
2637
2638 /* received number bytes */
2639 count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2640 count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2641 /* out data for fifo mode not working */
2642 count = 0;
2643
2644 /* 0 packet or real data ? */
2645 if (count != 0) {
2646 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2647 } else {
2648 /* dummy read confirm */
2649 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2650 ret_val = IRQ_HANDLED;
2651 }
2652 }
2653 }
2654
2655 /* check pending CNAKS */
2656 if (cnak_pending) {
2657 /* CNAk processing when rxfifo empty only */
2658 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2659 udc_process_cnak_queue(dev);
2660 }
2661
2662 finished:
2663 return ret_val;
2664 }
2665
2666 /* Interrupt handler for Control IN traffic */
udc_control_in_isr(struct udc * dev)2667 static irqreturn_t udc_control_in_isr(struct udc *dev)
2668 {
2669 irqreturn_t ret_val = IRQ_NONE;
2670 u32 tmp;
2671 struct udc_ep *ep;
2672 struct udc_request *req;
2673 unsigned len;
2674
2675 ep = &dev->ep[UDC_EP0IN_IX];
2676
2677 /* clear irq */
2678 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2679
2680 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2681 /* DMA completion */
2682 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
2683 VDBG(dev, "isr: TDC clear\n");
2684 ret_val = IRQ_HANDLED;
2685
2686 /* clear TDC bit */
2687 writel(AMD_BIT(UDC_EPSTS_TDC),
2688 &dev->ep[UDC_EP0IN_IX].regs->sts);
2689
2690 /* status reg has IN bit set ? */
2691 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2692 ret_val = IRQ_HANDLED;
2693
2694 if (ep->dma) {
2695 /* clear IN bit */
2696 writel(AMD_BIT(UDC_EPSTS_IN),
2697 &dev->ep[UDC_EP0IN_IX].regs->sts);
2698 }
2699 if (dev->stall_ep0in) {
2700 DBG(dev, "stall ep0in\n");
2701 /* halt ep0in */
2702 tmp = readl(&ep->regs->ctl);
2703 tmp |= AMD_BIT(UDC_EPCTL_S);
2704 writel(tmp, &ep->regs->ctl);
2705 } else {
2706 if (!list_empty(&ep->queue)) {
2707 /* next request */
2708 req = list_entry(ep->queue.next,
2709 struct udc_request, queue);
2710
2711 if (ep->dma) {
2712 /* write desc pointer */
2713 writel(req->td_phys, &ep->regs->desptr);
2714 /* set HOST READY */
2715 req->td_data->status =
2716 AMD_ADDBITS(
2717 req->td_data->status,
2718 UDC_DMA_STP_STS_BS_HOST_READY,
2719 UDC_DMA_STP_STS_BS);
2720
2721 /* set poll demand bit */
2722 tmp =
2723 readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2724 tmp |= AMD_BIT(UDC_EPCTL_P);
2725 writel(tmp,
2726 &dev->ep[UDC_EP0IN_IX].regs->ctl);
2727
2728 /* all bytes will be transferred */
2729 req->req.actual = req->req.length;
2730
2731 /* complete req */
2732 complete_req(ep, req, 0);
2733
2734 } else {
2735 /* write fifo */
2736 udc_txfifo_write(ep, &req->req);
2737
2738 /* lengh bytes transferred */
2739 len = req->req.length - req->req.actual;
2740 if (len > ep->ep.maxpacket)
2741 len = ep->ep.maxpacket;
2742
2743 req->req.actual += len;
2744 if (req->req.actual == req->req.length
2745 || (len != ep->ep.maxpacket)) {
2746 /* complete req */
2747 complete_req(ep, req, 0);
2748 }
2749 }
2750
2751 }
2752 }
2753 ep->halted = 0;
2754 dev->stall_ep0in = 0;
2755 if (!ep->dma) {
2756 /* clear IN bit */
2757 writel(AMD_BIT(UDC_EPSTS_IN),
2758 &dev->ep[UDC_EP0IN_IX].regs->sts);
2759 }
2760 }
2761
2762 return ret_val;
2763 }
2764
2765
2766 /* Interrupt handler for global device events */
udc_dev_isr(struct udc * dev,u32 dev_irq)2767 static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2768 __releases(dev->lock)
2769 __acquires(dev->lock)
2770 {
2771 irqreturn_t ret_val = IRQ_NONE;
2772 u32 tmp;
2773 u32 cfg;
2774 struct udc_ep *ep;
2775 u16 i;
2776 u8 udc_csr_epix;
2777
2778 /* SET_CONFIG irq ? */
2779 if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2780 ret_val = IRQ_HANDLED;
2781
2782 /* read config value */
2783 tmp = readl(&dev->regs->sts);
2784 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2785 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2786 dev->cur_config = cfg;
2787 dev->set_cfg_not_acked = 1;
2788
2789 /* make usb request for gadget driver */
2790 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2791 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
2792 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
2793
2794 /* programm the NE registers */
2795 for (i = 0; i < UDC_EP_NUM; i++) {
2796 ep = &dev->ep[i];
2797 if (ep->in) {
2798
2799 /* ep ix in UDC CSR register space */
2800 udc_csr_epix = ep->num;
2801
2802
2803 /* OUT ep */
2804 } else {
2805 /* ep ix in UDC CSR register space */
2806 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2807 }
2808
2809 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2810 /* ep cfg */
2811 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2812 UDC_CSR_NE_CFG);
2813 /* write reg */
2814 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2815
2816 /* clear stall bits */
2817 ep->halted = 0;
2818 tmp = readl(&ep->regs->ctl);
2819 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2820 writel(tmp, &ep->regs->ctl);
2821 }
2822 /* call gadget zero with setup data received */
2823 spin_unlock(&dev->lock);
2824 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2825 spin_lock(&dev->lock);
2826
2827 } /* SET_INTERFACE ? */
2828 if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2829 ret_val = IRQ_HANDLED;
2830
2831 dev->set_cfg_not_acked = 1;
2832 /* read interface and alt setting values */
2833 tmp = readl(&dev->regs->sts);
2834 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2835 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2836
2837 /* make usb request for gadget driver */
2838 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2839 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2840 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
2841 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2842 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
2843
2844 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2845 dev->cur_alt, dev->cur_intf);
2846
2847 /* programm the NE registers */
2848 for (i = 0; i < UDC_EP_NUM; i++) {
2849 ep = &dev->ep[i];
2850 if (ep->in) {
2851
2852 /* ep ix in UDC CSR register space */
2853 udc_csr_epix = ep->num;
2854
2855
2856 /* OUT ep */
2857 } else {
2858 /* ep ix in UDC CSR register space */
2859 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2860 }
2861
2862 /* UDC CSR reg */
2863 /* set ep values */
2864 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2865 /* ep interface */
2866 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2867 UDC_CSR_NE_INTF);
2868 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2869 /* ep alt */
2870 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2871 UDC_CSR_NE_ALT);
2872 /* write reg */
2873 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2874
2875 /* clear stall bits */
2876 ep->halted = 0;
2877 tmp = readl(&ep->regs->ctl);
2878 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2879 writel(tmp, &ep->regs->ctl);
2880 }
2881
2882 /* call gadget zero with setup data received */
2883 spin_unlock(&dev->lock);
2884 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2885 spin_lock(&dev->lock);
2886
2887 } /* USB reset */
2888 if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2889 DBG(dev, "USB Reset interrupt\n");
2890 ret_val = IRQ_HANDLED;
2891
2892 /* allow soft reset when suspend occurs */
2893 soft_reset_occured = 0;
2894
2895 dev->waiting_zlp_ack_ep0in = 0;
2896 dev->set_cfg_not_acked = 0;
2897
2898 /* mask not needed interrupts */
2899 udc_mask_unused_interrupts(dev);
2900
2901 /* call gadget to resume and reset configs etc. */
2902 spin_unlock(&dev->lock);
2903 if (dev->sys_suspended && dev->driver->resume) {
2904 dev->driver->resume(&dev->gadget);
2905 dev->sys_suspended = 0;
2906 }
2907 usb_gadget_udc_reset(&dev->gadget, dev->driver);
2908 spin_lock(&dev->lock);
2909
2910 /* disable ep0 to empty req queue */
2911 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2912 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2913
2914 /* soft reset when rxfifo not empty */
2915 tmp = readl(&dev->regs->sts);
2916 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2917 && !soft_reset_after_usbreset_occured) {
2918 udc_soft_reset(dev);
2919 soft_reset_after_usbreset_occured++;
2920 }
2921
2922 /*
2923 * DMA reset to kill potential old DMA hw hang,
2924 * POLL bit is already reset by ep_init() through
2925 * disconnect()
2926 */
2927 DBG(dev, "DMA machine reset\n");
2928 tmp = readl(&dev->regs->cfg);
2929 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2930 writel(tmp, &dev->regs->cfg);
2931
2932 /* put into initial config */
2933 udc_basic_init(dev);
2934
2935 /* enable device setup interrupts */
2936 udc_enable_dev_setup_interrupts(dev);
2937
2938 /* enable suspend interrupt */
2939 tmp = readl(&dev->regs->irqmsk);
2940 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2941 writel(tmp, &dev->regs->irqmsk);
2942
2943 } /* USB suspend */
2944 if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2945 DBG(dev, "USB Suspend interrupt\n");
2946 ret_val = IRQ_HANDLED;
2947 if (dev->driver->suspend) {
2948 spin_unlock(&dev->lock);
2949 dev->sys_suspended = 1;
2950 dev->driver->suspend(&dev->gadget);
2951 spin_lock(&dev->lock);
2952 }
2953 } /* new speed ? */
2954 if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
2955 DBG(dev, "ENUM interrupt\n");
2956 ret_val = IRQ_HANDLED;
2957 soft_reset_after_usbreset_occured = 0;
2958
2959 /* disable ep0 to empty req queue */
2960 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2961 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2962
2963 /* link up all endpoints */
2964 udc_setup_endpoints(dev);
2965 dev_info(dev->dev, "Connect: %s\n",
2966 usb_speed_string(dev->gadget.speed));
2967
2968 /* init ep 0 */
2969 activate_control_endpoints(dev);
2970
2971 /* enable ep0 interrupts */
2972 udc_enable_ep0_interrupts(dev);
2973 }
2974 /* session valid change interrupt */
2975 if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
2976 DBG(dev, "USB SVC interrupt\n");
2977 ret_val = IRQ_HANDLED;
2978
2979 /* check that session is not valid to detect disconnect */
2980 tmp = readl(&dev->regs->sts);
2981 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
2982 /* disable suspend interrupt */
2983 tmp = readl(&dev->regs->irqmsk);
2984 tmp |= AMD_BIT(UDC_DEVINT_US);
2985 writel(tmp, &dev->regs->irqmsk);
2986 DBG(dev, "USB Disconnect (session valid low)\n");
2987 /* cleanup on disconnect */
2988 usb_disconnect(udc);
2989 }
2990
2991 }
2992
2993 return ret_val;
2994 }
2995
2996 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
udc_irq(int irq,void * pdev)2997 irqreturn_t udc_irq(int irq, void *pdev)
2998 {
2999 struct udc *dev = pdev;
3000 u32 reg;
3001 u16 i;
3002 u32 ep_irq;
3003 irqreturn_t ret_val = IRQ_NONE;
3004
3005 spin_lock(&dev->lock);
3006
3007 /* check for ep irq */
3008 reg = readl(&dev->regs->ep_irqsts);
3009 if (reg) {
3010 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0))
3011 ret_val |= udc_control_out_isr(dev);
3012 if (reg & AMD_BIT(UDC_EPINT_IN_EP0))
3013 ret_val |= udc_control_in_isr(dev);
3014
3015 /*
3016 * data endpoint
3017 * iterate ep's
3018 */
3019 for (i = 1; i < UDC_EP_NUM; i++) {
3020 ep_irq = 1 << i;
3021 if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0)
3022 continue;
3023
3024 /* clear irq status */
3025 writel(ep_irq, &dev->regs->ep_irqsts);
3026
3027 /* irq for out ep ? */
3028 if (i > UDC_EPIN_NUM)
3029 ret_val |= udc_data_out_isr(dev, i);
3030 else
3031 ret_val |= udc_data_in_isr(dev, i);
3032 }
3033
3034 }
3035
3036
3037 /* check for dev irq */
3038 reg = readl(&dev->regs->irqsts);
3039 if (reg) {
3040 /* clear irq */
3041 writel(reg, &dev->regs->irqsts);
3042 ret_val |= udc_dev_isr(dev, reg);
3043 }
3044
3045
3046 spin_unlock(&dev->lock);
3047 return ret_val;
3048 }
3049 EXPORT_SYMBOL_GPL(udc_irq);
3050
3051 /* Tears down device */
gadget_release(struct device * pdev)3052 void gadget_release(struct device *pdev)
3053 {
3054 struct amd5536udc *dev = dev_get_drvdata(pdev);
3055 kfree(dev);
3056 }
3057 EXPORT_SYMBOL_GPL(gadget_release);
3058
3059 /* Cleanup on device remove */
udc_remove(struct udc * dev)3060 void udc_remove(struct udc *dev)
3061 {
3062 /* remove timer */
3063 stop_timer++;
3064 if (timer_pending(&udc_timer))
3065 wait_for_completion(&on_exit);
3066 del_timer_sync(&udc_timer);
3067 /* remove pollstall timer */
3068 stop_pollstall_timer++;
3069 if (timer_pending(&udc_pollstall_timer))
3070 wait_for_completion(&on_pollstall_exit);
3071 del_timer_sync(&udc_pollstall_timer);
3072 udc = NULL;
3073 }
3074 EXPORT_SYMBOL_GPL(udc_remove);
3075
3076 /* free all the dma pools */
free_dma_pools(struct udc * dev)3077 void free_dma_pools(struct udc *dev)
3078 {
3079 dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td,
3080 dev->ep[UDC_EP0OUT_IX].td_phys);
3081 dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td_stp,
3082 dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3083 dma_pool_destroy(dev->stp_requests);
3084 dma_pool_destroy(dev->data_requests);
3085 }
3086 EXPORT_SYMBOL_GPL(free_dma_pools);
3087
3088 /* create dma pools on init */
init_dma_pools(struct udc * dev)3089 int init_dma_pools(struct udc *dev)
3090 {
3091 struct udc_stp_dma *td_stp;
3092 struct udc_data_dma *td_data;
3093 int retval;
3094
3095 /* consistent DMA mode setting ? */
3096 if (use_dma_ppb) {
3097 use_dma_bufferfill_mode = 0;
3098 } else {
3099 use_dma_ppb_du = 0;
3100 use_dma_bufferfill_mode = 1;
3101 }
3102
3103 /* DMA setup */
3104 dev->data_requests = dma_pool_create("data_requests", dev->dev,
3105 sizeof(struct udc_data_dma), 0, 0);
3106 if (!dev->data_requests) {
3107 DBG(dev, "can't get request data pool\n");
3108 return -ENOMEM;
3109 }
3110
3111 /* EP0 in dma regs = dev control regs */
3112 dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
3113
3114 /* dma desc for setup data */
3115 dev->stp_requests = dma_pool_create("setup requests", dev->dev,
3116 sizeof(struct udc_stp_dma), 0, 0);
3117 if (!dev->stp_requests) {
3118 DBG(dev, "can't get stp request pool\n");
3119 retval = -ENOMEM;
3120 goto err_create_dma_pool;
3121 }
3122 /* setup */
3123 td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3124 &dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3125 if (!td_stp) {
3126 retval = -ENOMEM;
3127 goto err_alloc_dma;
3128 }
3129 dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
3130
3131 /* data: 0 packets !? */
3132 td_data = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3133 &dev->ep[UDC_EP0OUT_IX].td_phys);
3134 if (!td_data) {
3135 retval = -ENOMEM;
3136 goto err_alloc_phys;
3137 }
3138 dev->ep[UDC_EP0OUT_IX].td = td_data;
3139 return 0;
3140
3141 err_alloc_phys:
3142 dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td_stp,
3143 dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3144 err_alloc_dma:
3145 dma_pool_destroy(dev->stp_requests);
3146 dev->stp_requests = NULL;
3147 err_create_dma_pool:
3148 dma_pool_destroy(dev->data_requests);
3149 dev->data_requests = NULL;
3150 return retval;
3151 }
3152 EXPORT_SYMBOL_GPL(init_dma_pools);
3153
3154 /* general probe */
udc_probe(struct udc * dev)3155 int udc_probe(struct udc *dev)
3156 {
3157 char tmp[128];
3158 u32 reg;
3159 int retval;
3160
3161 /* device struct setup */
3162 dev->gadget.ops = &udc_ops;
3163
3164 dev_set_name(&dev->gadget.dev, "gadget");
3165 dev->gadget.name = name;
3166 dev->gadget.max_speed = USB_SPEED_HIGH;
3167
3168 /* init registers, interrupts, ... */
3169 startup_registers(dev);
3170
3171 dev_info(dev->dev, "%s\n", mod_desc);
3172
3173 snprintf(tmp, sizeof(tmp), "%d", dev->irq);
3174
3175 /* Print this device info for AMD chips only*/
3176 if (dev->chiprev == UDC_HSA0_REV ||
3177 dev->chiprev == UDC_HSB1_REV) {
3178 dev_info(dev->dev, "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3179 tmp, dev->phys_addr, dev->chiprev,
3180 (dev->chiprev == UDC_HSA0_REV) ?
3181 "A0" : "B1");
3182 strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3183 if (dev->chiprev == UDC_HSA0_REV) {
3184 dev_err(dev->dev, "chip revision is A0; too old\n");
3185 retval = -ENODEV;
3186 goto finished;
3187 }
3188 dev_info(dev->dev,
3189 "driver version: %s(for Geode5536 B1)\n", tmp);
3190 }
3191
3192 udc = dev;
3193
3194 retval = usb_add_gadget_udc_release(udc->dev, &dev->gadget,
3195 gadget_release);
3196 if (retval)
3197 goto finished;
3198
3199 /* timer init */
3200 timer_setup(&udc_timer, udc_timer_function, 0);
3201 timer_setup(&udc_pollstall_timer, udc_pollstall_timer_function, 0);
3202
3203 /* set SD */
3204 reg = readl(&dev->regs->ctl);
3205 reg |= AMD_BIT(UDC_DEVCTL_SD);
3206 writel(reg, &dev->regs->ctl);
3207
3208 /* print dev register info */
3209 print_regs(dev);
3210
3211 return 0;
3212
3213 finished:
3214 return retval;
3215 }
3216 EXPORT_SYMBOL_GPL(udc_probe);
3217
3218 MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
3219 MODULE_AUTHOR("Thomas Dahlmann");
3220 MODULE_LICENSE("GPL");
3221
