1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #ifndef __HCLGE_MAIN_H
5 #define __HCLGE_MAIN_H
6 #include <linux/fs.h>
7 #include <linux/types.h>
8 #include <linux/phy.h>
9 #include <linux/if_vlan.h>
10
11 #include "hclge_cmd.h"
12 #include "hnae3.h"
13
14 #define HCLGE_MOD_VERSION "1.0"
15 #define HCLGE_DRIVER_NAME "hclge"
16
17 #define HCLGE_INVALID_VPORT 0xffff
18
19 #define HCLGE_PF_CFG_BLOCK_SIZE 32
20 #define HCLGE_PF_CFG_DESC_NUM \
21 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
22
23 #define HCLGE_VECTOR_REG_BASE 0x20000
24 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400
25
26 #define HCLGE_VECTOR_REG_OFFSET 0x4
27 #define HCLGE_VECTOR_VF_OFFSET 0x100000
28
29 #define HCLGE_RSS_IND_TBL_SIZE 512
30 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0)
31 #define HCLGE_RSS_KEY_SIZE 40
32 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0
33 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1
34 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2
35 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0)
36 #define HCLGE_RSS_CFG_TBL_NUM \
37 (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE)
38
39 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0)
40 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0)
41 #define HCLGE_D_PORT_BIT BIT(0)
42 #define HCLGE_S_PORT_BIT BIT(1)
43 #define HCLGE_D_IP_BIT BIT(2)
44 #define HCLGE_S_IP_BIT BIT(3)
45 #define HCLGE_V_TAG_BIT BIT(4)
46
47 #define HCLGE_RSS_TC_SIZE_0 1
48 #define HCLGE_RSS_TC_SIZE_1 2
49 #define HCLGE_RSS_TC_SIZE_2 4
50 #define HCLGE_RSS_TC_SIZE_3 8
51 #define HCLGE_RSS_TC_SIZE_4 16
52 #define HCLGE_RSS_TC_SIZE_5 32
53 #define HCLGE_RSS_TC_SIZE_6 64
54 #define HCLGE_RSS_TC_SIZE_7 128
55
56 #define HCLGE_MTA_TBL_SIZE 4096
57
58 #define HCLGE_TQP_RESET_TRY_TIMES 10
59
60 #define HCLGE_PHY_PAGE_MDIX 0
61 #define HCLGE_PHY_PAGE_COPPER 0
62
63 /* Page Selection Reg. */
64 #define HCLGE_PHY_PAGE_REG 22
65
66 /* Copper Specific Control Register */
67 #define HCLGE_PHY_CSC_REG 16
68
69 /* Copper Specific Status Register */
70 #define HCLGE_PHY_CSS_REG 17
71
72 #define HCLGE_PHY_MDIX_CTRL_S 5
73 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
74
75 #define HCLGE_PHY_MDIX_STATUS_B 6
76 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11
77
78 /* Factor used to calculate offset and bitmap of VF num */
79 #define HCLGE_VF_NUM_PER_CMD 64
80 #define HCLGE_VF_NUM_PER_BYTE 8
81
82 /* Reset related Registers */
83 #define HCLGE_MISC_RESET_STS_REG 0x20700
84 #define HCLGE_MISC_VECTOR_INT_STS 0x20800
85 #define HCLGE_GLOBAL_RESET_REG 0x20A00
86 #define HCLGE_GLOBAL_RESET_BIT 0
87 #define HCLGE_CORE_RESET_BIT 1
88 #define HCLGE_FUN_RST_ING 0x20C00
89 #define HCLGE_FUN_RST_ING_B 0
90
91 /* Vector0 register bits define */
92 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
93 #define HCLGE_VECTOR0_CORERESET_INT_B 6
94 #define HCLGE_VECTOR0_IMPRESET_INT_B 7
95
96 /* Vector0 interrupt CMDQ event source register(RW) */
97 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100
98 /* CMDQ register bits for RX event(=MBX event) */
99 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1
100
101 #define HCLGE_MAC_DEFAULT_FRAME \
102 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN + ETH_DATA_LEN)
103 #define HCLGE_MAC_MIN_FRAME 64
104 #define HCLGE_MAC_MAX_FRAME 9728
105
106 #define HCLGE_SUPPORT_1G_BIT BIT(0)
107 #define HCLGE_SUPPORT_10G_BIT BIT(1)
108 #define HCLGE_SUPPORT_25G_BIT BIT(2)
109 #define HCLGE_SUPPORT_50G_BIT BIT(3)
110 #define HCLGE_SUPPORT_100G_BIT BIT(4)
111
112 enum HCLGE_DEV_STATE {
113 HCLGE_STATE_REINITING,
114 HCLGE_STATE_DOWN,
115 HCLGE_STATE_DISABLED,
116 HCLGE_STATE_REMOVING,
117 HCLGE_STATE_SERVICE_INITED,
118 HCLGE_STATE_SERVICE_SCHED,
119 HCLGE_STATE_RST_SERVICE_SCHED,
120 HCLGE_STATE_RST_HANDLING,
121 HCLGE_STATE_MBX_SERVICE_SCHED,
122 HCLGE_STATE_MBX_HANDLING,
123 HCLGE_STATE_STATISTICS_UPDATING,
124 HCLGE_STATE_CMD_DISABLE,
125 HCLGE_STATE_MAX
126 };
127
128 enum hclge_evt_cause {
129 HCLGE_VECTOR0_EVENT_RST,
130 HCLGE_VECTOR0_EVENT_MBX,
131 HCLGE_VECTOR0_EVENT_OTHER,
132 };
133
134 #define HCLGE_MPF_ENBALE 1
135
136 enum HCLGE_MAC_SPEED {
137 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */
138 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */
139 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
140 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
141 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
142 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
143 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
144 HCLGE_MAC_SPEED_100G = 100000 /* 100000 Mbps = 100 Gbps */
145 };
146
147 enum HCLGE_MAC_DUPLEX {
148 HCLGE_MAC_HALF,
149 HCLGE_MAC_FULL
150 };
151
152 enum hclge_mta_dmac_sel_type {
153 HCLGE_MAC_ADDR_47_36,
154 HCLGE_MAC_ADDR_46_35,
155 HCLGE_MAC_ADDR_45_34,
156 HCLGE_MAC_ADDR_44_33,
157 };
158
159 struct hclge_mac {
160 u8 phy_addr;
161 u8 flag;
162 u8 media_type;
163 u8 mac_addr[ETH_ALEN];
164 u8 autoneg;
165 u8 duplex;
166 u32 speed;
167 int link; /* store the link status of mac & phy (if phy exit)*/
168 struct phy_device *phydev;
169 struct mii_bus *mdio_bus;
170 phy_interface_t phy_if;
171 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
172 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
173 };
174
175 struct hclge_hw {
176 void __iomem *io_base;
177 struct hclge_mac mac;
178 int num_vec;
179 struct hclge_cmq cmq;
180 };
181
182 /* TQP stats */
183 struct hlcge_tqp_stats {
184 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */
185 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
186 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */
187 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
188 };
189
190 struct hclge_tqp {
191 /* copy of device pointer from pci_dev,
192 * used when perform DMA mapping
193 */
194 struct device *dev;
195 struct hnae3_queue q;
196 struct hlcge_tqp_stats tqp_stats;
197 u16 index; /* Global index in a NIC controller */
198
199 bool alloced;
200 };
201
202 enum hclge_fc_mode {
203 HCLGE_FC_NONE,
204 HCLGE_FC_RX_PAUSE,
205 HCLGE_FC_TX_PAUSE,
206 HCLGE_FC_FULL,
207 HCLGE_FC_PFC,
208 HCLGE_FC_DEFAULT
209 };
210
211 #define HCLGE_PG_NUM 4
212 #define HCLGE_SCH_MODE_SP 0
213 #define HCLGE_SCH_MODE_DWRR 1
214 struct hclge_pg_info {
215 u8 pg_id;
216 u8 pg_sch_mode; /* 0: sp; 1: dwrr */
217 u8 tc_bit_map;
218 u32 bw_limit;
219 u8 tc_dwrr[HNAE3_MAX_TC];
220 };
221
222 struct hclge_tc_info {
223 u8 tc_id;
224 u8 tc_sch_mode; /* 0: sp; 1: dwrr */
225 u8 pgid;
226 u32 bw_limit;
227 };
228
229 struct hclge_cfg {
230 u8 vmdq_vport_num;
231 u8 tc_num;
232 u16 tqp_desc_num;
233 u16 rx_buf_len;
234 u16 rss_size_max;
235 u8 phy_addr;
236 u8 media_type;
237 u8 mac_addr[ETH_ALEN];
238 u8 default_speed;
239 u32 numa_node_map;
240 u8 speed_ability;
241 };
242
243 struct hclge_tm_info {
244 u8 num_tc;
245 u8 num_pg; /* It must be 1 if vNET-Base schd */
246 u8 pg_dwrr[HCLGE_PG_NUM];
247 u8 prio_tc[HNAE3_MAX_USER_PRIO];
248 struct hclge_pg_info pg_info[HCLGE_PG_NUM];
249 struct hclge_tc_info tc_info[HNAE3_MAX_TC];
250 enum hclge_fc_mode fc_mode;
251 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
252 };
253
254 struct hclge_comm_stats_str {
255 char desc[ETH_GSTRING_LEN];
256 unsigned long offset;
257 };
258
259 /* all 64bit stats, opcode id: 0x0030 */
260 struct hclge_64_bit_stats {
261 /* query_igu_stat */
262 u64 igu_rx_oversize_pkt;
263 u64 igu_rx_undersize_pkt;
264 u64 igu_rx_out_all_pkt;
265 u64 igu_rx_uni_pkt;
266 u64 igu_rx_multi_pkt;
267 u64 igu_rx_broad_pkt;
268 u64 rsv0;
269
270 /* query_egu_stat */
271 u64 egu_tx_out_all_pkt;
272 u64 egu_tx_uni_pkt;
273 u64 egu_tx_multi_pkt;
274 u64 egu_tx_broad_pkt;
275
276 /* ssu_ppp packet stats */
277 u64 ssu_ppp_mac_key_num;
278 u64 ssu_ppp_host_key_num;
279 u64 ppp_ssu_mac_rlt_num;
280 u64 ppp_ssu_host_rlt_num;
281
282 /* ssu_tx_in_out_dfx_stats */
283 u64 ssu_tx_in_num;
284 u64 ssu_tx_out_num;
285 /* ssu_rx_in_out_dfx_stats */
286 u64 ssu_rx_in_num;
287 u64 ssu_rx_out_num;
288 };
289
290 /* all 32bit stats, opcode id: 0x0031 */
291 struct hclge_32_bit_stats {
292 u64 igu_rx_err_pkt;
293 u64 igu_rx_no_eof_pkt;
294 u64 igu_rx_no_sof_pkt;
295 u64 egu_tx_1588_pkt;
296 u64 egu_tx_err_pkt;
297 u64 ssu_full_drop_num;
298 u64 ssu_part_drop_num;
299 u64 ppp_key_drop_num;
300 u64 ppp_rlt_drop_num;
301 u64 ssu_key_drop_num;
302 u64 pkt_curr_buf_cnt;
303 u64 qcn_fb_rcv_cnt;
304 u64 qcn_fb_drop_cnt;
305 u64 qcn_fb_invaild_cnt;
306 u64 rsv0;
307 u64 rx_packet_tc0_in_cnt;
308 u64 rx_packet_tc1_in_cnt;
309 u64 rx_packet_tc2_in_cnt;
310 u64 rx_packet_tc3_in_cnt;
311 u64 rx_packet_tc4_in_cnt;
312 u64 rx_packet_tc5_in_cnt;
313 u64 rx_packet_tc6_in_cnt;
314 u64 rx_packet_tc7_in_cnt;
315 u64 rx_packet_tc0_out_cnt;
316 u64 rx_packet_tc1_out_cnt;
317 u64 rx_packet_tc2_out_cnt;
318 u64 rx_packet_tc3_out_cnt;
319 u64 rx_packet_tc4_out_cnt;
320 u64 rx_packet_tc5_out_cnt;
321 u64 rx_packet_tc6_out_cnt;
322 u64 rx_packet_tc7_out_cnt;
323
324 /* Tx packet level statistics */
325 u64 tx_packet_tc0_in_cnt;
326 u64 tx_packet_tc1_in_cnt;
327 u64 tx_packet_tc2_in_cnt;
328 u64 tx_packet_tc3_in_cnt;
329 u64 tx_packet_tc4_in_cnt;
330 u64 tx_packet_tc5_in_cnt;
331 u64 tx_packet_tc6_in_cnt;
332 u64 tx_packet_tc7_in_cnt;
333 u64 tx_packet_tc0_out_cnt;
334 u64 tx_packet_tc1_out_cnt;
335 u64 tx_packet_tc2_out_cnt;
336 u64 tx_packet_tc3_out_cnt;
337 u64 tx_packet_tc4_out_cnt;
338 u64 tx_packet_tc5_out_cnt;
339 u64 tx_packet_tc6_out_cnt;
340 u64 tx_packet_tc7_out_cnt;
341
342 /* packet buffer statistics */
343 u64 pkt_curr_buf_tc0_cnt;
344 u64 pkt_curr_buf_tc1_cnt;
345 u64 pkt_curr_buf_tc2_cnt;
346 u64 pkt_curr_buf_tc3_cnt;
347 u64 pkt_curr_buf_tc4_cnt;
348 u64 pkt_curr_buf_tc5_cnt;
349 u64 pkt_curr_buf_tc6_cnt;
350 u64 pkt_curr_buf_tc7_cnt;
351
352 u64 mb_uncopy_num;
353 u64 lo_pri_unicast_rlt_drop_num;
354 u64 hi_pri_multicast_rlt_drop_num;
355 u64 lo_pri_multicast_rlt_drop_num;
356 u64 rx_oq_drop_pkt_cnt;
357 u64 tx_oq_drop_pkt_cnt;
358 u64 nic_l2_err_drop_pkt_cnt;
359 u64 roc_l2_err_drop_pkt_cnt;
360 };
361
362 /* mac stats ,opcode id: 0x0032 */
363 struct hclge_mac_stats {
364 u64 mac_tx_mac_pause_num;
365 u64 mac_rx_mac_pause_num;
366 u64 mac_tx_pfc_pri0_pkt_num;
367 u64 mac_tx_pfc_pri1_pkt_num;
368 u64 mac_tx_pfc_pri2_pkt_num;
369 u64 mac_tx_pfc_pri3_pkt_num;
370 u64 mac_tx_pfc_pri4_pkt_num;
371 u64 mac_tx_pfc_pri5_pkt_num;
372 u64 mac_tx_pfc_pri6_pkt_num;
373 u64 mac_tx_pfc_pri7_pkt_num;
374 u64 mac_rx_pfc_pri0_pkt_num;
375 u64 mac_rx_pfc_pri1_pkt_num;
376 u64 mac_rx_pfc_pri2_pkt_num;
377 u64 mac_rx_pfc_pri3_pkt_num;
378 u64 mac_rx_pfc_pri4_pkt_num;
379 u64 mac_rx_pfc_pri5_pkt_num;
380 u64 mac_rx_pfc_pri6_pkt_num;
381 u64 mac_rx_pfc_pri7_pkt_num;
382 u64 mac_tx_total_pkt_num;
383 u64 mac_tx_total_oct_num;
384 u64 mac_tx_good_pkt_num;
385 u64 mac_tx_bad_pkt_num;
386 u64 mac_tx_good_oct_num;
387 u64 mac_tx_bad_oct_num;
388 u64 mac_tx_uni_pkt_num;
389 u64 mac_tx_multi_pkt_num;
390 u64 mac_tx_broad_pkt_num;
391 u64 mac_tx_undersize_pkt_num;
392 u64 mac_tx_oversize_pkt_num;
393 u64 mac_tx_64_oct_pkt_num;
394 u64 mac_tx_65_127_oct_pkt_num;
395 u64 mac_tx_128_255_oct_pkt_num;
396 u64 mac_tx_256_511_oct_pkt_num;
397 u64 mac_tx_512_1023_oct_pkt_num;
398 u64 mac_tx_1024_1518_oct_pkt_num;
399 u64 mac_tx_1519_2047_oct_pkt_num;
400 u64 mac_tx_2048_4095_oct_pkt_num;
401 u64 mac_tx_4096_8191_oct_pkt_num;
402 u64 rsv0;
403 u64 mac_tx_8192_9216_oct_pkt_num;
404 u64 mac_tx_9217_12287_oct_pkt_num;
405 u64 mac_tx_12288_16383_oct_pkt_num;
406 u64 mac_tx_1519_max_good_oct_pkt_num;
407 u64 mac_tx_1519_max_bad_oct_pkt_num;
408
409 u64 mac_rx_total_pkt_num;
410 u64 mac_rx_total_oct_num;
411 u64 mac_rx_good_pkt_num;
412 u64 mac_rx_bad_pkt_num;
413 u64 mac_rx_good_oct_num;
414 u64 mac_rx_bad_oct_num;
415 u64 mac_rx_uni_pkt_num;
416 u64 mac_rx_multi_pkt_num;
417 u64 mac_rx_broad_pkt_num;
418 u64 mac_rx_undersize_pkt_num;
419 u64 mac_rx_oversize_pkt_num;
420 u64 mac_rx_64_oct_pkt_num;
421 u64 mac_rx_65_127_oct_pkt_num;
422 u64 mac_rx_128_255_oct_pkt_num;
423 u64 mac_rx_256_511_oct_pkt_num;
424 u64 mac_rx_512_1023_oct_pkt_num;
425 u64 mac_rx_1024_1518_oct_pkt_num;
426 u64 mac_rx_1519_2047_oct_pkt_num;
427 u64 mac_rx_2048_4095_oct_pkt_num;
428 u64 mac_rx_4096_8191_oct_pkt_num;
429 u64 rsv1;
430 u64 mac_rx_8192_9216_oct_pkt_num;
431 u64 mac_rx_9217_12287_oct_pkt_num;
432 u64 mac_rx_12288_16383_oct_pkt_num;
433 u64 mac_rx_1519_max_good_oct_pkt_num;
434 u64 mac_rx_1519_max_bad_oct_pkt_num;
435
436 u64 mac_tx_fragment_pkt_num;
437 u64 mac_tx_undermin_pkt_num;
438 u64 mac_tx_jabber_pkt_num;
439 u64 mac_tx_err_all_pkt_num;
440 u64 mac_tx_from_app_good_pkt_num;
441 u64 mac_tx_from_app_bad_pkt_num;
442 u64 mac_rx_fragment_pkt_num;
443 u64 mac_rx_undermin_pkt_num;
444 u64 mac_rx_jabber_pkt_num;
445 u64 mac_rx_fcs_err_pkt_num;
446 u64 mac_rx_send_app_good_pkt_num;
447 u64 mac_rx_send_app_bad_pkt_num;
448 };
449
450 #define HCLGE_STATS_TIMER_INTERVAL (60 * 5)
451 struct hclge_hw_stats {
452 struct hclge_mac_stats mac_stats;
453 struct hclge_64_bit_stats all_64_bit_stats;
454 struct hclge_32_bit_stats all_32_bit_stats;
455 u32 stats_timer;
456 };
457
458 struct hclge_vlan_type_cfg {
459 u16 rx_ot_fst_vlan_type;
460 u16 rx_ot_sec_vlan_type;
461 u16 rx_in_fst_vlan_type;
462 u16 rx_in_sec_vlan_type;
463 u16 tx_ot_vlan_type;
464 u16 tx_in_vlan_type;
465 };
466
467 #define HCLGE_VPORT_NUM 256
468 struct hclge_dev {
469 struct pci_dev *pdev;
470 struct hnae3_ae_dev *ae_dev;
471 struct hclge_hw hw;
472 struct hclge_misc_vector misc_vector;
473 struct hclge_hw_stats hw_stats;
474 unsigned long state;
475
476 enum hnae3_reset_type reset_type;
477 unsigned long reset_request; /* reset has been requested */
478 unsigned long reset_pending; /* client rst is pending to be served */
479 u32 fw_version;
480 u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */
481 u16 num_tqps; /* Num task queue pairs of this PF */
482 u16 num_req_vfs; /* Num VFs requested for this PF */
483
484 u16 base_tqp_pid; /* Base task tqp physical id of this PF */
485 u16 alloc_rss_size; /* Allocated RSS task queue */
486 u16 rss_size_max; /* HW defined max RSS task queue */
487
488 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */
489 u16 num_alloc_vport; /* Num vports this driver supports */
490 u32 numa_node_mask;
491 u16 rx_buf_len;
492 u16 num_desc;
493 u8 hw_tc_map;
494 u8 tc_num_last_time;
495 enum hclge_fc_mode fc_mode_last_time;
496
497 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1
498 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2
499 u8 tx_sch_mode;
500 u8 tc_max;
501 u8 pfc_max;
502
503 u8 default_up;
504 u8 dcbx_cap;
505 struct hclge_tm_info tm_info;
506
507 u16 num_msi;
508 u16 num_msi_left;
509 u16 num_msi_used;
510 u16 roce_base_msix_offset;
511 u32 base_msi_vector;
512 u16 *vector_status;
513 int *vector_irq;
514 u16 num_roce_msi; /* Num of roce vectors for this PF */
515 int roce_base_vector;
516
517 u16 pending_udp_bitmap;
518
519 u16 rx_itr_default;
520 u16 tx_itr_default;
521
522 u16 adminq_work_limit; /* Num of admin receive queue desc to process */
523 unsigned long service_timer_period;
524 unsigned long service_timer_previous;
525 struct timer_list service_timer;
526 struct work_struct service_task;
527 struct work_struct rst_service_task;
528 struct work_struct mbx_service_task;
529
530 bool cur_promisc;
531 int num_alloc_vfs; /* Actual number of VFs allocated */
532
533 struct hclge_tqp *htqp;
534 struct hclge_vport *vport;
535
536 struct dentry *hclge_dbgfs;
537
538 struct hnae3_client *nic_client;
539 struct hnae3_client *roce_client;
540
541 #define HCLGE_FLAG_MAIN BIT(0)
542 #define HCLGE_FLAG_DCB_CAPABLE BIT(1)
543 #define HCLGE_FLAG_DCB_ENABLE BIT(2)
544 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3)
545 u32 flag;
546
547 u32 pkt_buf_size; /* Total pf buf size for tx/rx */
548 u32 mps; /* Max packet size */
549
550 enum hclge_mta_dmac_sel_type mta_mac_sel_type;
551 bool enable_mta; /* Multicast filter enable */
552
553 struct hclge_vlan_type_cfg vlan_type_cfg;
554
555 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)];
556 };
557
558 /* VPort level vlan tag configuration for TX direction */
559 struct hclge_tx_vtag_cfg {
560 bool accept_tag1; /* Whether accept tag1 packet from host */
561 bool accept_untag1; /* Whether accept untag1 packet from host */
562 bool accept_tag2;
563 bool accept_untag2;
564 bool insert_tag1_en; /* Whether insert inner vlan tag */
565 bool insert_tag2_en; /* Whether insert outer vlan tag */
566 u16 default_tag1; /* The default inner vlan tag to insert */
567 u16 default_tag2; /* The default outer vlan tag to insert */
568 };
569
570 /* VPort level vlan tag configuration for RX direction */
571 struct hclge_rx_vtag_cfg {
572 bool strip_tag1_en; /* Whether strip inner vlan tag */
573 bool strip_tag2_en; /* Whether strip outer vlan tag */
574 bool vlan1_vlan_prionly;/* Inner VLAN Tag up to descriptor Enable */
575 bool vlan2_vlan_prionly;/* Outer VLAN Tag up to descriptor Enable */
576 };
577
578 struct hclge_rss_tuple_cfg {
579 u8 ipv4_tcp_en;
580 u8 ipv4_udp_en;
581 u8 ipv4_sctp_en;
582 u8 ipv4_fragment_en;
583 u8 ipv6_tcp_en;
584 u8 ipv6_udp_en;
585 u8 ipv6_sctp_en;
586 u8 ipv6_fragment_en;
587 };
588
589 struct hclge_vport {
590 u16 alloc_tqps; /* Allocated Tx/Rx queues */
591
592 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
593 /* User configured lookup table entries */
594 u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];
595 int rss_algo; /* User configured hash algorithm */
596 /* User configured rss tuple sets */
597 struct hclge_rss_tuple_cfg rss_tuple_sets;
598
599 u16 alloc_rss_size;
600
601 u16 qs_offset;
602 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
603 u8 dwrr;
604
605 struct hclge_tx_vtag_cfg txvlan_cfg;
606 struct hclge_rx_vtag_cfg rxvlan_cfg;
607
608 int vport_id;
609 struct hclge_dev *back; /* Back reference to associated dev */
610 struct hnae3_handle nic;
611 struct hnae3_handle roce;
612
613 bool accept_mta_mc; /* whether to accept mta filter multicast */
614 unsigned long mta_shadow[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)];
615 };
616
617 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
618 bool en_mc, bool en_bc, int vport_id);
619
620 int hclge_add_uc_addr_common(struct hclge_vport *vport,
621 const unsigned char *addr);
622 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
623 const unsigned char *addr);
624 int hclge_add_mc_addr_common(struct hclge_vport *vport,
625 const unsigned char *addr);
626 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
627 const unsigned char *addr);
628
629 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
630 u8 func_id,
631 bool enable);
632 int hclge_update_mta_status_common(struct hclge_vport *vport,
633 unsigned long *status,
634 u16 idx,
635 u16 count,
636 bool update_filter);
637
638 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
639 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
640 int vector_id, bool en,
641 struct hnae3_ring_chain_node *ring_chain);
642
hclge_get_queue_id(struct hnae3_queue * queue)643 static inline int hclge_get_queue_id(struct hnae3_queue *queue)
644 {
645 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);
646
647 return tqp->index;
648 }
649
650 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
651 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
652 u16 vlan_id, bool is_kill);
653 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable);
654
655 int hclge_buffer_alloc(struct hclge_dev *hdev);
656 int hclge_rss_init_hw(struct hclge_dev *hdev);
657 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev);
658
659 void hclge_mbx_handler(struct hclge_dev *hdev);
660 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id);
661 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id);
662 int hclge_cfg_flowctrl(struct hclge_dev *hdev);
663 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id);
664 #endif
665
