1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * r2300.c: R2000 and R3000 specific mmu/cache code.
4 *
5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
6 *
7 * with a lot of changes to make this thing work for R3000s
8 * Tx39XX R4k style caches added. HK
9 * Copyright (C) 1998, 1999, 2000 Harald Koerfgen
10 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
11 */
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/sched.h>
15 #include <linux/smp.h>
16 #include <linux/mm.h>
17
18 #include <asm/cacheops.h>
19 #include <asm/page.h>
20 #include <asm/pgtable.h>
21 #include <asm/mmu_context.h>
22 #include <asm/isadep.h>
23 #include <asm/io.h>
24 #include <asm/bootinfo.h>
25 #include <asm/cpu.h>
26
27 /* For R3000 cores with R4000 style caches */
28 static unsigned long icache_size, dcache_size; /* Size in bytes */
29
30 #include <asm/r4kcache.h>
31
32 /* This sequence is required to ensure icache is disabled immediately */
33 #define TX39_STOP_STREAMING() \
34 __asm__ __volatile__( \
35 ".set push\n\t" \
36 ".set noreorder\n\t" \
37 "b 1f\n\t" \
38 "nop\n\t" \
39 "1:\n\t" \
40 ".set pop" \
41 )
42
43 /* TX39H-style cache flush routines. */
tx39h_flush_icache_all(void)44 static void tx39h_flush_icache_all(void)
45 {
46 unsigned long flags, config;
47
48 /* disable icache (set ICE#) */
49 local_irq_save(flags);
50 config = read_c0_conf();
51 write_c0_conf(config & ~TX39_CONF_ICE);
52 TX39_STOP_STREAMING();
53 blast_icache16();
54 write_c0_conf(config);
55 local_irq_restore(flags);
56 }
57
tx39h_dma_cache_wback_inv(unsigned long addr,unsigned long size)58 static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
59 {
60 /* Catch bad driver code */
61 BUG_ON(size == 0);
62
63 iob();
64 blast_inv_dcache_range(addr, addr + size);
65 }
66
67
68 /* TX39H2,TX39H3 */
tx39_blast_dcache_page(unsigned long addr)69 static inline void tx39_blast_dcache_page(unsigned long addr)
70 {
71 if (current_cpu_type() != CPU_TX3912)
72 blast_dcache16_page(addr);
73 }
74
tx39_blast_dcache_page_indexed(unsigned long addr)75 static inline void tx39_blast_dcache_page_indexed(unsigned long addr)
76 {
77 blast_dcache16_page_indexed(addr);
78 }
79
tx39_blast_dcache(void)80 static inline void tx39_blast_dcache(void)
81 {
82 blast_dcache16();
83 }
84
tx39_blast_icache_page(unsigned long addr)85 static inline void tx39_blast_icache_page(unsigned long addr)
86 {
87 unsigned long flags, config;
88 /* disable icache (set ICE#) */
89 local_irq_save(flags);
90 config = read_c0_conf();
91 write_c0_conf(config & ~TX39_CONF_ICE);
92 TX39_STOP_STREAMING();
93 blast_icache16_page(addr);
94 write_c0_conf(config);
95 local_irq_restore(flags);
96 }
97
tx39_blast_icache_page_indexed(unsigned long addr)98 static inline void tx39_blast_icache_page_indexed(unsigned long addr)
99 {
100 unsigned long flags, config;
101 /* disable icache (set ICE#) */
102 local_irq_save(flags);
103 config = read_c0_conf();
104 write_c0_conf(config & ~TX39_CONF_ICE);
105 TX39_STOP_STREAMING();
106 blast_icache16_page_indexed(addr);
107 write_c0_conf(config);
108 local_irq_restore(flags);
109 }
110
tx39_blast_icache(void)111 static inline void tx39_blast_icache(void)
112 {
113 unsigned long flags, config;
114 /* disable icache (set ICE#) */
115 local_irq_save(flags);
116 config = read_c0_conf();
117 write_c0_conf(config & ~TX39_CONF_ICE);
118 TX39_STOP_STREAMING();
119 blast_icache16();
120 write_c0_conf(config);
121 local_irq_restore(flags);
122 }
123
tx39__flush_cache_vmap(void)124 static void tx39__flush_cache_vmap(void)
125 {
126 tx39_blast_dcache();
127 }
128
tx39__flush_cache_vunmap(void)129 static void tx39__flush_cache_vunmap(void)
130 {
131 tx39_blast_dcache();
132 }
133
tx39_flush_cache_all(void)134 static inline void tx39_flush_cache_all(void)
135 {
136 if (!cpu_has_dc_aliases)
137 return;
138
139 tx39_blast_dcache();
140 }
141
tx39___flush_cache_all(void)142 static inline void tx39___flush_cache_all(void)
143 {
144 tx39_blast_dcache();
145 tx39_blast_icache();
146 }
147
tx39_flush_cache_mm(struct mm_struct * mm)148 static void tx39_flush_cache_mm(struct mm_struct *mm)
149 {
150 if (!cpu_has_dc_aliases)
151 return;
152
153 if (cpu_context(smp_processor_id(), mm) != 0)
154 tx39_blast_dcache();
155 }
156
tx39_flush_cache_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)157 static void tx39_flush_cache_range(struct vm_area_struct *vma,
158 unsigned long start, unsigned long end)
159 {
160 if (!cpu_has_dc_aliases)
161 return;
162 if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
163 return;
164
165 tx39_blast_dcache();
166 }
167
tx39_flush_cache_page(struct vm_area_struct * vma,unsigned long page,unsigned long pfn)168 static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
169 {
170 int exec = vma->vm_flags & VM_EXEC;
171 struct mm_struct *mm = vma->vm_mm;
172 pgd_t *pgdp;
173 pud_t *pudp;
174 pmd_t *pmdp;
175 pte_t *ptep;
176
177 /*
178 * If ownes no valid ASID yet, cannot possibly have gotten
179 * this page into the cache.
180 */
181 if (cpu_context(smp_processor_id(), mm) == 0)
182 return;
183
184 page &= PAGE_MASK;
185 pgdp = pgd_offset(mm, page);
186 pudp = pud_offset(pgdp, page);
187 pmdp = pmd_offset(pudp, page);
188 ptep = pte_offset(pmdp, page);
189
190 /*
191 * If the page isn't marked valid, the page cannot possibly be
192 * in the cache.
193 */
194 if (!(pte_val(*ptep) & _PAGE_PRESENT))
195 return;
196
197 /*
198 * Doing flushes for another ASID than the current one is
199 * too difficult since stupid R4k caches do a TLB translation
200 * for every cache flush operation. So we do indexed flushes
201 * in that case, which doesn't overly flush the cache too much.
202 */
203 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
204 if (cpu_has_dc_aliases || exec)
205 tx39_blast_dcache_page(page);
206 if (exec)
207 tx39_blast_icache_page(page);
208
209 return;
210 }
211
212 /*
213 * Do indexed flush, too much work to get the (possible) TLB refills
214 * to work correctly.
215 */
216 if (cpu_has_dc_aliases || exec)
217 tx39_blast_dcache_page_indexed(page);
218 if (exec)
219 tx39_blast_icache_page_indexed(page);
220 }
221
local_tx39_flush_data_cache_page(void * addr)222 static void local_tx39_flush_data_cache_page(void * addr)
223 {
224 tx39_blast_dcache_page((unsigned long)addr);
225 }
226
tx39_flush_data_cache_page(unsigned long addr)227 static void tx39_flush_data_cache_page(unsigned long addr)
228 {
229 tx39_blast_dcache_page(addr);
230 }
231
tx39_flush_icache_range(unsigned long start,unsigned long end)232 static void tx39_flush_icache_range(unsigned long start, unsigned long end)
233 {
234 if (end - start > dcache_size)
235 tx39_blast_dcache();
236 else
237 protected_blast_dcache_range(start, end);
238
239 if (end - start > icache_size)
240 tx39_blast_icache();
241 else {
242 unsigned long flags, config;
243 /* disable icache (set ICE#) */
244 local_irq_save(flags);
245 config = read_c0_conf();
246 write_c0_conf(config & ~TX39_CONF_ICE);
247 TX39_STOP_STREAMING();
248 protected_blast_icache_range(start, end);
249 write_c0_conf(config);
250 local_irq_restore(flags);
251 }
252 }
253
tx39_flush_kernel_vmap_range(unsigned long vaddr,int size)254 static void tx39_flush_kernel_vmap_range(unsigned long vaddr, int size)
255 {
256 BUG();
257 }
258
tx39_dma_cache_wback_inv(unsigned long addr,unsigned long size)259 static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
260 {
261 unsigned long end;
262
263 if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
264 end = addr + size;
265 do {
266 tx39_blast_dcache_page(addr);
267 addr += PAGE_SIZE;
268 } while(addr != end);
269 } else if (size > dcache_size) {
270 tx39_blast_dcache();
271 } else {
272 blast_dcache_range(addr, addr + size);
273 }
274 }
275
tx39_dma_cache_inv(unsigned long addr,unsigned long size)276 static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
277 {
278 unsigned long end;
279
280 if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
281 end = addr + size;
282 do {
283 tx39_blast_dcache_page(addr);
284 addr += PAGE_SIZE;
285 } while(addr != end);
286 } else if (size > dcache_size) {
287 tx39_blast_dcache();
288 } else {
289 blast_inv_dcache_range(addr, addr + size);
290 }
291 }
292
tx39_flush_cache_sigtramp(unsigned long addr)293 static void tx39_flush_cache_sigtramp(unsigned long addr)
294 {
295 unsigned long ic_lsize = current_cpu_data.icache.linesz;
296 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
297 unsigned long config;
298 unsigned long flags;
299
300 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
301
302 /* disable icache (set ICE#) */
303 local_irq_save(flags);
304 config = read_c0_conf();
305 write_c0_conf(config & ~TX39_CONF_ICE);
306 TX39_STOP_STREAMING();
307 protected_flush_icache_line(addr & ~(ic_lsize - 1));
308 write_c0_conf(config);
309 local_irq_restore(flags);
310 }
311
tx39_probe_cache(void)312 static __init void tx39_probe_cache(void)
313 {
314 unsigned long config;
315
316 config = read_c0_conf();
317
318 icache_size = 1 << (10 + ((config & TX39_CONF_ICS_MASK) >>
319 TX39_CONF_ICS_SHIFT));
320 dcache_size = 1 << (10 + ((config & TX39_CONF_DCS_MASK) >>
321 TX39_CONF_DCS_SHIFT));
322
323 current_cpu_data.icache.linesz = 16;
324 switch (current_cpu_type()) {
325 case CPU_TX3912:
326 current_cpu_data.icache.ways = 1;
327 current_cpu_data.dcache.ways = 1;
328 current_cpu_data.dcache.linesz = 4;
329 break;
330
331 case CPU_TX3927:
332 current_cpu_data.icache.ways = 2;
333 current_cpu_data.dcache.ways = 2;
334 current_cpu_data.dcache.linesz = 16;
335 break;
336
337 case CPU_TX3922:
338 default:
339 current_cpu_data.icache.ways = 1;
340 current_cpu_data.dcache.ways = 1;
341 current_cpu_data.dcache.linesz = 16;
342 break;
343 }
344 }
345
tx39_cache_init(void)346 void tx39_cache_init(void)
347 {
348 extern void build_clear_page(void);
349 extern void build_copy_page(void);
350 unsigned long config;
351
352 config = read_c0_conf();
353 config &= ~TX39_CONF_WBON;
354 write_c0_conf(config);
355
356 tx39_probe_cache();
357
358 switch (current_cpu_type()) {
359 case CPU_TX3912:
360 /* TX39/H core (writethru direct-map cache) */
361 __flush_cache_vmap = tx39__flush_cache_vmap;
362 __flush_cache_vunmap = tx39__flush_cache_vunmap;
363 flush_cache_all = tx39h_flush_icache_all;
364 __flush_cache_all = tx39h_flush_icache_all;
365 flush_cache_mm = (void *) tx39h_flush_icache_all;
366 flush_cache_range = (void *) tx39h_flush_icache_all;
367 flush_cache_page = (void *) tx39h_flush_icache_all;
368 flush_icache_range = (void *) tx39h_flush_icache_all;
369 local_flush_icache_range = (void *) tx39h_flush_icache_all;
370
371 flush_cache_sigtramp = (void *) tx39h_flush_icache_all;
372 local_flush_data_cache_page = (void *) tx39h_flush_icache_all;
373 flush_data_cache_page = (void *) tx39h_flush_icache_all;
374
375 _dma_cache_wback_inv = tx39h_dma_cache_wback_inv;
376
377 shm_align_mask = PAGE_SIZE - 1;
378
379 break;
380
381 case CPU_TX3922:
382 case CPU_TX3927:
383 default:
384 /* TX39/H2,H3 core (writeback 2way-set-associative cache) */
385 /* board-dependent init code may set WBON */
386
387 __flush_cache_vmap = tx39__flush_cache_vmap;
388 __flush_cache_vunmap = tx39__flush_cache_vunmap;
389
390 flush_cache_all = tx39_flush_cache_all;
391 __flush_cache_all = tx39___flush_cache_all;
392 flush_cache_mm = tx39_flush_cache_mm;
393 flush_cache_range = tx39_flush_cache_range;
394 flush_cache_page = tx39_flush_cache_page;
395 flush_icache_range = tx39_flush_icache_range;
396 local_flush_icache_range = tx39_flush_icache_range;
397
398 __flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
399
400 flush_cache_sigtramp = tx39_flush_cache_sigtramp;
401 local_flush_data_cache_page = local_tx39_flush_data_cache_page;
402 flush_data_cache_page = tx39_flush_data_cache_page;
403
404 _dma_cache_wback_inv = tx39_dma_cache_wback_inv;
405 _dma_cache_wback = tx39_dma_cache_wback_inv;
406 _dma_cache_inv = tx39_dma_cache_inv;
407
408 shm_align_mask = max_t(unsigned long,
409 (dcache_size / current_cpu_data.dcache.ways) - 1,
410 PAGE_SIZE - 1);
411
412 break;
413 }
414
415 __flush_icache_user_range = flush_icache_range;
416 __local_flush_icache_user_range = local_flush_icache_range;
417
418 current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways;
419 current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways;
420
421 current_cpu_data.icache.sets =
422 current_cpu_data.icache.waysize / current_cpu_data.icache.linesz;
423 current_cpu_data.dcache.sets =
424 current_cpu_data.dcache.waysize / current_cpu_data.dcache.linesz;
425
426 if (current_cpu_data.dcache.waysize > PAGE_SIZE)
427 current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES;
428
429 current_cpu_data.icache.waybit = 0;
430 current_cpu_data.dcache.waybit = 0;
431
432 printk("Primary instruction cache %ldkB, linesize %d bytes\n",
433 icache_size >> 10, current_cpu_data.icache.linesz);
434 printk("Primary data cache %ldkB, linesize %d bytes\n",
435 dcache_size >> 10, current_cpu_data.dcache.linesz);
436
437 build_clear_page();
438 build_copy_page();
439 tx39h_flush_icache_all();
440 }
441
