1 /*
2 * Copyright 2019 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 #include "priv.h"
23 #include <subdev/acr.h>
24
25 static const struct nvkm_falcon_func
26 tu102_sec2_flcn = {
27 .debug = 0x408,
28 .fbif = 0x600,
29 .load_imem = nvkm_falcon_v1_load_imem,
30 .load_dmem = nvkm_falcon_v1_load_dmem,
31 .read_dmem = nvkm_falcon_v1_read_dmem,
32 .emem_addr = 0x01000000,
33 .bind_context = gp102_sec2_flcn_bind_context,
34 .wait_for_halt = nvkm_falcon_v1_wait_for_halt,
35 .clear_interrupt = nvkm_falcon_v1_clear_interrupt,
36 .set_start_addr = nvkm_falcon_v1_set_start_addr,
37 .start = nvkm_falcon_v1_start,
38 .enable = nvkm_falcon_v1_enable,
39 .disable = nvkm_falcon_v1_disable,
40 .cmdq = { 0xc00, 0xc04, 8 },
41 .msgq = { 0xc80, 0xc84, 8 },
42 };
43
44 static const struct nvkm_sec2_func
45 tu102_sec2 = {
46 .flcn = &tu102_sec2_flcn,
47 .unit_acr = 0x07,
48 .intr = gp102_sec2_intr,
49 .initmsg = gp102_sec2_initmsg,
50 };
51
52 MODULE_FIRMWARE("nvidia/tu102/sec2/desc.bin");
53 MODULE_FIRMWARE("nvidia/tu102/sec2/image.bin");
54 MODULE_FIRMWARE("nvidia/tu102/sec2/sig.bin");
55 MODULE_FIRMWARE("nvidia/tu104/sec2/desc.bin");
56 MODULE_FIRMWARE("nvidia/tu104/sec2/image.bin");
57 MODULE_FIRMWARE("nvidia/tu104/sec2/sig.bin");
58 MODULE_FIRMWARE("nvidia/tu106/sec2/desc.bin");
59 MODULE_FIRMWARE("nvidia/tu106/sec2/image.bin");
60 MODULE_FIRMWARE("nvidia/tu106/sec2/sig.bin");
61 MODULE_FIRMWARE("nvidia/tu116/sec2/desc.bin");
62 MODULE_FIRMWARE("nvidia/tu116/sec2/image.bin");
63 MODULE_FIRMWARE("nvidia/tu116/sec2/sig.bin");
64 MODULE_FIRMWARE("nvidia/tu117/sec2/desc.bin");
65 MODULE_FIRMWARE("nvidia/tu117/sec2/image.bin");
66 MODULE_FIRMWARE("nvidia/tu117/sec2/sig.bin");
67
68 static const struct nvkm_sec2_fwif
69 tu102_sec2_fwif[] = {
70 { 0, gp102_sec2_load, &tu102_sec2, &gp102_sec2_acr_1 },
71 { -1, gp102_sec2_nofw, &tu102_sec2 }
72 };
73
74 int
tu102_sec2_new(struct nvkm_device * device,int index,struct nvkm_sec2 ** psec2)75 tu102_sec2_new(struct nvkm_device *device, int index, struct nvkm_sec2 **psec2)
76 {
77 /* TOP info wasn't updated on Turing to reflect the PRI
78 * address change for some reason. We override it here.
79 */
80 return nvkm_sec2_new_(tu102_sec2_fwif, device, index, 0x840000, psec2);
81 }
82
