1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2005, 2006 IBM Corporation
4 * Copyright (C) 2014, 2015 Intel Corporation
5 *
6 * Authors:
7 * Leendert van Doorn <leendert@watson.ibm.com>
8 * Kylene Hall <kjhall@us.ibm.com>
9 *
10 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
11 *
12 * Device driver for TCG/TCPA TPM (trusted platform module).
13 * Specifications at www.trustedcomputinggroup.org
14 *
15 * This device driver implements the TPM interface as defined in
16 * the TCG TPM Interface Spec version 1.2, revision 1.0.
17 */
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/pnp.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/wait.h>
25 #include <linux/acpi.h>
26 #include <linux/freezer.h>
27 #include "tpm.h"
28 #include "tpm_tis_core.h"
29
30 static void tpm_tis_clkrun_enable(struct tpm_chip *chip, bool value);
31
wait_for_tpm_stat_cond(struct tpm_chip * chip,u8 mask,bool check_cancel,bool * canceled)32 static bool wait_for_tpm_stat_cond(struct tpm_chip *chip, u8 mask,
33 bool check_cancel, bool *canceled)
34 {
35 u8 status = chip->ops->status(chip);
36
37 *canceled = false;
38 if ((status & mask) == mask)
39 return true;
40 if (check_cancel && chip->ops->req_canceled(chip, status)) {
41 *canceled = true;
42 return true;
43 }
44 return false;
45 }
46
wait_for_tpm_stat(struct tpm_chip * chip,u8 mask,unsigned long timeout,wait_queue_head_t * queue,bool check_cancel)47 static int wait_for_tpm_stat(struct tpm_chip *chip, u8 mask,
48 unsigned long timeout, wait_queue_head_t *queue,
49 bool check_cancel)
50 {
51 unsigned long stop;
52 long rc;
53 u8 status;
54 bool canceled = false;
55
56 /* check current status */
57 status = chip->ops->status(chip);
58 if ((status & mask) == mask)
59 return 0;
60
61 stop = jiffies + timeout;
62
63 if (chip->flags & TPM_CHIP_FLAG_IRQ) {
64 again:
65 timeout = stop - jiffies;
66 if ((long)timeout <= 0)
67 return -ETIME;
68 rc = wait_event_interruptible_timeout(*queue,
69 wait_for_tpm_stat_cond(chip, mask, check_cancel,
70 &canceled),
71 timeout);
72 if (rc > 0) {
73 if (canceled)
74 return -ECANCELED;
75 return 0;
76 }
77 if (rc == -ERESTARTSYS && freezing(current)) {
78 clear_thread_flag(TIF_SIGPENDING);
79 goto again;
80 }
81 } else {
82 do {
83 usleep_range(TPM_TIMEOUT_USECS_MIN,
84 TPM_TIMEOUT_USECS_MAX);
85 status = chip->ops->status(chip);
86 if ((status & mask) == mask)
87 return 0;
88 } while (time_before(jiffies, stop));
89 }
90 return -ETIME;
91 }
92
93 /* Before we attempt to access the TPM we must see that the valid bit is set.
94 * The specification says that this bit is 0 at reset and remains 0 until the
95 * 'TPM has gone through its self test and initialization and has established
96 * correct values in the other bits.'
97 */
wait_startup(struct tpm_chip * chip,int l)98 static int wait_startup(struct tpm_chip *chip, int l)
99 {
100 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
101 unsigned long stop = jiffies + chip->timeout_a;
102
103 do {
104 int rc;
105 u8 access;
106
107 rc = tpm_tis_read8(priv, TPM_ACCESS(l), &access);
108 if (rc < 0)
109 return rc;
110
111 if (access & TPM_ACCESS_VALID)
112 return 0;
113 tpm_msleep(TPM_TIMEOUT);
114 } while (time_before(jiffies, stop));
115 return -1;
116 }
117
check_locality(struct tpm_chip * chip,int l)118 static bool check_locality(struct tpm_chip *chip, int l)
119 {
120 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
121 int rc;
122 u8 access;
123
124 rc = tpm_tis_read8(priv, TPM_ACCESS(l), &access);
125 if (rc < 0)
126 return false;
127
128 if ((access & (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
129 (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) {
130 priv->locality = l;
131 return true;
132 }
133
134 return false;
135 }
136
locality_inactive(struct tpm_chip * chip,int l)137 static bool locality_inactive(struct tpm_chip *chip, int l)
138 {
139 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
140 int rc;
141 u8 access;
142
143 rc = tpm_tis_read8(priv, TPM_ACCESS(l), &access);
144 if (rc < 0)
145 return false;
146
147 if ((access & (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY))
148 == TPM_ACCESS_VALID)
149 return true;
150
151 return false;
152 }
153
release_locality(struct tpm_chip * chip,int l)154 static int release_locality(struct tpm_chip *chip, int l)
155 {
156 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
157 unsigned long stop, timeout;
158 long rc;
159
160 tpm_tis_write8(priv, TPM_ACCESS(l), TPM_ACCESS_ACTIVE_LOCALITY);
161
162 stop = jiffies + chip->timeout_a;
163
164 if (chip->flags & TPM_CHIP_FLAG_IRQ) {
165 again:
166 timeout = stop - jiffies;
167 if ((long)timeout <= 0)
168 return -1;
169
170 rc = wait_event_interruptible_timeout(priv->int_queue,
171 (locality_inactive(chip, l)),
172 timeout);
173
174 if (rc > 0)
175 return 0;
176
177 if (rc == -ERESTARTSYS && freezing(current)) {
178 clear_thread_flag(TIF_SIGPENDING);
179 goto again;
180 }
181 } else {
182 do {
183 if (locality_inactive(chip, l))
184 return 0;
185 tpm_msleep(TPM_TIMEOUT);
186 } while (time_before(jiffies, stop));
187 }
188 return -1;
189 }
190
request_locality(struct tpm_chip * chip,int l)191 static int request_locality(struct tpm_chip *chip, int l)
192 {
193 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
194 unsigned long stop, timeout;
195 long rc;
196
197 if (check_locality(chip, l))
198 return l;
199
200 rc = tpm_tis_write8(priv, TPM_ACCESS(l), TPM_ACCESS_REQUEST_USE);
201 if (rc < 0)
202 return rc;
203
204 stop = jiffies + chip->timeout_a;
205
206 if (chip->flags & TPM_CHIP_FLAG_IRQ) {
207 again:
208 timeout = stop - jiffies;
209 if ((long)timeout <= 0)
210 return -1;
211 rc = wait_event_interruptible_timeout(priv->int_queue,
212 (check_locality
213 (chip, l)),
214 timeout);
215 if (rc > 0)
216 return l;
217 if (rc == -ERESTARTSYS && freezing(current)) {
218 clear_thread_flag(TIF_SIGPENDING);
219 goto again;
220 }
221 } else {
222 /* wait for burstcount */
223 do {
224 if (check_locality(chip, l))
225 return l;
226 tpm_msleep(TPM_TIMEOUT);
227 } while (time_before(jiffies, stop));
228 }
229 return -1;
230 }
231
tpm_tis_status(struct tpm_chip * chip)232 static u8 tpm_tis_status(struct tpm_chip *chip)
233 {
234 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
235 int rc;
236 u8 status;
237
238 rc = tpm_tis_read8(priv, TPM_STS(priv->locality), &status);
239 if (rc < 0)
240 return 0;
241
242 return status;
243 }
244
tpm_tis_ready(struct tpm_chip * chip)245 static void tpm_tis_ready(struct tpm_chip *chip)
246 {
247 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
248
249 /* this causes the current command to be aborted */
250 tpm_tis_write8(priv, TPM_STS(priv->locality), TPM_STS_COMMAND_READY);
251 }
252
get_burstcount(struct tpm_chip * chip)253 static int get_burstcount(struct tpm_chip *chip)
254 {
255 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
256 unsigned long stop;
257 int burstcnt, rc;
258 u32 value;
259
260 /* wait for burstcount */
261 if (chip->flags & TPM_CHIP_FLAG_TPM2)
262 stop = jiffies + chip->timeout_a;
263 else
264 stop = jiffies + chip->timeout_d;
265 do {
266 rc = tpm_tis_read32(priv, TPM_STS(priv->locality), &value);
267 if (rc < 0)
268 return rc;
269
270 burstcnt = (value >> 8) & 0xFFFF;
271 if (burstcnt)
272 return burstcnt;
273 usleep_range(TPM_TIMEOUT_USECS_MIN, TPM_TIMEOUT_USECS_MAX);
274 } while (time_before(jiffies, stop));
275 return -EBUSY;
276 }
277
recv_data(struct tpm_chip * chip,u8 * buf,size_t count)278 static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
279 {
280 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
281 int size = 0, burstcnt, rc;
282
283 while (size < count) {
284 rc = wait_for_tpm_stat(chip,
285 TPM_STS_DATA_AVAIL | TPM_STS_VALID,
286 chip->timeout_c,
287 &priv->read_queue, true);
288 if (rc < 0)
289 return rc;
290 burstcnt = get_burstcount(chip);
291 if (burstcnt < 0) {
292 dev_err(&chip->dev, "Unable to read burstcount\n");
293 return burstcnt;
294 }
295 burstcnt = min_t(int, burstcnt, count - size);
296
297 rc = tpm_tis_read_bytes(priv, TPM_DATA_FIFO(priv->locality),
298 burstcnt, buf + size);
299 if (rc < 0)
300 return rc;
301
302 size += burstcnt;
303 }
304 return size;
305 }
306
tpm_tis_recv(struct tpm_chip * chip,u8 * buf,size_t count)307 static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
308 {
309 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
310 int size = 0;
311 int status;
312 u32 expected;
313
314 if (count < TPM_HEADER_SIZE) {
315 size = -EIO;
316 goto out;
317 }
318
319 size = recv_data(chip, buf, TPM_HEADER_SIZE);
320 /* read first 10 bytes, including tag, paramsize, and result */
321 if (size < TPM_HEADER_SIZE) {
322 dev_err(&chip->dev, "Unable to read header\n");
323 goto out;
324 }
325
326 expected = be32_to_cpu(*(__be32 *) (buf + 2));
327 if (expected > count || expected < TPM_HEADER_SIZE) {
328 size = -EIO;
329 goto out;
330 }
331
332 size += recv_data(chip, &buf[TPM_HEADER_SIZE],
333 expected - TPM_HEADER_SIZE);
334 if (size < expected) {
335 dev_err(&chip->dev, "Unable to read remainder of result\n");
336 size = -ETIME;
337 goto out;
338 }
339
340 if (wait_for_tpm_stat(chip, TPM_STS_VALID, chip->timeout_c,
341 &priv->int_queue, false) < 0) {
342 size = -ETIME;
343 goto out;
344 }
345 status = tpm_tis_status(chip);
346 if (status & TPM_STS_DATA_AVAIL) { /* retry? */
347 dev_err(&chip->dev, "Error left over data\n");
348 size = -EIO;
349 goto out;
350 }
351
352 out:
353 tpm_tis_ready(chip);
354 return size;
355 }
356
357 /*
358 * If interrupts are used (signaled by an irq set in the vendor structure)
359 * tpm.c can skip polling for the data to be available as the interrupt is
360 * waited for here
361 */
tpm_tis_send_data(struct tpm_chip * chip,const u8 * buf,size_t len)362 static int tpm_tis_send_data(struct tpm_chip *chip, const u8 *buf, size_t len)
363 {
364 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
365 int rc, status, burstcnt;
366 size_t count = 0;
367 bool itpm = priv->flags & TPM_TIS_ITPM_WORKAROUND;
368
369 status = tpm_tis_status(chip);
370 if ((status & TPM_STS_COMMAND_READY) == 0) {
371 tpm_tis_ready(chip);
372 if (wait_for_tpm_stat
373 (chip, TPM_STS_COMMAND_READY, chip->timeout_b,
374 &priv->int_queue, false) < 0) {
375 rc = -ETIME;
376 goto out_err;
377 }
378 }
379
380 while (count < len - 1) {
381 burstcnt = get_burstcount(chip);
382 if (burstcnt < 0) {
383 dev_err(&chip->dev, "Unable to read burstcount\n");
384 rc = burstcnt;
385 goto out_err;
386 }
387 burstcnt = min_t(int, burstcnt, len - count - 1);
388 rc = tpm_tis_write_bytes(priv, TPM_DATA_FIFO(priv->locality),
389 burstcnt, buf + count);
390 if (rc < 0)
391 goto out_err;
392
393 count += burstcnt;
394
395 if (wait_for_tpm_stat(chip, TPM_STS_VALID, chip->timeout_c,
396 &priv->int_queue, false) < 0) {
397 rc = -ETIME;
398 goto out_err;
399 }
400 status = tpm_tis_status(chip);
401 if (!itpm && (status & TPM_STS_DATA_EXPECT) == 0) {
402 rc = -EIO;
403 goto out_err;
404 }
405 }
406
407 /* write last byte */
408 rc = tpm_tis_write8(priv, TPM_DATA_FIFO(priv->locality), buf[count]);
409 if (rc < 0)
410 goto out_err;
411
412 if (wait_for_tpm_stat(chip, TPM_STS_VALID, chip->timeout_c,
413 &priv->int_queue, false) < 0) {
414 rc = -ETIME;
415 goto out_err;
416 }
417 status = tpm_tis_status(chip);
418 if (!itpm && (status & TPM_STS_DATA_EXPECT) != 0) {
419 rc = -EIO;
420 goto out_err;
421 }
422
423 return 0;
424
425 out_err:
426 tpm_tis_ready(chip);
427 return rc;
428 }
429
disable_interrupts(struct tpm_chip * chip)430 static void disable_interrupts(struct tpm_chip *chip)
431 {
432 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
433 u32 intmask;
434 int rc;
435
436 rc = tpm_tis_read32(priv, TPM_INT_ENABLE(priv->locality), &intmask);
437 if (rc < 0)
438 intmask = 0;
439
440 intmask &= ~TPM_GLOBAL_INT_ENABLE;
441 rc = tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality), intmask);
442
443 devm_free_irq(chip->dev.parent, priv->irq, chip);
444 priv->irq = 0;
445 chip->flags &= ~TPM_CHIP_FLAG_IRQ;
446 }
447
448 /*
449 * If interrupts are used (signaled by an irq set in the vendor structure)
450 * tpm.c can skip polling for the data to be available as the interrupt is
451 * waited for here
452 */
tpm_tis_send_main(struct tpm_chip * chip,const u8 * buf,size_t len)453 static int tpm_tis_send_main(struct tpm_chip *chip, const u8 *buf, size_t len)
454 {
455 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
456 int rc;
457 u32 ordinal;
458 unsigned long dur;
459
460 rc = tpm_tis_send_data(chip, buf, len);
461 if (rc < 0)
462 return rc;
463
464 /* go and do it */
465 rc = tpm_tis_write8(priv, TPM_STS(priv->locality), TPM_STS_GO);
466 if (rc < 0)
467 goto out_err;
468
469 if (chip->flags & TPM_CHIP_FLAG_IRQ) {
470 ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
471
472 dur = tpm_calc_ordinal_duration(chip, ordinal);
473 if (wait_for_tpm_stat
474 (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID, dur,
475 &priv->read_queue, false) < 0) {
476 rc = -ETIME;
477 goto out_err;
478 }
479 }
480 return 0;
481 out_err:
482 tpm_tis_ready(chip);
483 return rc;
484 }
485
tpm_tis_send(struct tpm_chip * chip,u8 * buf,size_t len)486 static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len)
487 {
488 int rc, irq;
489 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
490
491 if (!(chip->flags & TPM_CHIP_FLAG_IRQ) || priv->irq_tested)
492 return tpm_tis_send_main(chip, buf, len);
493
494 /* Verify receipt of the expected IRQ */
495 irq = priv->irq;
496 priv->irq = 0;
497 chip->flags &= ~TPM_CHIP_FLAG_IRQ;
498 rc = tpm_tis_send_main(chip, buf, len);
499 priv->irq = irq;
500 chip->flags |= TPM_CHIP_FLAG_IRQ;
501 if (!priv->irq_tested)
502 tpm_msleep(1);
503 if (!priv->irq_tested)
504 disable_interrupts(chip);
505 priv->irq_tested = true;
506 return rc;
507 }
508
509 struct tis_vendor_timeout_override {
510 u32 did_vid;
511 unsigned long timeout_us[4];
512 };
513
514 static const struct tis_vendor_timeout_override vendor_timeout_overrides[] = {
515 /* Atmel 3204 */
516 { 0x32041114, { (TIS_SHORT_TIMEOUT*1000), (TIS_LONG_TIMEOUT*1000),
517 (TIS_SHORT_TIMEOUT*1000), (TIS_SHORT_TIMEOUT*1000) } },
518 };
519
tpm_tis_update_timeouts(struct tpm_chip * chip,unsigned long * timeout_cap)520 static void tpm_tis_update_timeouts(struct tpm_chip *chip,
521 unsigned long *timeout_cap)
522 {
523 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
524 int i, rc;
525 u32 did_vid;
526
527 chip->timeout_adjusted = false;
528
529 if (chip->ops->clk_enable != NULL)
530 chip->ops->clk_enable(chip, true);
531
532 rc = tpm_tis_read32(priv, TPM_DID_VID(0), &did_vid);
533 if (rc < 0) {
534 dev_warn(&chip->dev, "%s: failed to read did_vid: %d\n",
535 __func__, rc);
536 goto out;
537 }
538
539 for (i = 0; i != ARRAY_SIZE(vendor_timeout_overrides); i++) {
540 if (vendor_timeout_overrides[i].did_vid != did_vid)
541 continue;
542 memcpy(timeout_cap, vendor_timeout_overrides[i].timeout_us,
543 sizeof(vendor_timeout_overrides[i].timeout_us));
544 chip->timeout_adjusted = true;
545 }
546
547 out:
548 if (chip->ops->clk_enable != NULL)
549 chip->ops->clk_enable(chip, false);
550
551 return;
552 }
553
554 /*
555 * Early probing for iTPM with STS_DATA_EXPECT flaw.
556 * Try sending command without itpm flag set and if that
557 * fails, repeat with itpm flag set.
558 */
probe_itpm(struct tpm_chip * chip)559 static int probe_itpm(struct tpm_chip *chip)
560 {
561 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
562 int rc = 0;
563 static const u8 cmd_getticks[] = {
564 0x00, 0xc1, 0x00, 0x00, 0x00, 0x0a,
565 0x00, 0x00, 0x00, 0xf1
566 };
567 size_t len = sizeof(cmd_getticks);
568 u16 vendor;
569
570 if (priv->flags & TPM_TIS_ITPM_WORKAROUND)
571 return 0;
572
573 rc = tpm_tis_read16(priv, TPM_DID_VID(0), &vendor);
574 if (rc < 0)
575 return rc;
576
577 /* probe only iTPMS */
578 if (vendor != TPM_VID_INTEL)
579 return 0;
580
581 if (request_locality(chip, 0) != 0)
582 return -EBUSY;
583
584 rc = tpm_tis_send_data(chip, cmd_getticks, len);
585 if (rc == 0)
586 goto out;
587
588 tpm_tis_ready(chip);
589
590 priv->flags |= TPM_TIS_ITPM_WORKAROUND;
591
592 rc = tpm_tis_send_data(chip, cmd_getticks, len);
593 if (rc == 0)
594 dev_info(&chip->dev, "Detected an iTPM.\n");
595 else {
596 priv->flags &= ~TPM_TIS_ITPM_WORKAROUND;
597 rc = -EFAULT;
598 }
599
600 out:
601 tpm_tis_ready(chip);
602 release_locality(chip, priv->locality);
603
604 return rc;
605 }
606
tpm_tis_req_canceled(struct tpm_chip * chip,u8 status)607 static bool tpm_tis_req_canceled(struct tpm_chip *chip, u8 status)
608 {
609 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
610
611 switch (priv->manufacturer_id) {
612 case TPM_VID_WINBOND:
613 return ((status == TPM_STS_VALID) ||
614 (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY)));
615 case TPM_VID_STM:
616 return (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY));
617 default:
618 return (status == TPM_STS_COMMAND_READY);
619 }
620 }
621
tis_int_handler(int dummy,void * dev_id)622 static irqreturn_t tis_int_handler(int dummy, void *dev_id)
623 {
624 struct tpm_chip *chip = dev_id;
625 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
626 u32 interrupt;
627 int i, rc;
628
629 rc = tpm_tis_read32(priv, TPM_INT_STATUS(priv->locality), &interrupt);
630 if (rc < 0)
631 return IRQ_NONE;
632
633 if (interrupt == 0)
634 return IRQ_NONE;
635
636 priv->irq_tested = true;
637 if (interrupt & TPM_INTF_DATA_AVAIL_INT)
638 wake_up_interruptible(&priv->read_queue);
639 if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT)
640 for (i = 0; i < 5; i++)
641 if (check_locality(chip, i))
642 break;
643 if (interrupt &
644 (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT |
645 TPM_INTF_CMD_READY_INT))
646 wake_up_interruptible(&priv->int_queue);
647
648 /* Clear interrupts handled with TPM_EOI */
649 rc = tpm_tis_write32(priv, TPM_INT_STATUS(priv->locality), interrupt);
650 if (rc < 0)
651 return IRQ_NONE;
652
653 tpm_tis_read32(priv, TPM_INT_STATUS(priv->locality), &interrupt);
654 return IRQ_HANDLED;
655 }
656
tpm_tis_gen_interrupt(struct tpm_chip * chip)657 static int tpm_tis_gen_interrupt(struct tpm_chip *chip)
658 {
659 const char *desc = "attempting to generate an interrupt";
660 u32 cap2;
661 cap_t cap;
662
663 if (chip->flags & TPM_CHIP_FLAG_TPM2)
664 return tpm2_get_tpm_pt(chip, 0x100, &cap2, desc);
665 else
666 return tpm1_getcap(chip, TPM_CAP_PROP_TIS_TIMEOUT, &cap, desc,
667 0);
668 }
669
670 /* Register the IRQ and issue a command that will cause an interrupt. If an
671 * irq is seen then leave the chip setup for IRQ operation, otherwise reverse
672 * everything and leave in polling mode. Returns 0 on success.
673 */
tpm_tis_probe_irq_single(struct tpm_chip * chip,u32 intmask,int flags,int irq)674 static int tpm_tis_probe_irq_single(struct tpm_chip *chip, u32 intmask,
675 int flags, int irq)
676 {
677 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
678 u8 original_int_vec;
679 int rc;
680 u32 int_status;
681
682 if (devm_request_irq(chip->dev.parent, irq, tis_int_handler, flags,
683 dev_name(&chip->dev), chip) != 0) {
684 dev_info(&chip->dev, "Unable to request irq: %d for probe\n",
685 irq);
686 return -1;
687 }
688 priv->irq = irq;
689
690 rc = tpm_tis_read8(priv, TPM_INT_VECTOR(priv->locality),
691 &original_int_vec);
692 if (rc < 0)
693 return rc;
694
695 rc = tpm_tis_write8(priv, TPM_INT_VECTOR(priv->locality), irq);
696 if (rc < 0)
697 return rc;
698
699 rc = tpm_tis_read32(priv, TPM_INT_STATUS(priv->locality), &int_status);
700 if (rc < 0)
701 return rc;
702
703 /* Clear all existing */
704 rc = tpm_tis_write32(priv, TPM_INT_STATUS(priv->locality), int_status);
705 if (rc < 0)
706 return rc;
707
708 /* Turn on */
709 rc = tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality),
710 intmask | TPM_GLOBAL_INT_ENABLE);
711 if (rc < 0)
712 return rc;
713
714 priv->irq_tested = false;
715
716 /* Generate an interrupt by having the core call through to
717 * tpm_tis_send
718 */
719 rc = tpm_tis_gen_interrupt(chip);
720 if (rc < 0)
721 return rc;
722
723 /* tpm_tis_send will either confirm the interrupt is working or it
724 * will call disable_irq which undoes all of the above.
725 */
726 if (!(chip->flags & TPM_CHIP_FLAG_IRQ)) {
727 rc = tpm_tis_write8(priv, original_int_vec,
728 TPM_INT_VECTOR(priv->locality));
729 if (rc < 0)
730 return rc;
731
732 return 1;
733 }
734
735 return 0;
736 }
737
738 /* Try to find the IRQ the TPM is using. This is for legacy x86 systems that
739 * do not have ACPI/etc. We typically expect the interrupt to be declared if
740 * present.
741 */
tpm_tis_probe_irq(struct tpm_chip * chip,u32 intmask)742 static void tpm_tis_probe_irq(struct tpm_chip *chip, u32 intmask)
743 {
744 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
745 u8 original_int_vec;
746 int i, rc;
747
748 rc = tpm_tis_read8(priv, TPM_INT_VECTOR(priv->locality),
749 &original_int_vec);
750 if (rc < 0)
751 return;
752
753 if (!original_int_vec) {
754 if (IS_ENABLED(CONFIG_X86))
755 for (i = 3; i <= 15; i++)
756 if (!tpm_tis_probe_irq_single(chip, intmask, 0,
757 i))
758 return;
759 } else if (!tpm_tis_probe_irq_single(chip, intmask, 0,
760 original_int_vec))
761 return;
762 }
763
tpm_tis_remove(struct tpm_chip * chip)764 void tpm_tis_remove(struct tpm_chip *chip)
765 {
766 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
767 u32 reg = TPM_INT_ENABLE(priv->locality);
768 u32 interrupt;
769 int rc;
770
771 tpm_tis_clkrun_enable(chip, true);
772
773 rc = tpm_tis_read32(priv, reg, &interrupt);
774 if (rc < 0)
775 interrupt = 0;
776
777 tpm_tis_write32(priv, reg, ~TPM_GLOBAL_INT_ENABLE & interrupt);
778
779 tpm_tis_clkrun_enable(chip, false);
780
781 if (priv->ilb_base_addr)
782 iounmap(priv->ilb_base_addr);
783 }
784 EXPORT_SYMBOL_GPL(tpm_tis_remove);
785
786 /**
787 * tpm_tis_clkrun_enable() - Keep clkrun protocol disabled for entire duration
788 * of a single TPM command
789 * @chip: TPM chip to use
790 * @value: 1 - Disable CLKRUN protocol, so that clocks are free running
791 * 0 - Enable CLKRUN protocol
792 * Call this function directly in tpm_tis_remove() in error or driver removal
793 * path, since the chip->ops is set to NULL in tpm_chip_unregister().
794 */
tpm_tis_clkrun_enable(struct tpm_chip * chip,bool value)795 static void tpm_tis_clkrun_enable(struct tpm_chip *chip, bool value)
796 {
797 struct tpm_tis_data *data = dev_get_drvdata(&chip->dev);
798 u32 clkrun_val;
799
800 if (!IS_ENABLED(CONFIG_X86) || !is_bsw() ||
801 !data->ilb_base_addr)
802 return;
803
804 if (value) {
805 data->clkrun_enabled++;
806 if (data->clkrun_enabled > 1)
807 return;
808 clkrun_val = ioread32(data->ilb_base_addr + LPC_CNTRL_OFFSET);
809
810 /* Disable LPC CLKRUN# */
811 clkrun_val &= ~LPC_CLKRUN_EN;
812 iowrite32(clkrun_val, data->ilb_base_addr + LPC_CNTRL_OFFSET);
813
814 /*
815 * Write any random value on port 0x80 which is on LPC, to make
816 * sure LPC clock is running before sending any TPM command.
817 */
818 outb(0xCC, 0x80);
819 } else {
820 data->clkrun_enabled--;
821 if (data->clkrun_enabled)
822 return;
823
824 clkrun_val = ioread32(data->ilb_base_addr + LPC_CNTRL_OFFSET);
825
826 /* Enable LPC CLKRUN# */
827 clkrun_val |= LPC_CLKRUN_EN;
828 iowrite32(clkrun_val, data->ilb_base_addr + LPC_CNTRL_OFFSET);
829
830 /*
831 * Write any random value on port 0x80 which is on LPC, to make
832 * sure LPC clock is running before sending any TPM command.
833 */
834 outb(0xCC, 0x80);
835 }
836 }
837
838 static const struct tpm_class_ops tpm_tis = {
839 .flags = TPM_OPS_AUTO_STARTUP,
840 .status = tpm_tis_status,
841 .recv = tpm_tis_recv,
842 .send = tpm_tis_send,
843 .cancel = tpm_tis_ready,
844 .update_timeouts = tpm_tis_update_timeouts,
845 .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
846 .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
847 .req_canceled = tpm_tis_req_canceled,
848 .request_locality = request_locality,
849 .relinquish_locality = release_locality,
850 .clk_enable = tpm_tis_clkrun_enable,
851 };
852
tpm_tis_core_init(struct device * dev,struct tpm_tis_data * priv,int irq,const struct tpm_tis_phy_ops * phy_ops,acpi_handle acpi_dev_handle)853 int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,
854 const struct tpm_tis_phy_ops *phy_ops,
855 acpi_handle acpi_dev_handle)
856 {
857 u32 vendor;
858 u32 intfcaps;
859 u32 intmask;
860 u32 clkrun_val;
861 u8 rid;
862 int rc, probe;
863 struct tpm_chip *chip;
864
865 chip = tpmm_chip_alloc(dev, &tpm_tis);
866 if (IS_ERR(chip))
867 return PTR_ERR(chip);
868
869 #ifdef CONFIG_ACPI
870 chip->acpi_dev_handle = acpi_dev_handle;
871 #endif
872
873 chip->hwrng.quality = priv->rng_quality;
874
875 /* Maximum timeouts */
876 chip->timeout_a = msecs_to_jiffies(TIS_TIMEOUT_A_MAX);
877 chip->timeout_b = msecs_to_jiffies(TIS_TIMEOUT_B_MAX);
878 chip->timeout_c = msecs_to_jiffies(TIS_TIMEOUT_C_MAX);
879 chip->timeout_d = msecs_to_jiffies(TIS_TIMEOUT_D_MAX);
880 priv->phy_ops = phy_ops;
881 dev_set_drvdata(&chip->dev, priv);
882
883 if (is_bsw()) {
884 priv->ilb_base_addr = ioremap(INTEL_LEGACY_BLK_BASE_ADDR,
885 ILB_REMAP_SIZE);
886 if (!priv->ilb_base_addr)
887 return -ENOMEM;
888
889 clkrun_val = ioread32(priv->ilb_base_addr + LPC_CNTRL_OFFSET);
890 /* Check if CLKRUN# is already not enabled in the LPC bus */
891 if (!(clkrun_val & LPC_CLKRUN_EN)) {
892 iounmap(priv->ilb_base_addr);
893 priv->ilb_base_addr = NULL;
894 }
895 }
896
897 if (chip->ops->clk_enable != NULL)
898 chip->ops->clk_enable(chip, true);
899
900 if (wait_startup(chip, 0) != 0) {
901 rc = -ENODEV;
902 goto out_err;
903 }
904
905 /* Take control of the TPM's interrupt hardware and shut it off */
906 rc = tpm_tis_read32(priv, TPM_INT_ENABLE(priv->locality), &intmask);
907 if (rc < 0)
908 goto out_err;
909
910 intmask |= TPM_INTF_CMD_READY_INT | TPM_INTF_LOCALITY_CHANGE_INT |
911 TPM_INTF_DATA_AVAIL_INT | TPM_INTF_STS_VALID_INT;
912 intmask &= ~TPM_GLOBAL_INT_ENABLE;
913 tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality), intmask);
914
915 rc = tpm_chip_start(chip);
916 if (rc)
917 goto out_err;
918 rc = tpm2_probe(chip);
919 tpm_chip_stop(chip);
920 if (rc)
921 goto out_err;
922
923 rc = tpm_tis_read32(priv, TPM_DID_VID(0), &vendor);
924 if (rc < 0)
925 goto out_err;
926
927 priv->manufacturer_id = vendor;
928
929 rc = tpm_tis_read8(priv, TPM_RID(0), &rid);
930 if (rc < 0)
931 goto out_err;
932
933 dev_info(dev, "%s TPM (device-id 0x%X, rev-id %d)\n",
934 (chip->flags & TPM_CHIP_FLAG_TPM2) ? "2.0" : "1.2",
935 vendor >> 16, rid);
936
937 probe = probe_itpm(chip);
938 if (probe < 0) {
939 rc = -ENODEV;
940 goto out_err;
941 }
942
943 /* Figure out the capabilities */
944 rc = tpm_tis_read32(priv, TPM_INTF_CAPS(priv->locality), &intfcaps);
945 if (rc < 0)
946 goto out_err;
947
948 dev_dbg(dev, "TPM interface capabilities (0x%x):\n",
949 intfcaps);
950 if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
951 dev_dbg(dev, "\tBurst Count Static\n");
952 if (intfcaps & TPM_INTF_CMD_READY_INT)
953 dev_dbg(dev, "\tCommand Ready Int Support\n");
954 if (intfcaps & TPM_INTF_INT_EDGE_FALLING)
955 dev_dbg(dev, "\tInterrupt Edge Falling\n");
956 if (intfcaps & TPM_INTF_INT_EDGE_RISING)
957 dev_dbg(dev, "\tInterrupt Edge Rising\n");
958 if (intfcaps & TPM_INTF_INT_LEVEL_LOW)
959 dev_dbg(dev, "\tInterrupt Level Low\n");
960 if (intfcaps & TPM_INTF_INT_LEVEL_HIGH)
961 dev_dbg(dev, "\tInterrupt Level High\n");
962 if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT)
963 dev_dbg(dev, "\tLocality Change Int Support\n");
964 if (intfcaps & TPM_INTF_STS_VALID_INT)
965 dev_dbg(dev, "\tSts Valid Int Support\n");
966 if (intfcaps & TPM_INTF_DATA_AVAIL_INT)
967 dev_dbg(dev, "\tData Avail Int Support\n");
968
969 /* INTERRUPT Setup */
970 init_waitqueue_head(&priv->read_queue);
971 init_waitqueue_head(&priv->int_queue);
972 if (irq != -1) {
973 /* Before doing irq testing issue a command to the TPM in polling mode
974 * to make sure it works. May as well use that command to set the
975 * proper timeouts for the driver.
976 */
977 if (tpm_get_timeouts(chip)) {
978 dev_err(dev, "Could not get TPM timeouts and durations\n");
979 rc = -ENODEV;
980 goto out_err;
981 }
982
983 tpm_chip_start(chip);
984 chip->flags |= TPM_CHIP_FLAG_IRQ;
985 if (irq) {
986 tpm_tis_probe_irq_single(chip, intmask, IRQF_SHARED,
987 irq);
988 if (!(chip->flags & TPM_CHIP_FLAG_IRQ))
989 dev_err(&chip->dev, FW_BUG
990 "TPM interrupt not working, polling instead\n");
991 } else {
992 tpm_tis_probe_irq(chip, intmask);
993 }
994 tpm_chip_stop(chip);
995 }
996
997 rc = tpm_chip_register(chip);
998 if (rc)
999 goto out_err;
1000
1001 if (chip->ops->clk_enable != NULL)
1002 chip->ops->clk_enable(chip, false);
1003
1004 return 0;
1005 out_err:
1006 if ((chip->ops != NULL) && (chip->ops->clk_enable != NULL))
1007 chip->ops->clk_enable(chip, false);
1008
1009 tpm_tis_remove(chip);
1010
1011 return rc;
1012 }
1013 EXPORT_SYMBOL_GPL(tpm_tis_core_init);
1014
1015 #ifdef CONFIG_PM_SLEEP
tpm_tis_reenable_interrupts(struct tpm_chip * chip)1016 static void tpm_tis_reenable_interrupts(struct tpm_chip *chip)
1017 {
1018 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
1019 u32 intmask;
1020 int rc;
1021
1022 if (chip->ops->clk_enable != NULL)
1023 chip->ops->clk_enable(chip, true);
1024
1025 /* reenable interrupts that device may have lost or
1026 * BIOS/firmware may have disabled
1027 */
1028 rc = tpm_tis_write8(priv, TPM_INT_VECTOR(priv->locality), priv->irq);
1029 if (rc < 0)
1030 goto out;
1031
1032 rc = tpm_tis_read32(priv, TPM_INT_ENABLE(priv->locality), &intmask);
1033 if (rc < 0)
1034 goto out;
1035
1036 intmask |= TPM_INTF_CMD_READY_INT
1037 | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
1038 | TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE;
1039
1040 tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality), intmask);
1041
1042 out:
1043 if (chip->ops->clk_enable != NULL)
1044 chip->ops->clk_enable(chip, false);
1045
1046 return;
1047 }
1048
tpm_tis_resume(struct device * dev)1049 int tpm_tis_resume(struct device *dev)
1050 {
1051 struct tpm_chip *chip = dev_get_drvdata(dev);
1052 int ret;
1053
1054 if (chip->flags & TPM_CHIP_FLAG_IRQ)
1055 tpm_tis_reenable_interrupts(chip);
1056
1057 ret = tpm_pm_resume(dev);
1058 if (ret)
1059 return ret;
1060
1061 /* TPM 1.2 requires self-test on resume. This function actually returns
1062 * an error code but for unknown reason it isn't handled.
1063 */
1064 if (!(chip->flags & TPM_CHIP_FLAG_TPM2))
1065 tpm1_do_selftest(chip);
1066
1067 return 0;
1068 }
1069 EXPORT_SYMBOL_GPL(tpm_tis_resume);
1070 #endif
1071
1072 MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
1073 MODULE_DESCRIPTION("TPM Driver");
1074 MODULE_VERSION("2.0");
1075 MODULE_LICENSE("GPL");
1076
