1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef _HNS_ROCE_DEVICE_H
34 #define _HNS_ROCE_DEVICE_H
35
36 #include <rdma/ib_verbs.h>
37 #include <rdma/hns-abi.h>
38
39 #define PCI_REVISION_ID_HIP08 0x21
40 #define PCI_REVISION_ID_HIP09 0x30
41
42 #define HNS_ROCE_MAX_MSG_LEN 0x80000000
43
44 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6
45
46 #define BA_BYTE_LEN 8
47
48 #define HNS_ROCE_MIN_CQE_NUM 0x40
49 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1
50
51 #define HNS_ROCE_MAX_IRQ_NUM 128
52
53 #define HNS_ROCE_SGE_IN_WQE 2
54 #define HNS_ROCE_SGE_SHIFT 4
55
56 #define EQ_ENABLE 1
57 #define EQ_DISABLE 0
58
59 #define HNS_ROCE_CEQ 0
60 #define HNS_ROCE_AEQ 1
61
62 #define HNS_ROCE_CEQE_SIZE 0x4
63 #define HNS_ROCE_AEQE_SIZE 0x10
64
65 #define HNS_ROCE_V3_EQE_SIZE 0x40
66
67 #define HNS_ROCE_V2_CQE_SIZE 32
68 #define HNS_ROCE_V3_CQE_SIZE 64
69
70 #define HNS_ROCE_V2_QPC_SZ 256
71 #define HNS_ROCE_V3_QPC_SZ 512
72
73 #define HNS_ROCE_MAX_PORTS 6
74 #define HNS_ROCE_GID_SIZE 16
75 #define HNS_ROCE_SGE_SIZE 16
76 #define HNS_ROCE_DWQE_SIZE 65536
77
78 #define HNS_ROCE_HOP_NUM_0 0xff
79
80 #define MR_TYPE_MR 0x00
81 #define MR_TYPE_FRMR 0x01
82 #define MR_TYPE_DMA 0x03
83
84 #define HNS_ROCE_FRMR_MAX_PA 512
85
86 #define PKEY_ID 0xffff
87 #define NODE_DESC_SIZE 64
88 #define DB_REG_OFFSET 0x1000
89
90 /* Configure to HW for PAGE_SIZE larger than 4KB */
91 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12)
92
93 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4
94 #define SRQ_DB_REG 0x230
95
96 #define HNS_ROCE_QP_BANK_NUM 8
97 #define HNS_ROCE_CQ_BANK_NUM 4
98
99 #define CQ_BANKID_SHIFT 2
100
101 enum {
102 SERV_TYPE_RC,
103 SERV_TYPE_UC,
104 SERV_TYPE_RD,
105 SERV_TYPE_UD,
106 SERV_TYPE_XRC = 5,
107 };
108
109 enum hns_roce_event {
110 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01,
111 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02,
112 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03,
113 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04,
114 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
115 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06,
116 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07,
117 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08,
118 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09,
119 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a,
120 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b,
121 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c,
122 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d,
123 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f,
124 /* 0x10 and 0x11 is unused in currently application case */
125 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12,
126 HNS_ROCE_EVENT_TYPE_MB = 0x13,
127 HNS_ROCE_EVENT_TYPE_FLR = 0x15,
128 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16,
129 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17,
130 };
131
132 enum {
133 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0),
134 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1),
135 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2),
136 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3),
137 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4),
138 HNS_ROCE_CAP_FLAG_SRQ = BIT(5),
139 HNS_ROCE_CAP_FLAG_XRC = BIT(6),
140 HNS_ROCE_CAP_FLAG_MW = BIT(7),
141 HNS_ROCE_CAP_FLAG_FRMR = BIT(8),
142 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9),
143 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10),
144 HNS_ROCE_CAP_FLAG_DIRECT_WQE = BIT(12),
145 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14),
146 HNS_ROCE_CAP_FLAG_STASH = BIT(17),
147 };
148
149 #define HNS_ROCE_DB_TYPE_COUNT 2
150 #define HNS_ROCE_DB_UNIT_SIZE 4
151
152 enum {
153 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
154 };
155
156 enum hns_roce_reset_stage {
157 HNS_ROCE_STATE_NON_RST,
158 HNS_ROCE_STATE_RST_BEF_DOWN,
159 HNS_ROCE_STATE_RST_DOWN,
160 HNS_ROCE_STATE_RST_UNINIT,
161 HNS_ROCE_STATE_RST_INIT,
162 HNS_ROCE_STATE_RST_INITED,
163 };
164
165 enum hns_roce_instance_state {
166 HNS_ROCE_STATE_NON_INIT,
167 HNS_ROCE_STATE_INIT,
168 HNS_ROCE_STATE_INITED,
169 HNS_ROCE_STATE_UNINIT,
170 };
171
172 enum {
173 HNS_ROCE_RST_DIRECT_RETURN = 0,
174 };
175
176 #define HNS_ROCE_CMD_SUCCESS 1
177
178 /* The minimum page size is 4K for hardware */
179 #define HNS_HW_PAGE_SHIFT 12
180 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT)
181
182 struct hns_roce_uar {
183 u64 pfn;
184 unsigned long index;
185 unsigned long logic_idx;
186 };
187
188 enum hns_roce_mmap_type {
189 HNS_ROCE_MMAP_TYPE_DB = 1,
190 HNS_ROCE_MMAP_TYPE_DWQE,
191 };
192
193 struct hns_user_mmap_entry {
194 struct rdma_user_mmap_entry rdma_entry;
195 enum hns_roce_mmap_type mmap_type;
196 u64 address;
197 };
198
199 struct hns_roce_ucontext {
200 struct ib_ucontext ibucontext;
201 struct hns_roce_uar uar;
202 struct list_head page_list;
203 struct mutex page_mutex;
204 struct hns_user_mmap_entry *db_mmap_entry;
205 };
206
207 struct hns_roce_pd {
208 struct ib_pd ibpd;
209 unsigned long pdn;
210 };
211
212 struct hns_roce_xrcd {
213 struct ib_xrcd ibxrcd;
214 u32 xrcdn;
215 };
216
217 struct hns_roce_bitmap {
218 /* Bitmap Traversal last a bit which is 1 */
219 unsigned long last;
220 unsigned long top;
221 unsigned long max;
222 unsigned long reserved_top;
223 unsigned long mask;
224 spinlock_t lock;
225 unsigned long *table;
226 };
227
228 struct hns_roce_ida {
229 struct ida ida;
230 u32 min; /* Lowest ID to allocate. */
231 u32 max; /* Highest ID to allocate. */
232 };
233
234 /* For Hardware Entry Memory */
235 struct hns_roce_hem_table {
236 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
237 u32 type;
238 /* HEM array elment num */
239 unsigned long num_hem;
240 /* Single obj size */
241 unsigned long obj_size;
242 unsigned long table_chunk_size;
243 struct mutex mutex;
244 struct hns_roce_hem **hem;
245 u64 **bt_l1;
246 dma_addr_t *bt_l1_dma_addr;
247 u64 **bt_l0;
248 dma_addr_t *bt_l0_dma_addr;
249 };
250
251 struct hns_roce_buf_region {
252 u32 offset; /* page offset */
253 u32 count; /* page count */
254 int hopnum; /* addressing hop num */
255 };
256
257 #define HNS_ROCE_MAX_BT_REGION 3
258 #define HNS_ROCE_MAX_BT_LEVEL 3
259 struct hns_roce_hem_list {
260 struct list_head root_bt;
261 /* link all bt dma mem by hop config */
262 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
263 struct list_head btm_bt; /* link all bottom bt in @mid_bt */
264 dma_addr_t root_ba; /* pointer to the root ba table */
265 };
266
267 struct hns_roce_buf_attr {
268 struct {
269 size_t size; /* region size */
270 int hopnum; /* multi-hop addressing hop num */
271 } region[HNS_ROCE_MAX_BT_REGION];
272 unsigned int region_count; /* valid region count */
273 unsigned int page_shift; /* buffer page shift */
274 unsigned int user_access; /* umem access flag */
275 bool mtt_only; /* only alloc buffer-required MTT memory */
276 };
277
278 struct hns_roce_hem_cfg {
279 dma_addr_t root_ba; /* root BA table's address */
280 bool is_direct; /* addressing without BA table */
281 unsigned int ba_pg_shift; /* BA table page shift */
282 unsigned int buf_pg_shift; /* buffer page shift */
283 unsigned int buf_pg_count; /* buffer page count */
284 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
285 unsigned int region_count;
286 };
287
288 /* memory translate region */
289 struct hns_roce_mtr {
290 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
291 struct ib_umem *umem; /* user space buffer */
292 struct hns_roce_buf *kmem; /* kernel space buffer */
293 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */
294 };
295
296 struct hns_roce_mw {
297 struct ib_mw ibmw;
298 u32 pdn;
299 u32 rkey;
300 int enabled; /* MW's active status */
301 u32 pbl_hop_num;
302 u32 pbl_ba_pg_sz;
303 u32 pbl_buf_pg_sz;
304 };
305
306 struct hns_roce_mr {
307 struct ib_mr ibmr;
308 u64 iova; /* MR's virtual original addr */
309 u64 size; /* Address range of MR */
310 u32 key; /* Key of MR */
311 u32 pd; /* PD num of MR */
312 u32 access; /* Access permission of MR */
313 int enabled; /* MR's active status */
314 int type; /* MR's register type */
315 u32 pbl_hop_num; /* multi-hop number */
316 struct hns_roce_mtr pbl_mtr;
317 u32 npages;
318 dma_addr_t *page_list;
319 };
320
321 struct hns_roce_mr_table {
322 struct hns_roce_ida mtpt_ida;
323 struct hns_roce_hem_table mtpt_table;
324 };
325
326 struct hns_roce_wq {
327 u64 *wrid; /* Work request ID */
328 spinlock_t lock;
329 u32 wqe_cnt; /* WQE num */
330 u32 max_gs;
331 u32 rsv_sge;
332 u32 offset;
333 u32 wqe_shift; /* WQE size */
334 u32 head;
335 u32 tail;
336 void __iomem *db_reg;
337 };
338
339 struct hns_roce_sge {
340 unsigned int sge_cnt; /* SGE num */
341 u32 offset;
342 u32 sge_shift; /* SGE size */
343 };
344
345 struct hns_roce_buf_list {
346 void *buf;
347 dma_addr_t map;
348 };
349
350 /*
351 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous
352 * dma address range.
353 *
354 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep.
355 *
356 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even
357 * the allocated size is smaller than the required size.
358 */
359 enum {
360 HNS_ROCE_BUF_DIRECT = BIT(0),
361 HNS_ROCE_BUF_NOSLEEP = BIT(1),
362 HNS_ROCE_BUF_NOFAIL = BIT(2),
363 };
364
365 struct hns_roce_buf {
366 struct hns_roce_buf_list *trunk_list;
367 u32 ntrunks;
368 u32 npages;
369 unsigned int trunk_shift;
370 unsigned int page_shift;
371 };
372
373 struct hns_roce_db_pgdir {
374 struct list_head list;
375 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
376 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
377 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT];
378 u32 *page;
379 dma_addr_t db_dma;
380 };
381
382 struct hns_roce_user_db_page {
383 struct list_head list;
384 struct ib_umem *umem;
385 unsigned long user_virt;
386 refcount_t refcount;
387 };
388
389 struct hns_roce_db {
390 u32 *db_record;
391 union {
392 struct hns_roce_db_pgdir *pgdir;
393 struct hns_roce_user_db_page *user_page;
394 } u;
395 dma_addr_t dma;
396 void *virt_addr;
397 unsigned long index;
398 unsigned long order;
399 };
400
401 struct hns_roce_cq {
402 struct ib_cq ib_cq;
403 struct hns_roce_mtr mtr;
404 struct hns_roce_db db;
405 u32 flags;
406 spinlock_t lock;
407 u32 cq_depth;
408 u32 cons_index;
409 u32 *set_ci_db;
410 void __iomem *db_reg;
411 int arm_sn;
412 int cqe_size;
413 unsigned long cqn;
414 u32 vector;
415 refcount_t refcount;
416 struct completion free;
417 struct list_head sq_list; /* all qps on this send cq */
418 struct list_head rq_list; /* all qps on this recv cq */
419 int is_armed; /* cq is armed */
420 struct list_head node; /* all armed cqs are on a list */
421 };
422
423 struct hns_roce_idx_que {
424 struct hns_roce_mtr mtr;
425 u32 entry_shift;
426 unsigned long *bitmap;
427 u32 head;
428 u32 tail;
429 };
430
431 struct hns_roce_srq {
432 struct ib_srq ibsrq;
433 unsigned long srqn;
434 u32 wqe_cnt;
435 int max_gs;
436 u32 rsv_sge;
437 u32 wqe_shift;
438 u32 cqn;
439 u32 xrcdn;
440 void __iomem *db_reg;
441
442 refcount_t refcount;
443 struct completion free;
444
445 struct hns_roce_mtr buf_mtr;
446
447 u64 *wrid;
448 struct hns_roce_idx_que idx_que;
449 spinlock_t lock;
450 struct mutex mutex;
451 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
452 };
453
454 struct hns_roce_uar_table {
455 struct hns_roce_bitmap bitmap;
456 };
457
458 struct hns_roce_bank {
459 struct ida ida;
460 u32 inuse; /* Number of IDs allocated */
461 u32 min; /* Lowest ID to allocate. */
462 u32 max; /* Highest ID to allocate. */
463 u32 next; /* Next ID to allocate. */
464 };
465
466 struct hns_roce_idx_table {
467 u32 *spare_idx;
468 u32 head;
469 u32 tail;
470 };
471
472 struct hns_roce_qp_table {
473 struct hns_roce_hem_table qp_table;
474 struct hns_roce_hem_table irrl_table;
475 struct hns_roce_hem_table trrl_table;
476 struct hns_roce_hem_table sccc_table;
477 struct mutex scc_mutex;
478 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
479 struct mutex bank_mutex;
480 struct hns_roce_idx_table idx_table;
481 };
482
483 struct hns_roce_cq_table {
484 struct xarray array;
485 struct hns_roce_hem_table table;
486 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM];
487 struct mutex bank_mutex;
488 };
489
490 struct hns_roce_srq_table {
491 struct hns_roce_ida srq_ida;
492 struct xarray xa;
493 struct hns_roce_hem_table table;
494 };
495
496 struct hns_roce_av {
497 u8 port;
498 u8 gid_index;
499 u8 stat_rate;
500 u8 hop_limit;
501 u32 flowlabel;
502 u16 udp_sport;
503 u8 sl;
504 u8 tclass;
505 u8 dgid[HNS_ROCE_GID_SIZE];
506 u8 mac[ETH_ALEN];
507 u16 vlan_id;
508 u8 vlan_en;
509 };
510
511 struct hns_roce_ah {
512 struct ib_ah ibah;
513 struct hns_roce_av av;
514 };
515
516 struct hns_roce_cmd_context {
517 struct completion done;
518 int result;
519 int next;
520 u64 out_param;
521 u16 token;
522 u16 busy;
523 };
524
525 enum hns_roce_cmdq_state {
526 HNS_ROCE_CMDQ_STATE_NORMAL,
527 HNS_ROCE_CMDQ_STATE_FATAL_ERR,
528 };
529
530 struct hns_roce_cmdq {
531 struct dma_pool *pool;
532 struct semaphore poll_sem;
533 /*
534 * Event mode: cmd register mutex protection,
535 * ensure to not exceed max_cmds and user use limit region
536 */
537 struct semaphore event_sem;
538 int max_cmds;
539 spinlock_t context_lock;
540 int free_head;
541 struct hns_roce_cmd_context *context;
542 /*
543 * Process whether use event mode, init default non-zero
544 * After the event queue of cmd event ready,
545 * can switch into event mode
546 * close device, switch into poll mode(non event mode)
547 */
548 u8 use_events;
549 enum hns_roce_cmdq_state state;
550 };
551
552 struct hns_roce_cmd_mailbox {
553 void *buf;
554 dma_addr_t dma;
555 };
556
557 struct hns_roce_mbox_msg {
558 u64 in_param;
559 u64 out_param;
560 u8 cmd;
561 u32 tag;
562 u16 token;
563 u8 event_en;
564 };
565
566 struct hns_roce_dev;
567
568 struct hns_roce_rinl_sge {
569 void *addr;
570 u32 len;
571 };
572
573 struct hns_roce_rinl_wqe {
574 struct hns_roce_rinl_sge *sg_list;
575 u32 sge_cnt;
576 };
577
578 struct hns_roce_rinl_buf {
579 struct hns_roce_rinl_wqe *wqe_list;
580 u32 wqe_cnt;
581 };
582
583 enum {
584 HNS_ROCE_FLUSH_FLAG = 0,
585 };
586
587 struct hns_roce_work {
588 struct hns_roce_dev *hr_dev;
589 struct work_struct work;
590 int event_type;
591 int sub_type;
592 u32 queue_num;
593 };
594
595 struct hns_roce_qp {
596 struct ib_qp ibqp;
597 struct hns_roce_wq rq;
598 struct hns_roce_db rdb;
599 struct hns_roce_db sdb;
600 unsigned long en_flags;
601 enum ib_sig_type sq_signal_bits;
602 struct hns_roce_wq sq;
603
604 struct hns_roce_mtr mtr;
605
606 u32 buff_size;
607 struct mutex mutex;
608 u8 port;
609 u8 phy_port;
610 u8 sl;
611 u8 resp_depth;
612 u8 state;
613 u32 atomic_rd_en;
614 u32 qkey;
615 void (*event)(struct hns_roce_qp *qp,
616 enum hns_roce_event event_type);
617 unsigned long qpn;
618
619 u32 xrcdn;
620
621 refcount_t refcount;
622 struct completion free;
623
624 struct hns_roce_sge sge;
625 u32 next_sge;
626 enum ib_mtu path_mtu;
627 u32 max_inline_data;
628 u8 free_mr_en;
629
630 /* 0: flush needed, 1: unneeded */
631 unsigned long flush_flag;
632 struct hns_roce_work flush_work;
633 struct hns_roce_rinl_buf rq_inl_buf;
634 struct list_head node; /* all qps are on a list */
635 struct list_head rq_node; /* all recv qps are on a list */
636 struct list_head sq_node; /* all send qps are on a list */
637 struct hns_user_mmap_entry *dwqe_mmap_entry;
638 };
639
640 struct hns_roce_ib_iboe {
641 spinlock_t lock;
642 struct net_device *netdevs[HNS_ROCE_MAX_PORTS];
643 struct notifier_block nb;
644 u8 phy_port[HNS_ROCE_MAX_PORTS];
645 };
646
647 struct hns_roce_ceqe {
648 __le32 comp;
649 __le32 rsv[15];
650 };
651
652 #define CEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_ceqe, h, l)
653
654 #define CEQE_CQN CEQE_FIELD_LOC(23, 0)
655 #define CEQE_OWNER CEQE_FIELD_LOC(31, 31)
656
657 struct hns_roce_aeqe {
658 __le32 asyn;
659 union {
660 struct {
661 __le32 num;
662 u32 rsv0;
663 u32 rsv1;
664 } queue_event;
665
666 struct {
667 __le64 out_param;
668 __le16 token;
669 u8 status;
670 u8 rsv0;
671 } __packed cmd;
672 } event;
673 __le32 rsv[12];
674 };
675
676 #define AEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_aeqe, h, l)
677
678 #define AEQE_EVENT_TYPE AEQE_FIELD_LOC(7, 0)
679 #define AEQE_SUB_TYPE AEQE_FIELD_LOC(15, 8)
680 #define AEQE_OWNER AEQE_FIELD_LOC(31, 31)
681 #define AEQE_EVENT_QUEUE_NUM AEQE_FIELD_LOC(55, 32)
682
683 struct hns_roce_eq {
684 struct hns_roce_dev *hr_dev;
685 void __iomem *db_reg;
686
687 int type_flag; /* Aeq:1 ceq:0 */
688 int eqn;
689 u32 entries;
690 int eqe_size;
691 int irq;
692 u32 cons_index;
693 int over_ignore;
694 int coalesce;
695 int arm_st;
696 int hop_num;
697 struct hns_roce_mtr mtr;
698 u16 eq_max_cnt;
699 u32 eq_period;
700 int shift;
701 int event_type;
702 int sub_type;
703 };
704
705 struct hns_roce_eq_table {
706 struct hns_roce_eq *eq;
707 };
708
709 enum cong_type {
710 CONG_TYPE_DCQCN,
711 CONG_TYPE_LDCP,
712 CONG_TYPE_HC3,
713 CONG_TYPE_DIP,
714 };
715
716 struct hns_roce_caps {
717 u64 fw_ver;
718 u8 num_ports;
719 int gid_table_len[HNS_ROCE_MAX_PORTS];
720 int pkey_table_len[HNS_ROCE_MAX_PORTS];
721 int local_ca_ack_delay;
722 int num_uars;
723 u32 phy_num_uars;
724 u32 max_sq_sg;
725 u32 max_sq_inline;
726 u32 max_rq_sg;
727 u32 rsv0;
728 u32 num_qps;
729 u32 num_pi_qps;
730 u32 reserved_qps;
731 u32 num_srqs;
732 u32 max_wqes;
733 u32 max_srq_wrs;
734 u32 max_srq_sges;
735 u32 max_sq_desc_sz;
736 u32 max_rq_desc_sz;
737 u32 rsv2;
738 int max_qp_init_rdma;
739 int max_qp_dest_rdma;
740 u32 num_cqs;
741 u32 max_cqes;
742 u32 min_cqes;
743 u32 min_wqes;
744 u32 reserved_cqs;
745 u32 reserved_srqs;
746 int num_aeq_vectors;
747 int num_comp_vectors;
748 int num_other_vectors;
749 u32 num_mtpts;
750 u32 rsv1;
751 u32 num_srqwqe_segs;
752 u32 num_idx_segs;
753 int reserved_mrws;
754 int reserved_uars;
755 int num_pds;
756 int reserved_pds;
757 u32 num_xrcds;
758 u32 reserved_xrcds;
759 u32 mtt_entry_sz;
760 u32 cqe_sz;
761 u32 page_size_cap;
762 u32 reserved_lkey;
763 int mtpt_entry_sz;
764 int qpc_sz;
765 int irrl_entry_sz;
766 int trrl_entry_sz;
767 int cqc_entry_sz;
768 int sccc_sz;
769 int qpc_timer_entry_sz;
770 int cqc_timer_entry_sz;
771 int srqc_entry_sz;
772 int idx_entry_sz;
773 u32 pbl_ba_pg_sz;
774 u32 pbl_buf_pg_sz;
775 u32 pbl_hop_num;
776 int aeqe_depth;
777 int ceqe_depth;
778 u32 aeqe_size;
779 u32 ceqe_size;
780 enum ib_mtu max_mtu;
781 u32 qpc_bt_num;
782 u32 qpc_timer_bt_num;
783 u32 srqc_bt_num;
784 u32 cqc_bt_num;
785 u32 cqc_timer_bt_num;
786 u32 mpt_bt_num;
787 u32 eqc_bt_num;
788 u32 smac_bt_num;
789 u32 sgid_bt_num;
790 u32 sccc_bt_num;
791 u32 gmv_bt_num;
792 u32 qpc_ba_pg_sz;
793 u32 qpc_buf_pg_sz;
794 u32 qpc_hop_num;
795 u32 srqc_ba_pg_sz;
796 u32 srqc_buf_pg_sz;
797 u32 srqc_hop_num;
798 u32 cqc_ba_pg_sz;
799 u32 cqc_buf_pg_sz;
800 u32 cqc_hop_num;
801 u32 mpt_ba_pg_sz;
802 u32 mpt_buf_pg_sz;
803 u32 mpt_hop_num;
804 u32 mtt_ba_pg_sz;
805 u32 mtt_buf_pg_sz;
806 u32 mtt_hop_num;
807 u32 wqe_sq_hop_num;
808 u32 wqe_sge_hop_num;
809 u32 wqe_rq_hop_num;
810 u32 sccc_ba_pg_sz;
811 u32 sccc_buf_pg_sz;
812 u32 sccc_hop_num;
813 u32 qpc_timer_ba_pg_sz;
814 u32 qpc_timer_buf_pg_sz;
815 u32 qpc_timer_hop_num;
816 u32 cqc_timer_ba_pg_sz;
817 u32 cqc_timer_buf_pg_sz;
818 u32 cqc_timer_hop_num;
819 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */
820 u32 cqe_buf_pg_sz;
821 u32 cqe_hop_num;
822 u32 srqwqe_ba_pg_sz;
823 u32 srqwqe_buf_pg_sz;
824 u32 srqwqe_hop_num;
825 u32 idx_ba_pg_sz;
826 u32 idx_buf_pg_sz;
827 u32 idx_hop_num;
828 u32 eqe_ba_pg_sz;
829 u32 eqe_buf_pg_sz;
830 u32 eqe_hop_num;
831 u32 gmv_entry_num;
832 u32 gmv_entry_sz;
833 u32 gmv_ba_pg_sz;
834 u32 gmv_buf_pg_sz;
835 u32 gmv_hop_num;
836 u32 sl_num;
837 u32 llm_buf_pg_sz;
838 u32 chunk_sz; /* chunk size in non multihop mode */
839 u64 flags;
840 u16 default_ceq_max_cnt;
841 u16 default_ceq_period;
842 u16 default_aeq_max_cnt;
843 u16 default_aeq_period;
844 u16 default_aeq_arm_st;
845 u16 default_ceq_arm_st;
846 enum cong_type cong_type;
847 };
848
849 enum hns_roce_device_state {
850 HNS_ROCE_DEVICE_STATE_INITED,
851 HNS_ROCE_DEVICE_STATE_RST_DOWN,
852 HNS_ROCE_DEVICE_STATE_UNINIT,
853 };
854
855 struct hns_roce_hw {
856 int (*cmq_init)(struct hns_roce_dev *hr_dev);
857 void (*cmq_exit)(struct hns_roce_dev *hr_dev);
858 int (*hw_profile)(struct hns_roce_dev *hr_dev);
859 int (*hw_init)(struct hns_roce_dev *hr_dev);
860 void (*hw_exit)(struct hns_roce_dev *hr_dev);
861 int (*post_mbox)(struct hns_roce_dev *hr_dev,
862 struct hns_roce_mbox_msg *mbox_msg);
863 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev);
864 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy);
865 int (*set_gid)(struct hns_roce_dev *hr_dev, int gid_index,
866 const union ib_gid *gid, const struct ib_gid_attr *attr);
867 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port,
868 const u8 *addr);
869 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
870 struct hns_roce_mr *mr);
871 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
872 struct hns_roce_mr *mr, int flags,
873 void *mb_buf);
874 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
875 struct hns_roce_mr *mr);
876 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
877 void (*write_cqc)(struct hns_roce_dev *hr_dev,
878 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
879 dma_addr_t dma_handle);
880 int (*set_hem)(struct hns_roce_dev *hr_dev,
881 struct hns_roce_hem_table *table, int obj, u32 step_idx);
882 int (*clear_hem)(struct hns_roce_dev *hr_dev,
883 struct hns_roce_hem_table *table, int obj,
884 u32 step_idx);
885 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
886 int attr_mask, enum ib_qp_state cur_state,
887 enum ib_qp_state new_state);
888 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
889 struct hns_roce_qp *hr_qp);
890 void (*dereg_mr)(struct hns_roce_dev *hr_dev);
891 int (*init_eq)(struct hns_roce_dev *hr_dev);
892 void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
893 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf);
894 int (*query_cqc)(struct hns_roce_dev *hr_dev, u32 cqn, void *buffer);
895 int (*query_qpc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer);
896 int (*query_mpt)(struct hns_roce_dev *hr_dev, u32 key, void *buffer);
897 const struct ib_device_ops *hns_roce_dev_ops;
898 const struct ib_device_ops *hns_roce_dev_srq_ops;
899 };
900
901 struct hns_roce_dev {
902 struct ib_device ib_dev;
903 struct pci_dev *pci_dev;
904 struct device *dev;
905 struct hns_roce_uar priv_uar;
906 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
907 spinlock_t sm_lock;
908 bool active;
909 bool is_reset;
910 bool dis_db;
911 unsigned long reset_cnt;
912 struct hns_roce_ib_iboe iboe;
913 enum hns_roce_device_state state;
914 struct list_head qp_list; /* list of all qps on this dev */
915 spinlock_t qp_list_lock; /* protect qp_list */
916 struct list_head dip_list; /* list of all dest ips on this dev */
917 spinlock_t dip_list_lock; /* protect dip_list */
918
919 struct list_head pgdir_list;
920 struct mutex pgdir_mutex;
921 int irq[HNS_ROCE_MAX_IRQ_NUM];
922 u8 __iomem *reg_base;
923 void __iomem *mem_base;
924 struct hns_roce_caps caps;
925 struct xarray qp_table_xa;
926
927 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
928 u64 sys_image_guid;
929 u32 vendor_id;
930 u32 vendor_part_id;
931 u32 hw_rev;
932 void __iomem *priv_addr;
933
934 struct hns_roce_cmdq cmd;
935 struct hns_roce_ida pd_ida;
936 struct hns_roce_ida xrcd_ida;
937 struct hns_roce_ida uar_ida;
938 struct hns_roce_mr_table mr_table;
939 struct hns_roce_cq_table cq_table;
940 struct hns_roce_srq_table srq_table;
941 struct hns_roce_qp_table qp_table;
942 struct hns_roce_eq_table eq_table;
943 struct hns_roce_hem_table qpc_timer_table;
944 struct hns_roce_hem_table cqc_timer_table;
945 /* GMV is the memory area that the driver allocates for the hardware
946 * to store SGID, SMAC and VLAN information.
947 */
948 struct hns_roce_hem_table gmv_table;
949
950 int cmd_mod;
951 int loop_idc;
952 u32 sdb_offset;
953 u32 odb_offset;
954 const struct hns_roce_hw *hw;
955 void *priv;
956 struct workqueue_struct *irq_workq;
957 struct work_struct ecc_work;
958 u32 func_num;
959 u32 is_vf;
960 u32 cong_algo_tmpl_id;
961 u64 dwqe_page;
962 };
963
to_hr_dev(struct ib_device * ib_dev)964 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
965 {
966 return container_of(ib_dev, struct hns_roce_dev, ib_dev);
967 }
968
969 static inline struct hns_roce_ucontext
to_hr_ucontext(struct ib_ucontext * ibucontext)970 *to_hr_ucontext(struct ib_ucontext *ibucontext)
971 {
972 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
973 }
974
to_hr_pd(struct ib_pd * ibpd)975 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
976 {
977 return container_of(ibpd, struct hns_roce_pd, ibpd);
978 }
979
to_hr_xrcd(struct ib_xrcd * ibxrcd)980 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd)
981 {
982 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd);
983 }
984
to_hr_ah(struct ib_ah * ibah)985 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
986 {
987 return container_of(ibah, struct hns_roce_ah, ibah);
988 }
989
to_hr_mr(struct ib_mr * ibmr)990 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
991 {
992 return container_of(ibmr, struct hns_roce_mr, ibmr);
993 }
994
to_hr_mw(struct ib_mw * ibmw)995 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
996 {
997 return container_of(ibmw, struct hns_roce_mw, ibmw);
998 }
999
to_hr_qp(struct ib_qp * ibqp)1000 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1001 {
1002 return container_of(ibqp, struct hns_roce_qp, ibqp);
1003 }
1004
to_hr_cq(struct ib_cq * ib_cq)1005 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1006 {
1007 return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1008 }
1009
to_hr_srq(struct ib_srq * ibsrq)1010 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1011 {
1012 return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1013 }
1014
1015 static inline struct hns_user_mmap_entry *
to_hns_mmap(struct rdma_user_mmap_entry * rdma_entry)1016 to_hns_mmap(struct rdma_user_mmap_entry *rdma_entry)
1017 {
1018 return container_of(rdma_entry, struct hns_user_mmap_entry, rdma_entry);
1019 }
1020
hns_roce_write64_k(__le32 val[2],void __iomem * dest)1021 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1022 {
1023 writeq(*(u64 *)val, dest);
1024 }
1025
1026 static inline struct hns_roce_qp
__hns_roce_qp_lookup(struct hns_roce_dev * hr_dev,u32 qpn)1027 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1028 {
1029 return xa_load(&hr_dev->qp_table_xa, qpn);
1030 }
1031
hns_roce_buf_offset(struct hns_roce_buf * buf,unsigned int offset)1032 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf,
1033 unsigned int offset)
1034 {
1035 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
1036 (offset & ((1 << buf->trunk_shift) - 1));
1037 }
1038
hns_roce_buf_dma_addr(struct hns_roce_buf * buf,unsigned int offset)1039 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf,
1040 unsigned int offset)
1041 {
1042 return buf->trunk_list[offset >> buf->trunk_shift].map +
1043 (offset & ((1 << buf->trunk_shift) - 1));
1044 }
1045
hns_roce_buf_page(struct hns_roce_buf * buf,u32 idx)1046 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx)
1047 {
1048 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift);
1049 }
1050
1051 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1052
to_hr_hw_page_addr(u64 addr)1053 static inline u64 to_hr_hw_page_addr(u64 addr)
1054 {
1055 return addr >> HNS_HW_PAGE_SHIFT;
1056 }
1057
to_hr_hw_page_shift(u32 page_shift)1058 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1059 {
1060 return page_shift - HNS_HW_PAGE_SHIFT;
1061 }
1062
to_hr_hem_hopnum(u32 hopnum,u32 count)1063 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1064 {
1065 if (count > 0)
1066 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1067
1068 return 0;
1069 }
1070
to_hr_hem_entries_size(u32 count,u32 buf_shift)1071 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1072 {
1073 return hr_hw_page_align(count << buf_shift);
1074 }
1075
to_hr_hem_entries_count(u32 count,u32 buf_shift)1076 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1077 {
1078 return hr_hw_page_align(count << buf_shift) >> buf_shift;
1079 }
1080
to_hr_hem_entries_shift(u32 count,u32 buf_shift)1081 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1082 {
1083 if (!count)
1084 return 0;
1085
1086 return ilog2(to_hr_hem_entries_count(count, buf_shift));
1087 }
1088
1089 #define DSCP_SHIFT 2
1090
get_tclass(const struct ib_global_route * grh)1091 static inline u8 get_tclass(const struct ib_global_route *grh)
1092 {
1093 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ?
1094 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class;
1095 }
1096
1097 void hns_roce_init_uar_table(struct hns_roce_dev *dev);
1098 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1099
1100 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1101 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1102 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1103 u64 out_param);
1104 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1105 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1106
1107 /* hns roce hw need current block and next block addr from mtt */
1108 #define MTT_MIN_COUNT 2
1109 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1110 u32 offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1111 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1112 struct hns_roce_buf_attr *buf_attr,
1113 unsigned int page_shift, struct ib_udata *udata,
1114 unsigned long user_addr);
1115 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1116 struct hns_roce_mtr *mtr);
1117 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1118 dma_addr_t *pages, unsigned int page_cnt);
1119
1120 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1121 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1122 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1123 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1124 void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1125 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev);
1126
1127 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1128 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1129 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1130
1131 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1132
1133 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1134 struct ib_udata *udata);
1135 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
hns_roce_destroy_ah(struct ib_ah * ah,u32 flags)1136 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
1137 {
1138 return 0;
1139 }
1140
1141 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1142 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1143
1144 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1145 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1146 u64 virt_addr, int access_flags,
1147 struct ib_udata *udata);
1148 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start,
1149 u64 length, u64 virt_addr,
1150 int mr_access_flags, struct ib_pd *pd,
1151 struct ib_udata *udata);
1152 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1153 u32 max_num_sg);
1154 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1155 unsigned int *sg_offset);
1156 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1157 unsigned long key_to_hw_index(u32 key);
1158
1159 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1160 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1161
1162 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1163 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size,
1164 u32 page_shift, u32 flags);
1165
1166 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1167 int buf_cnt, struct hns_roce_buf *buf,
1168 unsigned int page_shift);
1169 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1170 int buf_cnt, struct ib_umem *umem,
1171 unsigned int page_shift);
1172
1173 int hns_roce_create_srq(struct ib_srq *srq,
1174 struct ib_srq_init_attr *srq_init_attr,
1175 struct ib_udata *udata);
1176 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1177 enum ib_srq_attr_mask srq_attr_mask,
1178 struct ib_udata *udata);
1179 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1180
1181 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1182 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1183
1184 int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr,
1185 struct ib_udata *udata);
1186 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1187 int attr_mask, struct ib_udata *udata);
1188 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1189 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1190 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1191 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n);
1192 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1193 struct ib_cq *ib_cq);
1194 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1195 struct hns_roce_cq *recv_cq);
1196 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1197 struct hns_roce_cq *recv_cq);
1198 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1199 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1200 struct ib_udata *udata);
1201 __be32 send_ieth(const struct ib_send_wr *wr);
1202 int to_hr_qp_type(int qp_type);
1203
1204 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1205 struct ib_udata *udata);
1206
1207 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1208 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt,
1209 struct hns_roce_db *db);
1210 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1211 struct hns_roce_db *db);
1212 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1213 int order);
1214 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1215
1216 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1217 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1218 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp);
1219 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1220 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1221 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index);
1222 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1223 int hns_roce_init(struct hns_roce_dev *hr_dev);
1224 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1225 int hns_roce_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq);
1226 int hns_roce_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq);
1227 int hns_roce_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp);
1228 int hns_roce_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ib_qp);
1229 int hns_roce_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr);
1230 int hns_roce_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr);
1231 struct hns_user_mmap_entry *
1232 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
1233 size_t length,
1234 enum hns_roce_mmap_type mmap_type);
1235 #endif /* _HNS_ROCE_DEVICE_H */
1236
