1/* 2 * Low level TLB miss handlers for Book3E 3 * 4 * Copyright (C) 2008-2009 5 * Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13#include <asm/processor.h> 14#include <asm/reg.h> 15#include <asm/page.h> 16#include <asm/mmu.h> 17#include <asm/ppc_asm.h> 18#include <asm/asm-offsets.h> 19#include <asm/cputable.h> 20#include <asm/pgtable.h> 21#include <asm/exception-64e.h> 22#include <asm/ppc-opcode.h> 23#include <asm/kvm_asm.h> 24#include <asm/kvm_booke_hv_asm.h> 25#include <asm/feature-fixups.h> 26 27#ifdef CONFIG_PPC_64K_PAGES 28#define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1) 29#else 30#define VPTE_PMD_SHIFT (PTE_INDEX_SIZE) 31#endif 32#define VPTE_PUD_SHIFT (VPTE_PMD_SHIFT + PMD_INDEX_SIZE) 33#define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE) 34#define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE) 35 36/********************************************************************** 37 * * 38 * TLB miss handling for Book3E with a bolted linear mapping * 39 * No virtual page table, no nested TLB misses * 40 * * 41 **********************************************************************/ 42 43/* 44 * Note that, unlike non-bolted handlers, TLB_EXFRAME is not 45 * modified by the TLB miss handlers themselves, since the TLB miss 46 * handler code will not itself cause a recursive TLB miss. 47 * 48 * TLB_EXFRAME will be modified when crit/mc/debug exceptions are 49 * entered/exited. 50 */ 51.macro tlb_prolog_bolted intnum addr 52 mtspr SPRN_SPRG_GEN_SCRATCH,r12 53 mfspr r12,SPRN_SPRG_TLB_EXFRAME 54 std r13,EX_TLB_R13(r12) 55 std r10,EX_TLB_R10(r12) 56 mfspr r13,SPRN_SPRG_PACA 57 58 mfcr r10 59 std r11,EX_TLB_R11(r12) 60#ifdef CONFIG_KVM_BOOKE_HV 61BEGIN_FTR_SECTION 62 mfspr r11, SPRN_SRR1 63END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 64#endif 65 DO_KVM \intnum, SPRN_SRR1 66 std r16,EX_TLB_R16(r12) 67 mfspr r16,\addr /* get faulting address */ 68 std r14,EX_TLB_R14(r12) 69 ld r14,PACAPGD(r13) 70 std r15,EX_TLB_R15(r12) 71 std r10,EX_TLB_CR(r12) 72#ifdef CONFIG_PPC_FSL_BOOK3E 73 std r7,EX_TLB_R7(r12) 74#endif 75 TLB_MISS_PROLOG_STATS 76.endm 77 78.macro tlb_epilog_bolted 79 ld r14,EX_TLB_CR(r12) 80#ifdef CONFIG_PPC_FSL_BOOK3E 81 ld r7,EX_TLB_R7(r12) 82#endif 83 ld r10,EX_TLB_R10(r12) 84 ld r11,EX_TLB_R11(r12) 85 ld r13,EX_TLB_R13(r12) 86 mtcr r14 87 ld r14,EX_TLB_R14(r12) 88 ld r15,EX_TLB_R15(r12) 89 TLB_MISS_RESTORE_STATS 90 ld r16,EX_TLB_R16(r12) 91 mfspr r12,SPRN_SPRG_GEN_SCRATCH 92.endm 93 94/* Data TLB miss */ 95 START_EXCEPTION(data_tlb_miss_bolted) 96 tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR 97 98 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */ 99 100 /* We do the user/kernel test for the PID here along with the RW test 101 */ 102 /* We pre-test some combination of permissions to avoid double 103 * faults: 104 * 105 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE 106 * ESR_ST is 0x00800000 107 * _PAGE_BAP_SW is 0x00000010 108 * So the shift is >> 19. This tests for supervisor writeability. 109 * If the page happens to be supervisor writeable and not user 110 * writeable, we will take a new fault later, but that should be 111 * a rare enough case. 112 * 113 * We also move ESR_ST in _PAGE_DIRTY position 114 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11 115 * 116 * MAS1 is preset for all we need except for TID that needs to 117 * be cleared for kernel translations 118 */ 119 120 mfspr r11,SPRN_ESR 121 122 srdi r15,r16,60 /* get region */ 123 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 124 bne- dtlb_miss_fault_bolted /* Bail if fault addr is invalid */ 125 126 rlwinm r10,r11,32-19,27,27 127 rlwimi r10,r11,32-16,19,19 128 cmpwi r15,0 /* user vs kernel check */ 129 ori r10,r10,_PAGE_PRESENT 130 oris r11,r10,_PAGE_ACCESSED@h 131 132 TLB_MISS_STATS_SAVE_INFO_BOLTED 133 bne tlb_miss_kernel_bolted 134 135tlb_miss_common_bolted: 136/* 137 * This is the guts of the TLB miss handler for bolted-linear. 138 * We are entered with: 139 * 140 * r16 = faulting address 141 * r15 = crap (free to use) 142 * r14 = page table base 143 * r13 = PACA 144 * r11 = PTE permission mask 145 * r10 = crap (free to use) 146 */ 147 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3 148 cmpldi cr0,r14,0 149 clrrdi r15,r15,3 150 beq tlb_miss_fault_bolted /* No PGDIR, bail */ 151 152BEGIN_MMU_FTR_SECTION 153 /* Set the TLB reservation and search for existing entry. Then load 154 * the entry. 155 */ 156 PPC_TLBSRX_DOT(0,R16) 157 ldx r14,r14,r15 /* grab pgd entry */ 158 beq tlb_miss_done_bolted /* tlb exists already, bail */ 159MMU_FTR_SECTION_ELSE 160 ldx r14,r14,r15 /* grab pgd entry */ 161ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) 162 163#ifndef CONFIG_PPC_64K_PAGES 164 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3 165 clrrdi r15,r15,3 166 cmpdi cr0,r14,0 167 bge tlb_miss_fault_bolted /* Bad pgd entry or hugepage; bail */ 168 ldx r14,r14,r15 /* grab pud entry */ 169#endif /* CONFIG_PPC_64K_PAGES */ 170 171 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3 172 clrrdi r15,r15,3 173 cmpdi cr0,r14,0 174 bge tlb_miss_fault_bolted 175 ldx r14,r14,r15 /* Grab pmd entry */ 176 177 rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3 178 clrrdi r15,r15,3 179 cmpdi cr0,r14,0 180 bge tlb_miss_fault_bolted 181 ldx r14,r14,r15 /* Grab PTE, normal (!huge) page */ 182 183 /* Check if required permissions are met */ 184 andc. r15,r11,r14 185 rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT 186 bne- tlb_miss_fault_bolted 187 188 /* Now we build the MAS: 189 * 190 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG 191 * MAS 1 : Almost fully setup 192 * - PID already updated by caller if necessary 193 * - TSIZE need change if !base page size, not 194 * yet implemented for now 195 * MAS 2 : Defaults not useful, need to be redone 196 * MAS 3+7 : Needs to be done 197 */ 198 clrrdi r11,r16,12 /* Clear low crap in EA */ 199 clrldi r15,r15,12 /* Clear crap at the top */ 200 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */ 201 rlwimi r15,r14,32-8,22,25 /* Move in U bits */ 202 mtspr SPRN_MAS2,r11 203 andi. r11,r14,_PAGE_DIRTY 204 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */ 205 206 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */ 207 bne 1f 208 li r11,MAS3_SW|MAS3_UW 209 andc r15,r15,r11 2101: 211 mtspr SPRN_MAS7_MAS3,r15 212 tlbwe 213 214tlb_miss_done_bolted: 215 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK) 216 tlb_epilog_bolted 217 rfi 218 219itlb_miss_kernel_bolted: 220 li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */ 221 oris r11,r11,_PAGE_ACCESSED@h 222tlb_miss_kernel_bolted: 223 mfspr r10,SPRN_MAS1 224 ld r14,PACA_KERNELPGD(r13) 225 cmpldi cr0,r15,8 /* Check for vmalloc region */ 226 rlwinm r10,r10,0,16,1 /* Clear TID */ 227 mtspr SPRN_MAS1,r10 228 beq+ tlb_miss_common_bolted 229 230tlb_miss_fault_bolted: 231 /* We need to check if it was an instruction miss */ 232 andi. r10,r11,_PAGE_EXEC|_PAGE_BAP_SX 233 bne itlb_miss_fault_bolted 234dtlb_miss_fault_bolted: 235 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT) 236 tlb_epilog_bolted 237 b exc_data_storage_book3e 238itlb_miss_fault_bolted: 239 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) 240 tlb_epilog_bolted 241 b exc_instruction_storage_book3e 242 243/* Instruction TLB miss */ 244 START_EXCEPTION(instruction_tlb_miss_bolted) 245 tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0 246 247 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 248 srdi r15,r16,60 /* get region */ 249 TLB_MISS_STATS_SAVE_INFO_BOLTED 250 bne- itlb_miss_fault_bolted 251 252 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */ 253 254 /* We do the user/kernel test for the PID here along with the RW test 255 */ 256 257 cmpldi cr0,r15,0 /* Check for user region */ 258 oris r11,r11,_PAGE_ACCESSED@h 259 beq tlb_miss_common_bolted 260 b itlb_miss_kernel_bolted 261 262#ifdef CONFIG_PPC_FSL_BOOK3E 263/* 264 * TLB miss handling for e6500 and derivatives, using hardware tablewalk. 265 * 266 * Linear mapping is bolted: no virtual page table or nested TLB misses 267 * Indirect entries in TLB1, hardware loads resulting direct entries 268 * into TLB0 269 * No HES or NV hint on TLB1, so we need to do software round-robin 270 * No tlbsrx. so we need a spinlock, and we have to deal 271 * with MAS-damage caused by tlbsx 272 * 4K pages only 273 */ 274 275 START_EXCEPTION(instruction_tlb_miss_e6500) 276 tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0 277 278 ld r11,PACA_TCD_PTR(r13) 279 srdi. r15,r16,60 /* get region */ 280 ori r16,r16,1 281 282 TLB_MISS_STATS_SAVE_INFO_BOLTED 283 bne tlb_miss_kernel_e6500 /* user/kernel test */ 284 285 b tlb_miss_common_e6500 286 287 START_EXCEPTION(data_tlb_miss_e6500) 288 tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR 289 290 ld r11,PACA_TCD_PTR(r13) 291 srdi. r15,r16,60 /* get region */ 292 rldicr r16,r16,0,62 293 294 TLB_MISS_STATS_SAVE_INFO_BOLTED 295 bne tlb_miss_kernel_e6500 /* user vs kernel check */ 296 297/* 298 * This is the guts of the TLB miss handler for e6500 and derivatives. 299 * We are entered with: 300 * 301 * r16 = page of faulting address (low bit 0 if data, 1 if instruction) 302 * r15 = crap (free to use) 303 * r14 = page table base 304 * r13 = PACA 305 * r11 = tlb_per_core ptr 306 * r10 = crap (free to use) 307 * r7 = esel_next 308 */ 309tlb_miss_common_e6500: 310 crmove cr2*4+2,cr0*4+2 /* cr2.eq != 0 if kernel address */ 311 312BEGIN_FTR_SECTION /* CPU_FTR_SMT */ 313 /* 314 * Search if we already have an indirect entry for that virtual 315 * address, and if we do, bail out. 316 * 317 * MAS6:IND should be already set based on MAS4 318 */ 319 lhz r10,PACAPACAINDEX(r13) 320 addi r10,r10,1 321 crclr cr1*4+eq /* set cr1.eq = 0 for non-recursive */ 3221: lbarx r15,0,r11 323 cmpdi r15,0 324 bne 2f 325 stbcx. r10,0,r11 326 bne 1b 3273: 328 .subsection 1 3292: cmpd cr1,r15,r10 /* recursive lock due to mcheck/crit/etc? */ 330 beq cr1,3b /* unlock will happen if cr1.eq = 0 */ 33110: lbz r15,0(r11) 332 cmpdi r15,0 333 bne 10b 334 b 1b 335 .previous 336END_FTR_SECTION_IFSET(CPU_FTR_SMT) 337 338 lbz r7,TCD_ESEL_NEXT(r11) 339 340BEGIN_FTR_SECTION /* CPU_FTR_SMT */ 341 /* 342 * Erratum A-008139 says that we can't use tlbwe to change 343 * an indirect entry in any way (including replacing or 344 * invalidating) if the other thread could be in the process 345 * of a lookup. The workaround is to invalidate the entry 346 * with tlbilx before overwriting. 347 */ 348 349 rlwinm r10,r7,16,0xff0000 350 oris r10,r10,MAS0_TLBSEL(1)@h 351 mtspr SPRN_MAS0,r10 352 isync 353 tlbre 354 mfspr r15,SPRN_MAS1 355 andis. r15,r15,MAS1_VALID@h 356 beq 5f 357 358BEGIN_FTR_SECTION_NESTED(532) 359 mfspr r10,SPRN_MAS8 360 rlwinm r10,r10,0,0x80000fff /* tgs,tlpid -> sgs,slpid */ 361 mtspr SPRN_MAS5,r10 362END_FTR_SECTION_NESTED(CPU_FTR_EMB_HV,CPU_FTR_EMB_HV,532) 363 364 mfspr r10,SPRN_MAS1 365 rlwinm r15,r10,0,0x3fff0000 /* tid -> spid */ 366 rlwimi r15,r10,20,0x00000003 /* ind,ts -> sind,sas */ 367 mfspr r10,SPRN_MAS6 368 mtspr SPRN_MAS6,r15 369 370 mfspr r15,SPRN_MAS2 371 isync 372 tlbilxva 0,r15 373 isync 374 375 mtspr SPRN_MAS6,r10 376 3775: 378BEGIN_FTR_SECTION_NESTED(532) 379 li r10,0 380 mtspr SPRN_MAS8,r10 381 mtspr SPRN_MAS5,r10 382END_FTR_SECTION_NESTED(CPU_FTR_EMB_HV,CPU_FTR_EMB_HV,532) 383 384 tlbsx 0,r16 385 mfspr r10,SPRN_MAS1 386 andis. r15,r10,MAS1_VALID@h 387 bne tlb_miss_done_e6500 388FTR_SECTION_ELSE 389 mfspr r10,SPRN_MAS1 390ALT_FTR_SECTION_END_IFSET(CPU_FTR_SMT) 391 392 oris r10,r10,MAS1_VALID@h 393 beq cr2,4f 394 rlwinm r10,r10,0,16,1 /* Clear TID */ 3954: mtspr SPRN_MAS1,r10 396 397 /* Now, we need to walk the page tables. First check if we are in 398 * range. 399 */ 400 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 401 bne- tlb_miss_fault_e6500 402 403 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3 404 cmpldi cr0,r14,0 405 clrrdi r15,r15,3 406 beq- tlb_miss_fault_e6500 /* No PGDIR, bail */ 407 ldx r14,r14,r15 /* grab pgd entry */ 408 409 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3 410 clrrdi r15,r15,3 411 cmpdi cr0,r14,0 412 bge tlb_miss_huge_e6500 /* Bad pgd entry or hugepage; bail */ 413 ldx r14,r14,r15 /* grab pud entry */ 414 415 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3 416 clrrdi r15,r15,3 417 cmpdi cr0,r14,0 418 bge tlb_miss_huge_e6500 419 ldx r14,r14,r15 /* Grab pmd entry */ 420 421 mfspr r10,SPRN_MAS0 422 cmpdi cr0,r14,0 423 bge tlb_miss_huge_e6500 424 425 /* Now we build the MAS for a 2M indirect page: 426 * 427 * MAS 0 : ESEL needs to be filled by software round-robin 428 * MAS 1 : Fully set up 429 * - PID already updated by caller if necessary 430 * - TSIZE for now is base ind page size always 431 * - TID already cleared if necessary 432 * MAS 2 : Default not 2M-aligned, need to be redone 433 * MAS 3+7 : Needs to be done 434 */ 435 436 ori r14,r14,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT) 437 mtspr SPRN_MAS7_MAS3,r14 438 439 clrrdi r15,r16,21 /* make EA 2M-aligned */ 440 mtspr SPRN_MAS2,r15 441 442tlb_miss_huge_done_e6500: 443 lbz r16,TCD_ESEL_MAX(r11) 444 lbz r14,TCD_ESEL_FIRST(r11) 445 rlwimi r10,r7,16,0x00ff0000 /* insert esel_next into MAS0 */ 446 addi r7,r7,1 /* increment esel_next */ 447 mtspr SPRN_MAS0,r10 448 cmpw r7,r16 449 iseleq r7,r14,r7 /* if next == last use first */ 450 stb r7,TCD_ESEL_NEXT(r11) 451 452 tlbwe 453 454tlb_miss_done_e6500: 455 .macro tlb_unlock_e6500 456BEGIN_FTR_SECTION 457 beq cr1,1f /* no unlock if lock was recursively grabbed */ 458 li r15,0 459 isync 460 stb r15,0(r11) 4611: 462END_FTR_SECTION_IFSET(CPU_FTR_SMT) 463 .endm 464 465 tlb_unlock_e6500 466 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK) 467 tlb_epilog_bolted 468 rfi 469 470tlb_miss_huge_e6500: 471 beq tlb_miss_fault_e6500 472 li r10,1 473 andi. r15,r14,HUGEPD_SHIFT_MASK@l /* r15 = psize */ 474 rldimi r14,r10,63,0 /* Set PD_HUGE */ 475 xor r14,r14,r15 /* Clear size bits */ 476 ldx r14,0,r14 477 478 /* 479 * Now we build the MAS for a huge page. 480 * 481 * MAS 0 : ESEL needs to be filled by software round-robin 482 * - can be handled by indirect code 483 * MAS 1 : Need to clear IND and set TSIZE 484 * MAS 2,3+7: Needs to be redone similar to non-tablewalk handler 485 */ 486 487 subi r15,r15,10 /* Convert psize to tsize */ 488 mfspr r10,SPRN_MAS1 489 rlwinm r10,r10,0,~MAS1_IND 490 rlwimi r10,r15,MAS1_TSIZE_SHIFT,MAS1_TSIZE_MASK 491 mtspr SPRN_MAS1,r10 492 493 li r10,-0x400 494 sld r15,r10,r15 /* Generate mask based on size */ 495 and r10,r16,r15 496 rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT 497 rlwimi r10,r14,32-19,27,31 /* Insert WIMGE */ 498 clrldi r15,r15,PAGE_SHIFT /* Clear crap at the top */ 499 rlwimi r15,r14,32-8,22,25 /* Move in U bits */ 500 mtspr SPRN_MAS2,r10 501 andi. r10,r14,_PAGE_DIRTY 502 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */ 503 504 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */ 505 bne 1f 506 li r10,MAS3_SW|MAS3_UW 507 andc r15,r15,r10 5081: 509 mtspr SPRN_MAS7_MAS3,r15 510 511 mfspr r10,SPRN_MAS0 512 b tlb_miss_huge_done_e6500 513 514tlb_miss_kernel_e6500: 515 ld r14,PACA_KERNELPGD(r13) 516 cmpldi cr1,r15,8 /* Check for vmalloc region */ 517 beq+ cr1,tlb_miss_common_e6500 518 519tlb_miss_fault_e6500: 520 tlb_unlock_e6500 521 /* We need to check if it was an instruction miss */ 522 andi. r16,r16,1 523 bne itlb_miss_fault_e6500 524dtlb_miss_fault_e6500: 525 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT) 526 tlb_epilog_bolted 527 b exc_data_storage_book3e 528itlb_miss_fault_e6500: 529 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) 530 tlb_epilog_bolted 531 b exc_instruction_storage_book3e 532#endif /* CONFIG_PPC_FSL_BOOK3E */ 533 534/********************************************************************** 535 * * 536 * TLB miss handling for Book3E with TLB reservation and HES support * 537 * * 538 **********************************************************************/ 539 540 541/* Data TLB miss */ 542 START_EXCEPTION(data_tlb_miss) 543 TLB_MISS_PROLOG 544 545 /* Now we handle the fault proper. We only save DEAR in normal 546 * fault case since that's the only interesting values here. 547 * We could probably also optimize by not saving SRR0/1 in the 548 * linear mapping case but I'll leave that for later 549 */ 550 mfspr r14,SPRN_ESR 551 mfspr r16,SPRN_DEAR /* get faulting address */ 552 srdi r15,r16,60 /* get region */ 553 cmpldi cr0,r15,0xc /* linear mapping ? */ 554 TLB_MISS_STATS_SAVE_INFO 555 beq tlb_load_linear /* yes -> go to linear map load */ 556 557 /* The page tables are mapped virtually linear. At this point, though, 558 * we don't know whether we are trying to fault in a first level 559 * virtual address or a virtual page table address. We can get that 560 * from bit 0x1 of the region ID which we have set for a page table 561 */ 562 andi. r10,r15,0x1 563 bne- virt_page_table_tlb_miss 564 565 std r14,EX_TLB_ESR(r12); /* save ESR */ 566 std r16,EX_TLB_DEAR(r12); /* save DEAR */ 567 568 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */ 569 li r11,_PAGE_PRESENT 570 oris r11,r11,_PAGE_ACCESSED@h 571 572 /* We do the user/kernel test for the PID here along with the RW test 573 */ 574 cmpldi cr0,r15,0 /* Check for user region */ 575 576 /* We pre-test some combination of permissions to avoid double 577 * faults: 578 * 579 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE 580 * ESR_ST is 0x00800000 581 * _PAGE_BAP_SW is 0x00000010 582 * So the shift is >> 19. This tests for supervisor writeability. 583 * If the page happens to be supervisor writeable and not user 584 * writeable, we will take a new fault later, but that should be 585 * a rare enough case. 586 * 587 * We also move ESR_ST in _PAGE_DIRTY position 588 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11 589 * 590 * MAS1 is preset for all we need except for TID that needs to 591 * be cleared for kernel translations 592 */ 593 rlwimi r11,r14,32-19,27,27 594 rlwimi r11,r14,32-16,19,19 595 beq normal_tlb_miss 596 /* XXX replace the RMW cycles with immediate loads + writes */ 5971: mfspr r10,SPRN_MAS1 598 cmpldi cr0,r15,8 /* Check for vmalloc region */ 599 rlwinm r10,r10,0,16,1 /* Clear TID */ 600 mtspr SPRN_MAS1,r10 601 beq+ normal_tlb_miss 602 603 /* We got a crappy address, just fault with whatever DEAR and ESR 604 * are here 605 */ 606 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT) 607 TLB_MISS_EPILOG_ERROR 608 b exc_data_storage_book3e 609 610/* Instruction TLB miss */ 611 START_EXCEPTION(instruction_tlb_miss) 612 TLB_MISS_PROLOG 613 614 /* If we take a recursive fault, the second level handler may need 615 * to know whether we are handling a data or instruction fault in 616 * order to get to the right store fault handler. We provide that 617 * info by writing a crazy value in ESR in our exception frame 618 */ 619 li r14,-1 /* store to exception frame is done later */ 620 621 /* Now we handle the fault proper. We only save DEAR in the non 622 * linear mapping case since we know the linear mapping case will 623 * not re-enter. We could indeed optimize and also not save SRR0/1 624 * in the linear mapping case but I'll leave that for later 625 * 626 * Faulting address is SRR0 which is already in r16 627 */ 628 srdi r15,r16,60 /* get region */ 629 cmpldi cr0,r15,0xc /* linear mapping ? */ 630 TLB_MISS_STATS_SAVE_INFO 631 beq tlb_load_linear /* yes -> go to linear map load */ 632 633 /* We do the user/kernel test for the PID here along with the RW test 634 */ 635 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */ 636 oris r11,r11,_PAGE_ACCESSED@h 637 638 cmpldi cr0,r15,0 /* Check for user region */ 639 std r14,EX_TLB_ESR(r12) /* write crazy -1 to frame */ 640 beq normal_tlb_miss 641 642 li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */ 643 oris r11,r11,_PAGE_ACCESSED@h 644 /* XXX replace the RMW cycles with immediate loads + writes */ 645 mfspr r10,SPRN_MAS1 646 cmpldi cr0,r15,8 /* Check for vmalloc region */ 647 rlwinm r10,r10,0,16,1 /* Clear TID */ 648 mtspr SPRN_MAS1,r10 649 beq+ normal_tlb_miss 650 651 /* We got a crappy address, just fault */ 652 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) 653 TLB_MISS_EPILOG_ERROR 654 b exc_instruction_storage_book3e 655 656/* 657 * This is the guts of the first-level TLB miss handler for direct 658 * misses. We are entered with: 659 * 660 * r16 = faulting address 661 * r15 = region ID 662 * r14 = crap (free to use) 663 * r13 = PACA 664 * r12 = TLB exception frame in PACA 665 * r11 = PTE permission mask 666 * r10 = crap (free to use) 667 */ 668normal_tlb_miss: 669 /* So we first construct the page table address. We do that by 670 * shifting the bottom of the address (not the region ID) by 671 * PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and 672 * or'ing the fourth high bit. 673 * 674 * NOTE: For 64K pages, we do things slightly differently in 675 * order to handle the weird page table format used by linux 676 */ 677 ori r10,r15,0x1 678#ifdef CONFIG_PPC_64K_PAGES 679 /* For the top bits, 16 bytes per PTE */ 680 rldicl r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4 681 /* Now create the bottom bits as 0 in position 0x8000 and 682 * the rest calculated for 8 bytes per PTE 683 */ 684 rldicl r15,r16,64-(PAGE_SHIFT-3),64-15 685 /* Insert the bottom bits in */ 686 rlwimi r14,r15,0,16,31 687#else 688 rldicl r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4 689#endif 690 sldi r15,r10,60 691 clrrdi r14,r14,3 692 or r10,r15,r14 693 694BEGIN_MMU_FTR_SECTION 695 /* Set the TLB reservation and search for existing entry. Then load 696 * the entry. 697 */ 698 PPC_TLBSRX_DOT(0,R16) 699 ld r14,0(r10) 700 beq normal_tlb_miss_done 701MMU_FTR_SECTION_ELSE 702 ld r14,0(r10) 703ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) 704 705finish_normal_tlb_miss: 706 /* Check if required permissions are met */ 707 andc. r15,r11,r14 708 bne- normal_tlb_miss_access_fault 709 710 /* Now we build the MAS: 711 * 712 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG 713 * MAS 1 : Almost fully setup 714 * - PID already updated by caller if necessary 715 * - TSIZE need change if !base page size, not 716 * yet implemented for now 717 * MAS 2 : Defaults not useful, need to be redone 718 * MAS 3+7 : Needs to be done 719 * 720 * TODO: mix up code below for better scheduling 721 */ 722 clrrdi r11,r16,12 /* Clear low crap in EA */ 723 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */ 724 mtspr SPRN_MAS2,r11 725 726 /* Check page size, if not standard, update MAS1 */ 727 rldicl r11,r14,64-8,64-8 728#ifdef CONFIG_PPC_64K_PAGES 729 cmpldi cr0,r11,BOOK3E_PAGESZ_64K 730#else 731 cmpldi cr0,r11,BOOK3E_PAGESZ_4K 732#endif 733 beq- 1f 734 mfspr r11,SPRN_MAS1 735 rlwimi r11,r14,31,21,24 736 rlwinm r11,r11,0,21,19 737 mtspr SPRN_MAS1,r11 7381: 739 /* Move RPN in position */ 740 rldicr r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT 741 clrldi r15,r11,12 /* Clear crap at the top */ 742 rlwimi r15,r14,32-8,22,25 /* Move in U bits */ 743 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */ 744 745 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */ 746 andi. r11,r14,_PAGE_DIRTY 747 bne 1f 748 li r11,MAS3_SW|MAS3_UW 749 andc r15,r15,r11 7501: 751BEGIN_MMU_FTR_SECTION 752 srdi r16,r15,32 753 mtspr SPRN_MAS3,r15 754 mtspr SPRN_MAS7,r16 755MMU_FTR_SECTION_ELSE 756 mtspr SPRN_MAS7_MAS3,r15 757ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS) 758 759 tlbwe 760 761normal_tlb_miss_done: 762 /* We don't bother with restoring DEAR or ESR since we know we are 763 * level 0 and just going back to userland. They are only needed 764 * if you are going to take an access fault 765 */ 766 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK) 767 TLB_MISS_EPILOG_SUCCESS 768 rfi 769 770normal_tlb_miss_access_fault: 771 /* We need to check if it was an instruction miss */ 772 andi. r10,r11,_PAGE_EXEC 773 bne 1f 774 ld r14,EX_TLB_DEAR(r12) 775 ld r15,EX_TLB_ESR(r12) 776 mtspr SPRN_DEAR,r14 777 mtspr SPRN_ESR,r15 778 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT) 779 TLB_MISS_EPILOG_ERROR 780 b exc_data_storage_book3e 7811: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) 782 TLB_MISS_EPILOG_ERROR 783 b exc_instruction_storage_book3e 784 785 786/* 787 * This is the guts of the second-level TLB miss handler for direct 788 * misses. We are entered with: 789 * 790 * r16 = virtual page table faulting address 791 * r15 = region (top 4 bits of address) 792 * r14 = crap (free to use) 793 * r13 = PACA 794 * r12 = TLB exception frame in PACA 795 * r11 = crap (free to use) 796 * r10 = crap (free to use) 797 * 798 * Note that this should only ever be called as a second level handler 799 * with the current scheme when using SW load. 800 * That means we can always get the original fault DEAR at 801 * EX_TLB_DEAR-EX_TLB_SIZE(r12) 802 * 803 * It can be re-entered by the linear mapping miss handler. However, to 804 * avoid too much complication, it will restart the whole fault at level 805 * 0 so we don't care too much about clobbers 806 * 807 * XXX That code was written back when we couldn't clobber r14. We can now, 808 * so we could probably optimize things a bit 809 */ 810virt_page_table_tlb_miss: 811 /* Are we hitting a kernel page table ? */ 812 andi. r10,r15,0x8 813 814 /* The cool thing now is that r10 contains 0 for user and 8 for kernel, 815 * and we happen to have the swapper_pg_dir at offset 8 from the user 816 * pgdir in the PACA :-). 817 */ 818 add r11,r10,r13 819 820 /* If kernel, we need to clear MAS1 TID */ 821 beq 1f 822 /* XXX replace the RMW cycles with immediate loads + writes */ 823 mfspr r10,SPRN_MAS1 824 rlwinm r10,r10,0,16,1 /* Clear TID */ 825 mtspr SPRN_MAS1,r10 8261: 827BEGIN_MMU_FTR_SECTION 828 /* Search if we already have a TLB entry for that virtual address, and 829 * if we do, bail out. 830 */ 831 PPC_TLBSRX_DOT(0,R16) 832 beq virt_page_table_tlb_miss_done 833END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV) 834 835 /* Now, we need to walk the page tables. First check if we are in 836 * range. 837 */ 838 rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4 839 bne- virt_page_table_tlb_miss_fault 840 841 /* Get the PGD pointer */ 842 ld r15,PACAPGD(r11) 843 cmpldi cr0,r15,0 844 beq- virt_page_table_tlb_miss_fault 845 846 /* Get to PGD entry */ 847 rldicl r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3 848 clrrdi r10,r11,3 849 ldx r15,r10,r15 850 cmpdi cr0,r15,0 851 bge virt_page_table_tlb_miss_fault 852 853#ifndef CONFIG_PPC_64K_PAGES 854 /* Get to PUD entry */ 855 rldicl r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3 856 clrrdi r10,r11,3 857 ldx r15,r10,r15 858 cmpdi cr0,r15,0 859 bge virt_page_table_tlb_miss_fault 860#endif /* CONFIG_PPC_64K_PAGES */ 861 862 /* Get to PMD entry */ 863 rldicl r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3 864 clrrdi r10,r11,3 865 ldx r15,r10,r15 866 cmpdi cr0,r15,0 867 bge virt_page_table_tlb_miss_fault 868 869 /* Ok, we're all right, we can now create a kernel translation for 870 * a 4K or 64K page from r16 -> r15. 871 */ 872 /* Now we build the MAS: 873 * 874 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG 875 * MAS 1 : Almost fully setup 876 * - PID already updated by caller if necessary 877 * - TSIZE for now is base page size always 878 * MAS 2 : Use defaults 879 * MAS 3+7 : Needs to be done 880 * 881 * So we only do MAS 2 and 3 for now... 882 */ 883 clrldi r11,r15,4 /* remove region ID from RPN */ 884 ori r10,r11,1 /* Or-in SR */ 885 886BEGIN_MMU_FTR_SECTION 887 srdi r16,r10,32 888 mtspr SPRN_MAS3,r10 889 mtspr SPRN_MAS7,r16 890MMU_FTR_SECTION_ELSE 891 mtspr SPRN_MAS7_MAS3,r10 892ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS) 893 894 tlbwe 895 896BEGIN_MMU_FTR_SECTION 897virt_page_table_tlb_miss_done: 898 899 /* We have overridden MAS2:EPN but currently our primary TLB miss 900 * handler will always restore it so that should not be an issue, 901 * if we ever optimize the primary handler to not write MAS2 on 902 * some cases, we'll have to restore MAS2:EPN here based on the 903 * original fault's DEAR. If we do that we have to modify the 904 * ITLB miss handler to also store SRR0 in the exception frame 905 * as DEAR. 906 * 907 * However, one nasty thing we did is we cleared the reservation 908 * (well, potentially we did). We do a trick here thus if we 909 * are not a level 0 exception (we interrupted the TLB miss) we 910 * offset the return address by -4 in order to replay the tlbsrx 911 * instruction there 912 */ 913 subf r10,r13,r12 914 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE 915 bne- 1f 916 ld r11,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13) 917 addi r10,r11,-4 918 std r10,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13) 9191: 920END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV) 921 /* Return to caller, normal case */ 922 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK); 923 TLB_MISS_EPILOG_SUCCESS 924 rfi 925 926virt_page_table_tlb_miss_fault: 927 /* If we fault here, things are a little bit tricky. We need to call 928 * either data or instruction store fault, and we need to retrieve 929 * the original fault address and ESR (for data). 930 * 931 * The thing is, we know that in normal circumstances, this is 932 * always called as a second level tlb miss for SW load or as a first 933 * level TLB miss for HW load, so we should be able to peek at the 934 * relevant information in the first exception frame in the PACA. 935 * 936 * However, we do need to double check that, because we may just hit 937 * a stray kernel pointer or a userland attack trying to hit those 938 * areas. If that is the case, we do a data fault. (We can't get here 939 * from an instruction tlb miss anyway). 940 * 941 * Note also that when going to a fault, we must unwind the previous 942 * level as well. Since we are doing that, we don't need to clear or 943 * restore the TLB reservation neither. 944 */ 945 subf r10,r13,r12 946 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE 947 bne- virt_page_table_tlb_miss_whacko_fault 948 949 /* We dig the original DEAR and ESR from slot 0 */ 950 ld r15,EX_TLB_DEAR+PACA_EXTLB(r13) 951 ld r16,EX_TLB_ESR+PACA_EXTLB(r13) 952 953 /* We check for the "special" ESR value for instruction faults */ 954 cmpdi cr0,r16,-1 955 beq 1f 956 mtspr SPRN_DEAR,r15 957 mtspr SPRN_ESR,r16 958 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT); 959 TLB_MISS_EPILOG_ERROR 960 b exc_data_storage_book3e 9611: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT); 962 TLB_MISS_EPILOG_ERROR 963 b exc_instruction_storage_book3e 964 965virt_page_table_tlb_miss_whacko_fault: 966 /* The linear fault will restart everything so ESR and DEAR will 967 * not have been clobbered, let's just fault with what we have 968 */ 969 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT); 970 TLB_MISS_EPILOG_ERROR 971 b exc_data_storage_book3e 972 973 974/************************************************************** 975 * * 976 * TLB miss handling for Book3E with hw page table support * 977 * * 978 **************************************************************/ 979 980 981/* Data TLB miss */ 982 START_EXCEPTION(data_tlb_miss_htw) 983 TLB_MISS_PROLOG 984 985 /* Now we handle the fault proper. We only save DEAR in normal 986 * fault case since that's the only interesting values here. 987 * We could probably also optimize by not saving SRR0/1 in the 988 * linear mapping case but I'll leave that for later 989 */ 990 mfspr r14,SPRN_ESR 991 mfspr r16,SPRN_DEAR /* get faulting address */ 992 srdi r11,r16,60 /* get region */ 993 cmpldi cr0,r11,0xc /* linear mapping ? */ 994 TLB_MISS_STATS_SAVE_INFO 995 beq tlb_load_linear /* yes -> go to linear map load */ 996 997 /* We do the user/kernel test for the PID here along with the RW test 998 */ 999 cmpldi cr0,r11,0 /* Check for user region */ 1000 ld r15,PACAPGD(r13) /* Load user pgdir */ 1001 beq htw_tlb_miss 1002 1003 /* XXX replace the RMW cycles with immediate loads + writes */ 10041: mfspr r10,SPRN_MAS1 1005 cmpldi cr0,r11,8 /* Check for vmalloc region */ 1006 rlwinm r10,r10,0,16,1 /* Clear TID */ 1007 mtspr SPRN_MAS1,r10 1008 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */ 1009 beq+ htw_tlb_miss 1010 1011 /* We got a crappy address, just fault with whatever DEAR and ESR 1012 * are here 1013 */ 1014 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT) 1015 TLB_MISS_EPILOG_ERROR 1016 b exc_data_storage_book3e 1017 1018/* Instruction TLB miss */ 1019 START_EXCEPTION(instruction_tlb_miss_htw) 1020 TLB_MISS_PROLOG 1021 1022 /* If we take a recursive fault, the second level handler may need 1023 * to know whether we are handling a data or instruction fault in 1024 * order to get to the right store fault handler. We provide that 1025 * info by keeping a crazy value for ESR in r14 1026 */ 1027 li r14,-1 /* store to exception frame is done later */ 1028 1029 /* Now we handle the fault proper. We only save DEAR in the non 1030 * linear mapping case since we know the linear mapping case will 1031 * not re-enter. We could indeed optimize and also not save SRR0/1 1032 * in the linear mapping case but I'll leave that for later 1033 * 1034 * Faulting address is SRR0 which is already in r16 1035 */ 1036 srdi r11,r16,60 /* get region */ 1037 cmpldi cr0,r11,0xc /* linear mapping ? */ 1038 TLB_MISS_STATS_SAVE_INFO 1039 beq tlb_load_linear /* yes -> go to linear map load */ 1040 1041 /* We do the user/kernel test for the PID here along with the RW test 1042 */ 1043 cmpldi cr0,r11,0 /* Check for user region */ 1044 ld r15,PACAPGD(r13) /* Load user pgdir */ 1045 beq htw_tlb_miss 1046 1047 /* XXX replace the RMW cycles with immediate loads + writes */ 10481: mfspr r10,SPRN_MAS1 1049 cmpldi cr0,r11,8 /* Check for vmalloc region */ 1050 rlwinm r10,r10,0,16,1 /* Clear TID */ 1051 mtspr SPRN_MAS1,r10 1052 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */ 1053 beq+ htw_tlb_miss 1054 1055 /* We got a crappy address, just fault */ 1056 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) 1057 TLB_MISS_EPILOG_ERROR 1058 b exc_instruction_storage_book3e 1059 1060 1061/* 1062 * This is the guts of the second-level TLB miss handler for direct 1063 * misses. We are entered with: 1064 * 1065 * r16 = virtual page table faulting address 1066 * r15 = PGD pointer 1067 * r14 = ESR 1068 * r13 = PACA 1069 * r12 = TLB exception frame in PACA 1070 * r11 = crap (free to use) 1071 * r10 = crap (free to use) 1072 * 1073 * It can be re-entered by the linear mapping miss handler. However, to 1074 * avoid too much complication, it will save/restore things for us 1075 */ 1076htw_tlb_miss: 1077 /* Search if we already have a TLB entry for that virtual address, and 1078 * if we do, bail out. 1079 * 1080 * MAS1:IND should be already set based on MAS4 1081 */ 1082 PPC_TLBSRX_DOT(0,R16) 1083 beq htw_tlb_miss_done 1084 1085 /* Now, we need to walk the page tables. First check if we are in 1086 * range. 1087 */ 1088 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 1089 bne- htw_tlb_miss_fault 1090 1091 /* Get the PGD pointer */ 1092 cmpldi cr0,r15,0 1093 beq- htw_tlb_miss_fault 1094 1095 /* Get to PGD entry */ 1096 rldicl r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3 1097 clrrdi r10,r11,3 1098 ldx r15,r10,r15 1099 cmpdi cr0,r15,0 1100 bge htw_tlb_miss_fault 1101 1102#ifndef CONFIG_PPC_64K_PAGES 1103 /* Get to PUD entry */ 1104 rldicl r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3 1105 clrrdi r10,r11,3 1106 ldx r15,r10,r15 1107 cmpdi cr0,r15,0 1108 bge htw_tlb_miss_fault 1109#endif /* CONFIG_PPC_64K_PAGES */ 1110 1111 /* Get to PMD entry */ 1112 rldicl r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3 1113 clrrdi r10,r11,3 1114 ldx r15,r10,r15 1115 cmpdi cr0,r15,0 1116 bge htw_tlb_miss_fault 1117 1118 /* Ok, we're all right, we can now create an indirect entry for 1119 * a 1M or 256M page. 1120 * 1121 * The last trick is now that because we use "half" pages for 1122 * the HTW (1M IND is 2K and 256M IND is 32K) we need to account 1123 * for an added LSB bit to the RPN. For 64K pages, there is no 1124 * problem as we already use 32K arrays (half PTE pages), but for 1125 * 4K page we need to extract a bit from the virtual address and 1126 * insert it into the "PA52" bit of the RPN. 1127 */ 1128#ifndef CONFIG_PPC_64K_PAGES 1129 rlwimi r15,r16,32-9,20,20 1130#endif 1131 /* Now we build the MAS: 1132 * 1133 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG 1134 * MAS 1 : Almost fully setup 1135 * - PID already updated by caller if necessary 1136 * - TSIZE for now is base ind page size always 1137 * MAS 2 : Use defaults 1138 * MAS 3+7 : Needs to be done 1139 */ 1140#ifdef CONFIG_PPC_64K_PAGES 1141 ori r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT) 1142#else 1143 ori r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT) 1144#endif 1145 1146BEGIN_MMU_FTR_SECTION 1147 srdi r16,r10,32 1148 mtspr SPRN_MAS3,r10 1149 mtspr SPRN_MAS7,r16 1150MMU_FTR_SECTION_ELSE 1151 mtspr SPRN_MAS7_MAS3,r10 1152ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS) 1153 1154 tlbwe 1155 1156htw_tlb_miss_done: 1157 /* We don't bother with restoring DEAR or ESR since we know we are 1158 * level 0 and just going back to userland. They are only needed 1159 * if you are going to take an access fault 1160 */ 1161 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK) 1162 TLB_MISS_EPILOG_SUCCESS 1163 rfi 1164 1165htw_tlb_miss_fault: 1166 /* We need to check if it was an instruction miss. We know this 1167 * though because r14 would contain -1 1168 */ 1169 cmpdi cr0,r14,-1 1170 beq 1f 1171 mtspr SPRN_DEAR,r16 1172 mtspr SPRN_ESR,r14 1173 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT) 1174 TLB_MISS_EPILOG_ERROR 1175 b exc_data_storage_book3e 11761: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT) 1177 TLB_MISS_EPILOG_ERROR 1178 b exc_instruction_storage_book3e 1179 1180/* 1181 * This is the guts of "any" level TLB miss handler for kernel linear 1182 * mapping misses. We are entered with: 1183 * 1184 * 1185 * r16 = faulting address 1186 * r15 = crap (free to use) 1187 * r14 = ESR (data) or -1 (instruction) 1188 * r13 = PACA 1189 * r12 = TLB exception frame in PACA 1190 * r11 = crap (free to use) 1191 * r10 = crap (free to use) 1192 * 1193 * In addition we know that we will not re-enter, so in theory, we could 1194 * use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later. 1195 * 1196 * We also need to be careful about MAS registers here & TLB reservation, 1197 * as we know we'll have clobbered them if we interrupt the main TLB miss 1198 * handlers in which case we probably want to do a full restart at level 1199 * 0 rather than saving / restoring the MAS. 1200 * 1201 * Note: If we care about performance of that core, we can easily shuffle 1202 * a few things around 1203 */ 1204tlb_load_linear: 1205 /* For now, we assume the linear mapping is contiguous and stops at 1206 * linear_map_top. We also assume the size is a multiple of 1G, thus 1207 * we only use 1G pages for now. That might have to be changed in a 1208 * final implementation, especially when dealing with hypervisors 1209 */ 1210 ld r11,PACATOC(r13) 1211 ld r11,linear_map_top@got(r11) 1212 ld r10,0(r11) 1213 tovirt(10,10) 1214 cmpld cr0,r16,r10 1215 bge tlb_load_linear_fault 1216 1217 /* MAS1 need whole new setup. */ 1218 li r15,(BOOK3E_PAGESZ_1GB<<MAS1_TSIZE_SHIFT) 1219 oris r15,r15,MAS1_VALID@h /* MAS1 needs V and TSIZE */ 1220 mtspr SPRN_MAS1,r15 1221 1222 /* Already somebody there ? */ 1223 PPC_TLBSRX_DOT(0,R16) 1224 beq tlb_load_linear_done 1225 1226 /* Now we build the remaining MAS. MAS0 and 2 should be fine 1227 * with their defaults, which leaves us with MAS 3 and 7. The 1228 * mapping is linear, so we just take the address, clear the 1229 * region bits, and or in the permission bits which are currently 1230 * hard wired 1231 */ 1232 clrrdi r10,r16,30 /* 1G page index */ 1233 clrldi r10,r10,4 /* clear region bits */ 1234 ori r10,r10,MAS3_SR|MAS3_SW|MAS3_SX 1235 1236BEGIN_MMU_FTR_SECTION 1237 srdi r16,r10,32 1238 mtspr SPRN_MAS3,r10 1239 mtspr SPRN_MAS7,r16 1240MMU_FTR_SECTION_ELSE 1241 mtspr SPRN_MAS7_MAS3,r10 1242ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS) 1243 1244 tlbwe 1245 1246tlb_load_linear_done: 1247 /* We use the "error" epilog for success as we do want to 1248 * restore to the initial faulting context, whatever it was. 1249 * We do that because we can't resume a fault within a TLB 1250 * miss handler, due to MAS and TLB reservation being clobbered. 1251 */ 1252 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR) 1253 TLB_MISS_EPILOG_ERROR 1254 rfi 1255 1256tlb_load_linear_fault: 1257 /* We keep the DEAR and ESR around, this shouldn't have happened */ 1258 cmpdi cr0,r14,-1 1259 beq 1f 1260 TLB_MISS_EPILOG_ERROR_SPECIAL 1261 b exc_data_storage_book3e 12621: TLB_MISS_EPILOG_ERROR_SPECIAL 1263 b exc_instruction_storage_book3e 1264 1265 1266#ifdef CONFIG_BOOK3E_MMU_TLB_STATS 1267.tlb_stat_inc: 12681: ldarx r8,0,r9 1269 addi r8,r8,1 1270 stdcx. r8,0,r9 1271 bne- 1b 1272 blr 1273#endif 1274
