1 /*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
12 *
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
24
25 #include <asm/tlb.h>
26 #include <asm/mach/map.h>
27
28 #include <linux/omap-dma.h>
29
30 #include "omap_hwmod.h"
31 #include "soc.h"
32 #include "iomap.h"
33 #include "voltage.h"
34 #include "powerdomain.h"
35 #include "clockdomain.h"
36 #include "common.h"
37 #include "clock.h"
38 #include "clock2xxx.h"
39 #include "clock3xxx.h"
40 #include "sdrc.h"
41 #include "control.h"
42 #include "serial.h"
43 #include "sram.h"
44 #include "cm2xxx.h"
45 #include "cm3xxx.h"
46 #include "cm33xx.h"
47 #include "cm44xx.h"
48 #include "prm.h"
49 #include "cm.h"
50 #include "prcm_mpu44xx.h"
51 #include "prminst44xx.h"
52 #include "prm2xxx.h"
53 #include "prm3xxx.h"
54 #include "prm33xx.h"
55 #include "prm44xx.h"
56 #include "opp2xxx.h"
57
58 /*
59 * omap_clk_soc_init: points to a function that does the SoC-specific
60 * clock initializations
61 */
62 static int (*omap_clk_soc_init)(void);
63
64 /*
65 * The machine specific code may provide the extra mapping besides the
66 * default mapping provided here.
67 */
68
69 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
70 static struct map_desc omap24xx_io_desc[] __initdata = {
71 {
72 .virtual = L3_24XX_VIRT,
73 .pfn = __phys_to_pfn(L3_24XX_PHYS),
74 .length = L3_24XX_SIZE,
75 .type = MT_DEVICE
76 },
77 {
78 .virtual = L4_24XX_VIRT,
79 .pfn = __phys_to_pfn(L4_24XX_PHYS),
80 .length = L4_24XX_SIZE,
81 .type = MT_DEVICE
82 },
83 };
84
85 #ifdef CONFIG_SOC_OMAP2420
86 static struct map_desc omap242x_io_desc[] __initdata = {
87 {
88 .virtual = DSP_MEM_2420_VIRT,
89 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
90 .length = DSP_MEM_2420_SIZE,
91 .type = MT_DEVICE
92 },
93 {
94 .virtual = DSP_IPI_2420_VIRT,
95 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
96 .length = DSP_IPI_2420_SIZE,
97 .type = MT_DEVICE
98 },
99 {
100 .virtual = DSP_MMU_2420_VIRT,
101 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
102 .length = DSP_MMU_2420_SIZE,
103 .type = MT_DEVICE
104 },
105 };
106
107 #endif
108
109 #ifdef CONFIG_SOC_OMAP2430
110 static struct map_desc omap243x_io_desc[] __initdata = {
111 {
112 .virtual = L4_WK_243X_VIRT,
113 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
114 .length = L4_WK_243X_SIZE,
115 .type = MT_DEVICE
116 },
117 {
118 .virtual = OMAP243X_GPMC_VIRT,
119 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
120 .length = OMAP243X_GPMC_SIZE,
121 .type = MT_DEVICE
122 },
123 {
124 .virtual = OMAP243X_SDRC_VIRT,
125 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
126 .length = OMAP243X_SDRC_SIZE,
127 .type = MT_DEVICE
128 },
129 {
130 .virtual = OMAP243X_SMS_VIRT,
131 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
132 .length = OMAP243X_SMS_SIZE,
133 .type = MT_DEVICE
134 },
135 };
136 #endif
137 #endif
138
139 #ifdef CONFIG_ARCH_OMAP3
140 static struct map_desc omap34xx_io_desc[] __initdata = {
141 {
142 .virtual = L3_34XX_VIRT,
143 .pfn = __phys_to_pfn(L3_34XX_PHYS),
144 .length = L3_34XX_SIZE,
145 .type = MT_DEVICE
146 },
147 {
148 .virtual = L4_34XX_VIRT,
149 .pfn = __phys_to_pfn(L4_34XX_PHYS),
150 .length = L4_34XX_SIZE,
151 .type = MT_DEVICE
152 },
153 {
154 .virtual = OMAP34XX_GPMC_VIRT,
155 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
156 .length = OMAP34XX_GPMC_SIZE,
157 .type = MT_DEVICE
158 },
159 {
160 .virtual = OMAP343X_SMS_VIRT,
161 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
162 .length = OMAP343X_SMS_SIZE,
163 .type = MT_DEVICE
164 },
165 {
166 .virtual = OMAP343X_SDRC_VIRT,
167 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
168 .length = OMAP343X_SDRC_SIZE,
169 .type = MT_DEVICE
170 },
171 {
172 .virtual = L4_PER_34XX_VIRT,
173 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
174 .length = L4_PER_34XX_SIZE,
175 .type = MT_DEVICE
176 },
177 {
178 .virtual = L4_EMU_34XX_VIRT,
179 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
180 .length = L4_EMU_34XX_SIZE,
181 .type = MT_DEVICE
182 },
183 };
184 #endif
185
186 #ifdef CONFIG_SOC_TI81XX
187 static struct map_desc omapti81xx_io_desc[] __initdata = {
188 {
189 .virtual = L4_34XX_VIRT,
190 .pfn = __phys_to_pfn(L4_34XX_PHYS),
191 .length = L4_34XX_SIZE,
192 .type = MT_DEVICE
193 }
194 };
195 #endif
196
197 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
198 static struct map_desc omapam33xx_io_desc[] __initdata = {
199 {
200 .virtual = L4_34XX_VIRT,
201 .pfn = __phys_to_pfn(L4_34XX_PHYS),
202 .length = L4_34XX_SIZE,
203 .type = MT_DEVICE
204 },
205 {
206 .virtual = L4_WK_AM33XX_VIRT,
207 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
208 .length = L4_WK_AM33XX_SIZE,
209 .type = MT_DEVICE
210 }
211 };
212 #endif
213
214 #ifdef CONFIG_ARCH_OMAP4
215 static struct map_desc omap44xx_io_desc[] __initdata = {
216 {
217 .virtual = L3_44XX_VIRT,
218 .pfn = __phys_to_pfn(L3_44XX_PHYS),
219 .length = L3_44XX_SIZE,
220 .type = MT_DEVICE,
221 },
222 {
223 .virtual = L4_44XX_VIRT,
224 .pfn = __phys_to_pfn(L4_44XX_PHYS),
225 .length = L4_44XX_SIZE,
226 .type = MT_DEVICE,
227 },
228 {
229 .virtual = L4_PER_44XX_VIRT,
230 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
231 .length = L4_PER_44XX_SIZE,
232 .type = MT_DEVICE,
233 },
234 };
235 #endif
236
237 #ifdef CONFIG_SOC_OMAP5
238 static struct map_desc omap54xx_io_desc[] __initdata = {
239 {
240 .virtual = L3_54XX_VIRT,
241 .pfn = __phys_to_pfn(L3_54XX_PHYS),
242 .length = L3_54XX_SIZE,
243 .type = MT_DEVICE,
244 },
245 {
246 .virtual = L4_54XX_VIRT,
247 .pfn = __phys_to_pfn(L4_54XX_PHYS),
248 .length = L4_54XX_SIZE,
249 .type = MT_DEVICE,
250 },
251 {
252 .virtual = L4_WK_54XX_VIRT,
253 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
254 .length = L4_WK_54XX_SIZE,
255 .type = MT_DEVICE,
256 },
257 {
258 .virtual = L4_PER_54XX_VIRT,
259 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
260 .length = L4_PER_54XX_SIZE,
261 .type = MT_DEVICE,
262 },
263 };
264 #endif
265
266 #ifdef CONFIG_SOC_DRA7XX
267 static struct map_desc dra7xx_io_desc[] __initdata = {
268 {
269 .virtual = L4_CFG_MPU_DRA7XX_VIRT,
270 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
271 .length = L4_CFG_MPU_DRA7XX_SIZE,
272 .type = MT_DEVICE,
273 },
274 {
275 .virtual = L3_MAIN_SN_DRA7XX_VIRT,
276 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
277 .length = L3_MAIN_SN_DRA7XX_SIZE,
278 .type = MT_DEVICE,
279 },
280 {
281 .virtual = L4_PER1_DRA7XX_VIRT,
282 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
283 .length = L4_PER1_DRA7XX_SIZE,
284 .type = MT_DEVICE,
285 },
286 {
287 .virtual = L4_PER2_DRA7XX_VIRT,
288 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
289 .length = L4_PER2_DRA7XX_SIZE,
290 .type = MT_DEVICE,
291 },
292 {
293 .virtual = L4_PER3_DRA7XX_VIRT,
294 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
295 .length = L4_PER3_DRA7XX_SIZE,
296 .type = MT_DEVICE,
297 },
298 {
299 .virtual = L4_CFG_DRA7XX_VIRT,
300 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
301 .length = L4_CFG_DRA7XX_SIZE,
302 .type = MT_DEVICE,
303 },
304 {
305 .virtual = L4_WKUP_DRA7XX_VIRT,
306 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
307 .length = L4_WKUP_DRA7XX_SIZE,
308 .type = MT_DEVICE,
309 },
310 };
311 #endif
312
313 #ifdef CONFIG_SOC_OMAP2420
omap242x_map_io(void)314 void __init omap242x_map_io(void)
315 {
316 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
317 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
318 }
319 #endif
320
321 #ifdef CONFIG_SOC_OMAP2430
omap243x_map_io(void)322 void __init omap243x_map_io(void)
323 {
324 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
325 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
326 }
327 #endif
328
329 #ifdef CONFIG_ARCH_OMAP3
omap3_map_io(void)330 void __init omap3_map_io(void)
331 {
332 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
333 }
334 #endif
335
336 #ifdef CONFIG_SOC_TI81XX
ti81xx_map_io(void)337 void __init ti81xx_map_io(void)
338 {
339 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
340 }
341 #endif
342
343 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
am33xx_map_io(void)344 void __init am33xx_map_io(void)
345 {
346 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
347 }
348 #endif
349
350 #ifdef CONFIG_ARCH_OMAP4
omap4_map_io(void)351 void __init omap4_map_io(void)
352 {
353 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
354 omap_barriers_init();
355 }
356 #endif
357
358 #ifdef CONFIG_SOC_OMAP5
omap5_map_io(void)359 void __init omap5_map_io(void)
360 {
361 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
362 omap_barriers_init();
363 }
364 #endif
365
366 #ifdef CONFIG_SOC_DRA7XX
dra7xx_map_io(void)367 void __init dra7xx_map_io(void)
368 {
369 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
370 omap_barriers_init();
371 }
372 #endif
373 /*
374 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
375 *
376 * Sets the CORE DPLL3 M2 divider to the same value that it's at
377 * currently. This has the effect of setting the SDRC SDRAM AC timing
378 * registers to the values currently defined by the kernel. Currently
379 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
380 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
381 * or passes along the return value of clk_set_rate().
382 */
_omap2_init_reprogram_sdrc(void)383 static int __init _omap2_init_reprogram_sdrc(void)
384 {
385 struct clk *dpll3_m2_ck;
386 int v = -EINVAL;
387 long rate;
388
389 if (!cpu_is_omap34xx())
390 return 0;
391
392 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
393 if (IS_ERR(dpll3_m2_ck))
394 return -EINVAL;
395
396 rate = clk_get_rate(dpll3_m2_ck);
397 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
398 v = clk_set_rate(dpll3_m2_ck, rate);
399 if (v)
400 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
401
402 clk_put(dpll3_m2_ck);
403
404 return v;
405 }
406
_set_hwmod_postsetup_state(struct omap_hwmod * oh,void * data)407 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
408 {
409 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
410 }
411
omap_hwmod_init_postsetup(void)412 static void __init __maybe_unused omap_hwmod_init_postsetup(void)
413 {
414 u8 postsetup_state;
415
416 /* Set the default postsetup state for all hwmods */
417 #ifdef CONFIG_PM
418 postsetup_state = _HWMOD_STATE_IDLE;
419 #else
420 postsetup_state = _HWMOD_STATE_ENABLED;
421 #endif
422 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
423 }
424
425 #ifdef CONFIG_SOC_OMAP2420
omap2420_init_early(void)426 void __init omap2420_init_early(void)
427 {
428 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
429 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
430 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
431 omap2_control_base_init();
432 omap2xxx_check_revision();
433 omap2_prcm_base_init();
434 omap2xxx_voltagedomains_init();
435 omap242x_powerdomains_init();
436 omap242x_clockdomains_init();
437 omap2420_hwmod_init();
438 omap_hwmod_init_postsetup();
439 omap_clk_soc_init = omap2420_dt_clk_init;
440 rate_table = omap2420_rate_table;
441 }
442
omap2420_init_late(void)443 void __init omap2420_init_late(void)
444 {
445 omap_pm_soc_init = omap2_pm_init;
446 }
447 #endif
448
449 #ifdef CONFIG_SOC_OMAP2430
omap2430_init_early(void)450 void __init omap2430_init_early(void)
451 {
452 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
453 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
454 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
455 omap2_control_base_init();
456 omap2xxx_check_revision();
457 omap2_prcm_base_init();
458 omap2xxx_voltagedomains_init();
459 omap243x_powerdomains_init();
460 omap243x_clockdomains_init();
461 omap2430_hwmod_init();
462 omap_hwmod_init_postsetup();
463 omap_clk_soc_init = omap2430_dt_clk_init;
464 rate_table = omap2430_rate_table;
465 }
466
omap2430_init_late(void)467 void __init omap2430_init_late(void)
468 {
469 omap_pm_soc_init = omap2_pm_init;
470 }
471 #endif
472
473 /*
474 * Currently only board-omap3beagle.c should call this because of the
475 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
476 */
477 #ifdef CONFIG_ARCH_OMAP3
omap3_init_early(void)478 void __init omap3_init_early(void)
479 {
480 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
481 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
482 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
483 omap2_control_base_init();
484 omap3xxx_check_revision();
485 omap3xxx_check_features();
486 omap2_prcm_base_init();
487 omap3xxx_voltagedomains_init();
488 omap3xxx_powerdomains_init();
489 omap3xxx_clockdomains_init();
490 omap3xxx_hwmod_init();
491 omap_hwmod_init_postsetup();
492 }
493
omap3430_init_early(void)494 void __init omap3430_init_early(void)
495 {
496 omap3_init_early();
497 omap_clk_soc_init = omap3430_dt_clk_init;
498 }
499
omap35xx_init_early(void)500 void __init omap35xx_init_early(void)
501 {
502 omap3_init_early();
503 omap_clk_soc_init = omap3430_dt_clk_init;
504 }
505
omap3630_init_early(void)506 void __init omap3630_init_early(void)
507 {
508 omap3_init_early();
509 omap_clk_soc_init = omap3630_dt_clk_init;
510 }
511
am35xx_init_early(void)512 void __init am35xx_init_early(void)
513 {
514 omap3_init_early();
515 omap_clk_soc_init = am35xx_dt_clk_init;
516 }
517
omap3_init_late(void)518 void __init omap3_init_late(void)
519 {
520 omap_pm_soc_init = omap3_pm_init;
521 }
522
ti81xx_init_late(void)523 void __init ti81xx_init_late(void)
524 {
525 omap_pm_soc_init = omap_pm_nop_init;
526 }
527 #endif
528
529 #ifdef CONFIG_SOC_TI81XX
ti814x_init_early(void)530 void __init ti814x_init_early(void)
531 {
532 omap2_set_globals_tap(TI814X_CLASS,
533 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
534 omap2_control_base_init();
535 omap3xxx_check_revision();
536 ti81xx_check_features();
537 omap2_prcm_base_init();
538 omap3xxx_voltagedomains_init();
539 omap3xxx_powerdomains_init();
540 ti814x_clockdomains_init();
541 dm814x_hwmod_init();
542 omap_hwmod_init_postsetup();
543 omap_clk_soc_init = dm814x_dt_clk_init;
544 }
545
ti816x_init_early(void)546 void __init ti816x_init_early(void)
547 {
548 omap2_set_globals_tap(TI816X_CLASS,
549 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
550 omap2_control_base_init();
551 omap3xxx_check_revision();
552 ti81xx_check_features();
553 omap2_prcm_base_init();
554 omap3xxx_voltagedomains_init();
555 omap3xxx_powerdomains_init();
556 ti816x_clockdomains_init();
557 dm816x_hwmod_init();
558 omap_hwmod_init_postsetup();
559 omap_clk_soc_init = dm816x_dt_clk_init;
560 }
561 #endif
562
563 #ifdef CONFIG_SOC_AM33XX
am33xx_init_early(void)564 void __init am33xx_init_early(void)
565 {
566 omap2_set_globals_tap(AM335X_CLASS,
567 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
568 omap2_control_base_init();
569 omap3xxx_check_revision();
570 am33xx_check_features();
571 omap2_prcm_base_init();
572 am33xx_powerdomains_init();
573 am33xx_clockdomains_init();
574 am33xx_hwmod_init();
575 omap_hwmod_init_postsetup();
576 omap_clk_soc_init = am33xx_dt_clk_init;
577 }
578
am33xx_init_late(void)579 void __init am33xx_init_late(void)
580 {
581 omap_pm_soc_init = amx3_common_pm_init;
582 }
583 #endif
584
585 #ifdef CONFIG_SOC_AM43XX
am43xx_init_early(void)586 void __init am43xx_init_early(void)
587 {
588 omap2_set_globals_tap(AM335X_CLASS,
589 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
590 omap2_control_base_init();
591 omap3xxx_check_revision();
592 am33xx_check_features();
593 omap2_prcm_base_init();
594 am43xx_powerdomains_init();
595 am43xx_clockdomains_init();
596 am43xx_hwmod_init();
597 omap_hwmod_init_postsetup();
598 omap_l2_cache_init();
599 omap_clk_soc_init = am43xx_dt_clk_init;
600 }
601
am43xx_init_late(void)602 void __init am43xx_init_late(void)
603 {
604 omap_pm_soc_init = amx3_common_pm_init;
605 }
606 #endif
607
608 #ifdef CONFIG_ARCH_OMAP4
omap4430_init_early(void)609 void __init omap4430_init_early(void)
610 {
611 omap2_set_globals_tap(OMAP443X_CLASS,
612 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
613 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
614 omap2_control_base_init();
615 omap4xxx_check_revision();
616 omap4xxx_check_features();
617 omap2_prcm_base_init();
618 omap4_sar_ram_init();
619 omap4_mpuss_early_init();
620 omap4_pm_init_early();
621 omap44xx_voltagedomains_init();
622 omap44xx_powerdomains_init();
623 omap44xx_clockdomains_init();
624 omap44xx_hwmod_init();
625 omap_hwmod_init_postsetup();
626 omap_l2_cache_init();
627 omap_clk_soc_init = omap4xxx_dt_clk_init;
628 }
629
omap4430_init_late(void)630 void __init omap4430_init_late(void)
631 {
632 omap_pm_soc_init = omap4_pm_init;
633 }
634 #endif
635
636 #ifdef CONFIG_SOC_OMAP5
omap5_init_early(void)637 void __init omap5_init_early(void)
638 {
639 omap2_set_globals_tap(OMAP54XX_CLASS,
640 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
641 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
642 omap2_control_base_init();
643 omap2_prcm_base_init();
644 omap5xxx_check_revision();
645 omap4_sar_ram_init();
646 omap4_mpuss_early_init();
647 omap4_pm_init_early();
648 omap54xx_voltagedomains_init();
649 omap54xx_powerdomains_init();
650 omap54xx_clockdomains_init();
651 omap54xx_hwmod_init();
652 omap_hwmod_init_postsetup();
653 omap_clk_soc_init = omap5xxx_dt_clk_init;
654 }
655
omap5_init_late(void)656 void __init omap5_init_late(void)
657 {
658 omap_pm_soc_init = omap4_pm_init;
659 }
660 #endif
661
662 #ifdef CONFIG_SOC_DRA7XX
dra7xx_init_early(void)663 void __init dra7xx_init_early(void)
664 {
665 omap2_set_globals_tap(DRA7XX_CLASS,
666 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
667 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
668 omap2_control_base_init();
669 omap4_pm_init_early();
670 omap2_prcm_base_init();
671 dra7xxx_check_revision();
672 dra7xx_powerdomains_init();
673 dra7xx_clockdomains_init();
674 dra7xx_hwmod_init();
675 omap_hwmod_init_postsetup();
676 omap_clk_soc_init = dra7xx_dt_clk_init;
677 }
678
dra7xx_init_late(void)679 void __init dra7xx_init_late(void)
680 {
681 omap_pm_soc_init = omap4_pm_init;
682 }
683 #endif
684
685
omap_sdrc_init(struct omap_sdrc_params * sdrc_cs0,struct omap_sdrc_params * sdrc_cs1)686 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
687 struct omap_sdrc_params *sdrc_cs1)
688 {
689 omap_sram_init();
690
691 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
692 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
693 _omap2_init_reprogram_sdrc();
694 }
695 }
696
omap_clk_init(void)697 int __init omap_clk_init(void)
698 {
699 int ret = 0;
700
701 if (!omap_clk_soc_init)
702 return 0;
703
704 ti_clk_init_features();
705
706 omap2_clk_setup_ll_ops();
707
708 ret = omap_control_init();
709 if (ret)
710 return ret;
711
712 ret = omap_prcm_init();
713 if (ret)
714 return ret;
715
716 of_clk_init(NULL);
717
718 ti_dt_clk_init_retry_clks();
719
720 ti_dt_clockdomains_setup();
721
722 ret = omap_clk_soc_init();
723
724 return ret;
725 }
726