1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/clk/tegra.h>
8 #include <linux/device.h>
9 #include <linux/host1x.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_graph.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16
17 #include <media/v4l2-fwnode.h>
18
19 #include "csi.h"
20 #include "video.h"
21
22 #define MHZ 1000000
23
24 static inline struct tegra_csi *
host1x_client_to_csi(struct host1x_client * client)25 host1x_client_to_csi(struct host1x_client *client)
26 {
27 return container_of(client, struct tegra_csi, client);
28 }
29
to_csi_chan(struct v4l2_subdev * subdev)30 static inline struct tegra_csi_channel *to_csi_chan(struct v4l2_subdev *subdev)
31 {
32 return container_of(subdev, struct tegra_csi_channel, subdev);
33 }
34
35 /*
36 * CSI is a separate subdevice which has 6 source pads to generate
37 * test pattern. CSI subdevice pad ops are used only for TPG and
38 * allows below TPG formats.
39 */
40 static const struct v4l2_mbus_framefmt tegra_csi_tpg_fmts[] = {
41 {
42 TEGRA_DEF_WIDTH,
43 TEGRA_DEF_HEIGHT,
44 MEDIA_BUS_FMT_SRGGB10_1X10,
45 V4L2_FIELD_NONE,
46 V4L2_COLORSPACE_SRGB
47 },
48 {
49 TEGRA_DEF_WIDTH,
50 TEGRA_DEF_HEIGHT,
51 MEDIA_BUS_FMT_RGB888_1X32_PADHI,
52 V4L2_FIELD_NONE,
53 V4L2_COLORSPACE_SRGB
54 },
55 };
56
57 static const struct v4l2_frmsize_discrete tegra_csi_tpg_sizes[] = {
58 { 1280, 720 },
59 { 1920, 1080 },
60 { 3840, 2160 },
61 };
62
63 /*
64 * V4L2 Subdevice Pad Operations
65 */
csi_enum_bus_code(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)66 static int csi_enum_bus_code(struct v4l2_subdev *subdev,
67 struct v4l2_subdev_pad_config *cfg,
68 struct v4l2_subdev_mbus_code_enum *code)
69 {
70 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
71 return -ENOIOCTLCMD;
72
73 if (code->index >= ARRAY_SIZE(tegra_csi_tpg_fmts))
74 return -EINVAL;
75
76 code->code = tegra_csi_tpg_fmts[code->index].code;
77
78 return 0;
79 }
80
csi_get_format(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)81 static int csi_get_format(struct v4l2_subdev *subdev,
82 struct v4l2_subdev_pad_config *cfg,
83 struct v4l2_subdev_format *fmt)
84 {
85 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev);
86
87 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
88 return -ENOIOCTLCMD;
89
90 fmt->format = csi_chan->format;
91
92 return 0;
93 }
94
csi_get_frmrate_table_index(struct tegra_csi * csi,u32 code,u32 width,u32 height)95 static int csi_get_frmrate_table_index(struct tegra_csi *csi, u32 code,
96 u32 width, u32 height)
97 {
98 const struct tpg_framerate *frmrate;
99 unsigned int i;
100
101 frmrate = csi->soc->tpg_frmrate_table;
102 for (i = 0; i < csi->soc->tpg_frmrate_table_size; i++) {
103 if (frmrate[i].code == code &&
104 frmrate[i].frmsize.width == width &&
105 frmrate[i].frmsize.height == height) {
106 return i;
107 }
108 }
109
110 return -EINVAL;
111 }
112
csi_chan_update_blank_intervals(struct tegra_csi_channel * csi_chan,u32 code,u32 width,u32 height)113 static void csi_chan_update_blank_intervals(struct tegra_csi_channel *csi_chan,
114 u32 code, u32 width, u32 height)
115 {
116 struct tegra_csi *csi = csi_chan->csi;
117 const struct tpg_framerate *frmrate = csi->soc->tpg_frmrate_table;
118 int index;
119
120 index = csi_get_frmrate_table_index(csi_chan->csi, code,
121 width, height);
122 if (index >= 0) {
123 csi_chan->h_blank = frmrate[index].h_blank;
124 csi_chan->v_blank = frmrate[index].v_blank;
125 csi_chan->framerate = frmrate[index].framerate;
126 }
127 }
128
csi_enum_framesizes(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)129 static int csi_enum_framesizes(struct v4l2_subdev *subdev,
130 struct v4l2_subdev_pad_config *cfg,
131 struct v4l2_subdev_frame_size_enum *fse)
132 {
133 unsigned int i;
134
135 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
136 return -ENOIOCTLCMD;
137
138 if (fse->index >= ARRAY_SIZE(tegra_csi_tpg_sizes))
139 return -EINVAL;
140
141 for (i = 0; i < ARRAY_SIZE(tegra_csi_tpg_fmts); i++)
142 if (fse->code == tegra_csi_tpg_fmts[i].code)
143 break;
144
145 if (i == ARRAY_SIZE(tegra_csi_tpg_fmts))
146 return -EINVAL;
147
148 fse->min_width = tegra_csi_tpg_sizes[fse->index].width;
149 fse->max_width = tegra_csi_tpg_sizes[fse->index].width;
150 fse->min_height = tegra_csi_tpg_sizes[fse->index].height;
151 fse->max_height = tegra_csi_tpg_sizes[fse->index].height;
152
153 return 0;
154 }
155
csi_enum_frameintervals(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)156 static int csi_enum_frameintervals(struct v4l2_subdev *subdev,
157 struct v4l2_subdev_pad_config *cfg,
158 struct v4l2_subdev_frame_interval_enum *fie)
159 {
160 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev);
161 struct tegra_csi *csi = csi_chan->csi;
162 const struct tpg_framerate *frmrate = csi->soc->tpg_frmrate_table;
163 int index;
164
165 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
166 return -ENOIOCTLCMD;
167
168 /* one framerate per format and resolution */
169 if (fie->index > 0)
170 return -EINVAL;
171
172 index = csi_get_frmrate_table_index(csi_chan->csi, fie->code,
173 fie->width, fie->height);
174 if (index < 0)
175 return -EINVAL;
176
177 fie->interval.numerator = 1;
178 fie->interval.denominator = frmrate[index].framerate;
179
180 return 0;
181 }
182
csi_set_format(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)183 static int csi_set_format(struct v4l2_subdev *subdev,
184 struct v4l2_subdev_pad_config *cfg,
185 struct v4l2_subdev_format *fmt)
186 {
187 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev);
188 struct v4l2_mbus_framefmt *format = &fmt->format;
189 const struct v4l2_frmsize_discrete *sizes;
190 unsigned int i;
191
192 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
193 return -ENOIOCTLCMD;
194
195 sizes = v4l2_find_nearest_size(tegra_csi_tpg_sizes,
196 ARRAY_SIZE(tegra_csi_tpg_sizes),
197 width, height,
198 format->width, format->width);
199 format->width = sizes->width;
200 format->height = sizes->height;
201
202 for (i = 0; i < ARRAY_SIZE(tegra_csi_tpg_fmts); i++)
203 if (format->code == tegra_csi_tpg_fmts[i].code)
204 break;
205
206 if (i == ARRAY_SIZE(tegra_csi_tpg_fmts))
207 i = 0;
208
209 format->code = tegra_csi_tpg_fmts[i].code;
210 format->field = V4L2_FIELD_NONE;
211
212 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
213 return 0;
214
215 /* update blanking intervals from frame rate table and format */
216 csi_chan_update_blank_intervals(csi_chan, format->code,
217 format->width, format->height);
218 csi_chan->format = *format;
219
220 return 0;
221 }
222
223 /*
224 * V4L2 Subdevice Video Operations
225 */
tegra_csi_g_frame_interval(struct v4l2_subdev * subdev,struct v4l2_subdev_frame_interval * vfi)226 static int tegra_csi_g_frame_interval(struct v4l2_subdev *subdev,
227 struct v4l2_subdev_frame_interval *vfi)
228 {
229 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev);
230
231 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
232 return -ENOIOCTLCMD;
233
234 vfi->interval.numerator = 1;
235 vfi->interval.denominator = csi_chan->framerate;
236
237 return 0;
238 }
239
csi_get_pixel_rate(struct tegra_csi_channel * csi_chan)240 static unsigned int csi_get_pixel_rate(struct tegra_csi_channel *csi_chan)
241 {
242 struct tegra_vi_channel *chan;
243 struct v4l2_subdev *src_subdev;
244 struct v4l2_ctrl *ctrl;
245
246 chan = v4l2_get_subdev_hostdata(&csi_chan->subdev);
247 src_subdev = tegra_channel_get_remote_source_subdev(chan);
248 ctrl = v4l2_ctrl_find(src_subdev->ctrl_handler, V4L2_CID_PIXEL_RATE);
249 if (ctrl)
250 return v4l2_ctrl_g_ctrl_int64(ctrl);
251
252 return 0;
253 }
254
tegra_csi_calc_settle_time(struct tegra_csi_channel * csi_chan,u8 * clk_settle_time,u8 * ths_settle_time)255 void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan,
256 u8 *clk_settle_time,
257 u8 *ths_settle_time)
258 {
259 struct tegra_csi *csi = csi_chan->csi;
260 unsigned int cil_clk_mhz;
261 unsigned int pix_clk_mhz;
262 int clk_idx = (csi_chan->csi_port_num >> 1) + 1;
263
264 cil_clk_mhz = clk_get_rate(csi->clks[clk_idx].clk) / MHZ;
265 pix_clk_mhz = csi_get_pixel_rate(csi_chan) / MHZ;
266
267 /*
268 * CLK Settle time is the interval during which HS receiver should
269 * ignore any clock lane HS transitions, starting from the beginning
270 * of T-CLK-PREPARE.
271 * Per DPHY specification, T-CLK-SETTLE should be between 95ns ~ 300ns
272 *
273 * 95ns < (clk-settle-programmed + 7) * lp clk period < 300ns
274 * midpoint = 197.5 ns
275 */
276 *clk_settle_time = ((95 + 300) * cil_clk_mhz - 14000) / 2000;
277
278 /*
279 * THS Settle time is the interval during which HS receiver should
280 * ignore any data lane HS transitions, starting from the beginning
281 * of THS-PREPARE.
282 *
283 * Per DPHY specification, T-HS-SETTLE should be between 85ns + 6UI
284 * and 145ns+10UI.
285 * 85ns + 6UI < (Ths-settle-prog + 5) * lp_clk_period < 145ns + 10UI
286 * midpoint = 115ns + 8UI
287 */
288 if (pix_clk_mhz)
289 *ths_settle_time = (115 * cil_clk_mhz + 8000 * cil_clk_mhz
290 / (2 * pix_clk_mhz) - 5000) / 1000;
291 }
292
tegra_csi_enable_stream(struct v4l2_subdev * subdev)293 static int tegra_csi_enable_stream(struct v4l2_subdev *subdev)
294 {
295 struct tegra_vi_channel *chan = v4l2_get_subdev_hostdata(subdev);
296 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev);
297 struct tegra_csi *csi = csi_chan->csi;
298 int ret, err;
299
300 ret = pm_runtime_get_sync(csi->dev);
301 if (ret < 0) {
302 dev_err(csi->dev, "failed to get runtime PM: %d\n", ret);
303 pm_runtime_put_noidle(csi->dev);
304 return ret;
305 }
306
307 if (csi_chan->mipi) {
308 ret = tegra_mipi_enable(csi_chan->mipi);
309 if (ret < 0) {
310 dev_err(csi->dev,
311 "failed to enable MIPI pads: %d\n", ret);
312 goto rpm_put;
313 }
314
315 /*
316 * CSI MIPI pads PULLUP, PULLDN and TERM impedances need to
317 * be calibrated after power on.
318 * So, trigger the calibration start here and results will
319 * be latched and applied to the pads when link is in LP11
320 * state during start of sensor streaming.
321 */
322 ret = tegra_mipi_start_calibration(csi_chan->mipi);
323 if (ret < 0) {
324 dev_err(csi->dev,
325 "failed to start MIPI calibration: %d\n", ret);
326 goto disable_mipi;
327 }
328 }
329
330 csi_chan->pg_mode = chan->pg_mode;
331 ret = csi->ops->csi_start_streaming(csi_chan);
332 if (ret < 0)
333 goto finish_calibration;
334
335 return 0;
336
337 finish_calibration:
338 if (csi_chan->mipi)
339 tegra_mipi_finish_calibration(csi_chan->mipi);
340 disable_mipi:
341 if (csi_chan->mipi) {
342 err = tegra_mipi_disable(csi_chan->mipi);
343 if (err < 0)
344 dev_err(csi->dev,
345 "failed to disable MIPI pads: %d\n", err);
346 }
347
348 rpm_put:
349 pm_runtime_put(csi->dev);
350 return ret;
351 }
352
tegra_csi_disable_stream(struct v4l2_subdev * subdev)353 static int tegra_csi_disable_stream(struct v4l2_subdev *subdev)
354 {
355 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev);
356 struct tegra_csi *csi = csi_chan->csi;
357 int err;
358
359 csi->ops->csi_stop_streaming(csi_chan);
360
361 if (csi_chan->mipi) {
362 err = tegra_mipi_disable(csi_chan->mipi);
363 if (err < 0)
364 dev_err(csi->dev,
365 "failed to disable MIPI pads: %d\n", err);
366 }
367
368 pm_runtime_put(csi->dev);
369
370 return 0;
371 }
372
tegra_csi_s_stream(struct v4l2_subdev * subdev,int enable)373 static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable)
374 {
375 int ret;
376
377 if (enable)
378 ret = tegra_csi_enable_stream(subdev);
379 else
380 ret = tegra_csi_disable_stream(subdev);
381
382 return ret;
383 }
384
385 /*
386 * V4L2 Subdevice Operations
387 */
388 static const struct v4l2_subdev_video_ops tegra_csi_video_ops = {
389 .s_stream = tegra_csi_s_stream,
390 .g_frame_interval = tegra_csi_g_frame_interval,
391 .s_frame_interval = tegra_csi_g_frame_interval,
392 };
393
394 static const struct v4l2_subdev_pad_ops tegra_csi_pad_ops = {
395 .enum_mbus_code = csi_enum_bus_code,
396 .enum_frame_size = csi_enum_framesizes,
397 .enum_frame_interval = csi_enum_frameintervals,
398 .get_fmt = csi_get_format,
399 .set_fmt = csi_set_format,
400 };
401
402 static const struct v4l2_subdev_ops tegra_csi_ops = {
403 .video = &tegra_csi_video_ops,
404 .pad = &tegra_csi_pad_ops,
405 };
406
tegra_csi_channel_alloc(struct tegra_csi * csi,struct device_node * node,unsigned int port_num,unsigned int lanes,unsigned int num_pads)407 static int tegra_csi_channel_alloc(struct tegra_csi *csi,
408 struct device_node *node,
409 unsigned int port_num, unsigned int lanes,
410 unsigned int num_pads)
411 {
412 struct tegra_csi_channel *chan;
413 int ret = 0;
414
415 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
416 if (!chan)
417 return -ENOMEM;
418
419 list_add_tail(&chan->list, &csi->csi_chans);
420 chan->csi = csi;
421 chan->csi_port_num = port_num;
422 chan->numlanes = lanes;
423 chan->of_node = node;
424 chan->numpads = num_pads;
425 if (num_pads & 0x2) {
426 chan->pads[0].flags = MEDIA_PAD_FL_SINK;
427 chan->pads[1].flags = MEDIA_PAD_FL_SOURCE;
428 } else {
429 chan->pads[0].flags = MEDIA_PAD_FL_SOURCE;
430 }
431
432 if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
433 return 0;
434
435 chan->mipi = tegra_mipi_request(csi->dev, node);
436 if (IS_ERR(chan->mipi)) {
437 ret = PTR_ERR(chan->mipi);
438 dev_err(csi->dev, "failed to get mipi device: %d\n", ret);
439 }
440
441 return ret;
442 }
443
tegra_csi_tpg_channels_alloc(struct tegra_csi * csi)444 static int tegra_csi_tpg_channels_alloc(struct tegra_csi *csi)
445 {
446 struct device_node *node = csi->dev->of_node;
447 unsigned int port_num;
448 unsigned int tpg_channels = csi->soc->csi_max_channels;
449 int ret;
450
451 /* allocate CSI channel for each CSI x2 ports */
452 for (port_num = 0; port_num < tpg_channels; port_num++) {
453 ret = tegra_csi_channel_alloc(csi, node, port_num, 2, 1);
454 if (ret < 0)
455 return ret;
456 }
457
458 return 0;
459 }
460
tegra_csi_channels_alloc(struct tegra_csi * csi)461 static int tegra_csi_channels_alloc(struct tegra_csi *csi)
462 {
463 struct device_node *node = csi->dev->of_node;
464 struct v4l2_fwnode_endpoint v4l2_ep = {
465 .bus_type = V4L2_MBUS_CSI2_DPHY
466 };
467 struct fwnode_handle *fwh;
468 struct device_node *channel;
469 struct device_node *ep;
470 unsigned int lanes, portno, num_pads;
471 int ret;
472
473 for_each_child_of_node(node, channel) {
474 if (!of_node_name_eq(channel, "channel"))
475 continue;
476
477 ret = of_property_read_u32(channel, "reg", &portno);
478 if (ret < 0)
479 continue;
480
481 if (portno >= csi->soc->csi_max_channels) {
482 dev_err(csi->dev, "invalid port num %d for %pOF\n",
483 portno, channel);
484 ret = -EINVAL;
485 goto err_node_put;
486 }
487
488 ep = of_graph_get_endpoint_by_regs(channel, 0, 0);
489 if (!ep)
490 continue;
491
492 fwh = of_fwnode_handle(ep);
493 ret = v4l2_fwnode_endpoint_parse(fwh, &v4l2_ep);
494 of_node_put(ep);
495 if (ret) {
496 dev_err(csi->dev,
497 "failed to parse v4l2 endpoint for %pOF: %d\n",
498 channel, ret);
499 goto err_node_put;
500 }
501
502 lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes;
503 if (!lanes || ((lanes & (lanes - 1)) != 0)) {
504 dev_err(csi->dev, "invalid data-lanes %d for %pOF\n",
505 lanes, channel);
506 ret = -EINVAL;
507 goto err_node_put;
508 }
509
510 num_pads = of_graph_get_endpoint_count(channel);
511 if (num_pads == TEGRA_CSI_PADS_NUM) {
512 ret = tegra_csi_channel_alloc(csi, channel, portno,
513 lanes, num_pads);
514 if (ret < 0)
515 goto err_node_put;
516 }
517 }
518
519 return 0;
520
521 err_node_put:
522 of_node_put(channel);
523 return ret;
524 }
525
tegra_csi_channel_init(struct tegra_csi_channel * chan)526 static int tegra_csi_channel_init(struct tegra_csi_channel *chan)
527 {
528 struct tegra_csi *csi = chan->csi;
529 struct v4l2_subdev *subdev;
530 int ret;
531
532 /* initialize the default format */
533 chan->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
534 chan->format.field = V4L2_FIELD_NONE;
535 chan->format.colorspace = V4L2_COLORSPACE_SRGB;
536 chan->format.width = TEGRA_DEF_WIDTH;
537 chan->format.height = TEGRA_DEF_HEIGHT;
538 csi_chan_update_blank_intervals(chan, chan->format.code,
539 chan->format.width,
540 chan->format.height);
541 /* initialize V4L2 subdevice and media entity */
542 subdev = &chan->subdev;
543 v4l2_subdev_init(subdev, &tegra_csi_ops);
544 subdev->dev = csi->dev;
545 if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
546 snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s-%d", "tpg",
547 chan->csi_port_num);
548 else
549 snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s",
550 kbasename(chan->of_node->full_name));
551
552 v4l2_set_subdevdata(subdev, chan);
553 subdev->fwnode = of_fwnode_handle(chan->of_node);
554 subdev->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
555
556 /* initialize media entity pads */
557 ret = media_entity_pads_init(&subdev->entity, chan->numpads,
558 chan->pads);
559 if (ret < 0) {
560 dev_err(csi->dev,
561 "failed to initialize media entity: %d\n", ret);
562 subdev->dev = NULL;
563 return ret;
564 }
565
566 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) {
567 ret = v4l2_async_register_subdev(subdev);
568 if (ret < 0) {
569 dev_err(csi->dev,
570 "failed to register subdev: %d\n", ret);
571 return ret;
572 }
573 }
574
575 return 0;
576 }
577
tegra_csi_error_recover(struct v4l2_subdev * sd)578 void tegra_csi_error_recover(struct v4l2_subdev *sd)
579 {
580 struct tegra_csi_channel *csi_chan = to_csi_chan(sd);
581 struct tegra_csi *csi = csi_chan->csi;
582
583 /* stop streaming during error recovery */
584 csi->ops->csi_stop_streaming(csi_chan);
585 csi->ops->csi_err_recover(csi_chan);
586 csi->ops->csi_start_streaming(csi_chan);
587 }
588
tegra_csi_channels_init(struct tegra_csi * csi)589 static int tegra_csi_channels_init(struct tegra_csi *csi)
590 {
591 struct tegra_csi_channel *chan;
592 int ret;
593
594 list_for_each_entry(chan, &csi->csi_chans, list) {
595 ret = tegra_csi_channel_init(chan);
596 if (ret) {
597 dev_err(csi->dev,
598 "failed to initialize channel-%d: %d\n",
599 chan->csi_port_num, ret);
600 return ret;
601 }
602 }
603
604 return 0;
605 }
606
tegra_csi_channels_cleanup(struct tegra_csi * csi)607 static void tegra_csi_channels_cleanup(struct tegra_csi *csi)
608 {
609 struct v4l2_subdev *subdev;
610 struct tegra_csi_channel *chan, *tmp;
611
612 list_for_each_entry_safe(chan, tmp, &csi->csi_chans, list) {
613 if (chan->mipi)
614 tegra_mipi_free(chan->mipi);
615
616 subdev = &chan->subdev;
617 if (subdev->dev) {
618 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
619 v4l2_async_unregister_subdev(subdev);
620 media_entity_cleanup(&subdev->entity);
621 }
622
623 list_del(&chan->list);
624 kfree(chan);
625 }
626 }
627
csi_runtime_suspend(struct device * dev)628 static int __maybe_unused csi_runtime_suspend(struct device *dev)
629 {
630 struct tegra_csi *csi = dev_get_drvdata(dev);
631
632 clk_bulk_disable_unprepare(csi->soc->num_clks, csi->clks);
633
634 return 0;
635 }
636
csi_runtime_resume(struct device * dev)637 static int __maybe_unused csi_runtime_resume(struct device *dev)
638 {
639 struct tegra_csi *csi = dev_get_drvdata(dev);
640 int ret;
641
642 ret = clk_bulk_prepare_enable(csi->soc->num_clks, csi->clks);
643 if (ret < 0) {
644 dev_err(csi->dev, "failed to enable clocks: %d\n", ret);
645 return ret;
646 }
647
648 return 0;
649 }
650
tegra_csi_init(struct host1x_client * client)651 static int tegra_csi_init(struct host1x_client *client)
652 {
653 struct tegra_csi *csi = host1x_client_to_csi(client);
654 struct tegra_video_device *vid = dev_get_drvdata(client->host);
655 int ret;
656
657 INIT_LIST_HEAD(&csi->csi_chans);
658
659 if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG))
660 ret = tegra_csi_tpg_channels_alloc(csi);
661 else
662 ret = tegra_csi_channels_alloc(csi);
663 if (ret < 0) {
664 dev_err(csi->dev,
665 "failed to allocate channels: %d\n", ret);
666 goto cleanup;
667 }
668
669 ret = tegra_csi_channels_init(csi);
670 if (ret < 0)
671 goto cleanup;
672
673 vid->csi = csi;
674
675 return 0;
676
677 cleanup:
678 tegra_csi_channels_cleanup(csi);
679 return ret;
680 }
681
tegra_csi_exit(struct host1x_client * client)682 static int tegra_csi_exit(struct host1x_client *client)
683 {
684 struct tegra_csi *csi = host1x_client_to_csi(client);
685
686 tegra_csi_channels_cleanup(csi);
687
688 return 0;
689 }
690
691 static const struct host1x_client_ops csi_client_ops = {
692 .init = tegra_csi_init,
693 .exit = tegra_csi_exit,
694 };
695
tegra_csi_probe(struct platform_device * pdev)696 static int tegra_csi_probe(struct platform_device *pdev)
697 {
698 struct tegra_csi *csi;
699 unsigned int i;
700 int ret;
701
702 csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL);
703 if (!csi)
704 return -ENOMEM;
705
706 csi->iomem = devm_platform_ioremap_resource(pdev, 0);
707 if (IS_ERR(csi->iomem))
708 return PTR_ERR(csi->iomem);
709
710 csi->soc = of_device_get_match_data(&pdev->dev);
711
712 csi->clks = devm_kcalloc(&pdev->dev, csi->soc->num_clks,
713 sizeof(*csi->clks), GFP_KERNEL);
714 if (!csi->clks)
715 return -ENOMEM;
716
717 for (i = 0; i < csi->soc->num_clks; i++)
718 csi->clks[i].id = csi->soc->clk_names[i];
719
720 ret = devm_clk_bulk_get(&pdev->dev, csi->soc->num_clks, csi->clks);
721 if (ret) {
722 dev_err(&pdev->dev, "failed to get the clocks: %d\n", ret);
723 return ret;
724 }
725
726 if (!pdev->dev.pm_domain) {
727 ret = -ENOENT;
728 dev_warn(&pdev->dev, "PM domain is not attached: %d\n", ret);
729 return ret;
730 }
731
732 csi->dev = &pdev->dev;
733 csi->ops = csi->soc->ops;
734 platform_set_drvdata(pdev, csi);
735 pm_runtime_enable(&pdev->dev);
736
737 /* initialize host1x interface */
738 INIT_LIST_HEAD(&csi->client.list);
739 csi->client.ops = &csi_client_ops;
740 csi->client.dev = &pdev->dev;
741
742 ret = host1x_client_register(&csi->client);
743 if (ret < 0) {
744 dev_err(&pdev->dev,
745 "failed to register host1x client: %d\n", ret);
746 goto rpm_disable;
747 }
748
749 return 0;
750
751 rpm_disable:
752 pm_runtime_disable(&pdev->dev);
753 return ret;
754 }
755
tegra_csi_remove(struct platform_device * pdev)756 static int tegra_csi_remove(struct platform_device *pdev)
757 {
758 struct tegra_csi *csi = platform_get_drvdata(pdev);
759 int err;
760
761 err = host1x_client_unregister(&csi->client);
762 if (err < 0) {
763 dev_err(&pdev->dev,
764 "failed to unregister host1x client: %d\n", err);
765 return err;
766 }
767
768 pm_runtime_disable(&pdev->dev);
769
770 return 0;
771 }
772
773 static const struct of_device_id tegra_csi_of_id_table[] = {
774 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
775 { .compatible = "nvidia,tegra210-csi", .data = &tegra210_csi_soc },
776 #endif
777 { }
778 };
779 MODULE_DEVICE_TABLE(of, tegra_csi_of_id_table);
780
781 static const struct dev_pm_ops tegra_csi_pm_ops = {
782 SET_RUNTIME_PM_OPS(csi_runtime_suspend, csi_runtime_resume, NULL)
783 };
784
785 struct platform_driver tegra_csi_driver = {
786 .driver = {
787 .name = "tegra-csi",
788 .of_match_table = tegra_csi_of_id_table,
789 .pm = &tegra_csi_pm_ops,
790 },
791 .probe = tegra_csi_probe,
792 .remove = tegra_csi_remove,
793 };
794
