1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * CPU idle driver for Tegra CPUs
4 *
5 * Copyright (c) 2010-2012, NVIDIA Corporation.
6 * Copyright (c) 2011 Google, Inc.
7 * Author: Colin Cross <ccross@android.com>
8 * Gary King <gking@nvidia.com>
9 *
10 * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
11 */
12
13 #include <linux/clk/tegra.h>
14 #include <linux/tick.h>
15 #include <linux/cpuidle.h>
16 #include <linux/cpu_pm.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19
20 #include <soc/tegra/flowctrl.h>
21
22 #include <asm/cpuidle.h>
23 #include <asm/smp_plat.h>
24 #include <asm/suspend.h>
25
26 #include "cpuidle.h"
27 #include "iomap.h"
28 #include "irq.h"
29 #include "pm.h"
30 #include "reset.h"
31 #include "sleep.h"
32
33 #ifdef CONFIG_PM_SLEEP
34 static bool abort_flag;
35 static atomic_t abort_barrier;
36 static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
37 struct cpuidle_driver *drv,
38 int index);
39 #define TEGRA20_MAX_STATES 2
40 #else
41 #define TEGRA20_MAX_STATES 1
42 #endif
43
44 static struct cpuidle_driver tegra_idle_driver = {
45 .name = "tegra_idle",
46 .owner = THIS_MODULE,
47 .states = {
48 ARM_CPUIDLE_WFI_STATE_PWR(600),
49 #ifdef CONFIG_PM_SLEEP
50 {
51 .enter = tegra20_idle_lp2_coupled,
52 .exit_latency = 5000,
53 .target_residency = 10000,
54 .power_usage = 0,
55 .flags = CPUIDLE_FLAG_COUPLED |
56 CPUIDLE_FLAG_TIMER_STOP,
57 .name = "powered-down",
58 .desc = "CPU power gated",
59 },
60 #endif
61 },
62 .state_count = TEGRA20_MAX_STATES,
63 .safe_state_index = 0,
64 };
65
66 #ifdef CONFIG_PM_SLEEP
67 #ifdef CONFIG_SMP
tegra20_reset_sleeping_cpu_1(void)68 static int tegra20_reset_sleeping_cpu_1(void)
69 {
70 int ret = 0;
71
72 tegra_pen_lock();
73
74 if (readb(tegra20_cpu1_resettable_status) == CPU_RESETTABLE)
75 tegra20_cpu_shutdown(1);
76 else
77 ret = -EINVAL;
78
79 tegra_pen_unlock();
80
81 return ret;
82 }
83
tegra20_wake_cpu1_from_reset(void)84 static void tegra20_wake_cpu1_from_reset(void)
85 {
86 tegra_pen_lock();
87
88 tegra20_cpu_clear_resettable();
89
90 /* enable cpu clock on cpu */
91 tegra_enable_cpu_clock(1);
92
93 /* take the CPU out of reset */
94 tegra_cpu_out_of_reset(1);
95
96 /* unhalt the cpu */
97 flowctrl_write_cpu_halt(1, 0);
98
99 tegra_pen_unlock();
100 }
101
tegra20_reset_cpu_1(void)102 static int tegra20_reset_cpu_1(void)
103 {
104 if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1())
105 return 0;
106
107 tegra20_wake_cpu1_from_reset();
108 return -EBUSY;
109 }
110 #else
tegra20_wake_cpu1_from_reset(void)111 static inline void tegra20_wake_cpu1_from_reset(void)
112 {
113 }
114
tegra20_reset_cpu_1(void)115 static inline int tegra20_reset_cpu_1(void)
116 {
117 return 0;
118 }
119 #endif
120
tegra20_cpu_cluster_power_down(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)121 static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
122 struct cpuidle_driver *drv,
123 int index)
124 {
125 while (tegra20_cpu_is_resettable_soon())
126 cpu_relax();
127
128 if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready())
129 return false;
130
131 tegra_idle_lp2_last();
132
133 if (cpu_online(1))
134 tegra20_wake_cpu1_from_reset();
135
136 return true;
137 }
138
139 #ifdef CONFIG_SMP
tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)140 static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
141 struct cpuidle_driver *drv,
142 int index)
143 {
144 cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
145
146 tegra20_cpu_clear_resettable();
147
148 return true;
149 }
150 #else
tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)151 static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
152 struct cpuidle_driver *drv,
153 int index)
154 {
155 return true;
156 }
157 #endif
158
tegra20_idle_lp2_coupled(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)159 static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
160 struct cpuidle_driver *drv,
161 int index)
162 {
163 bool entered_lp2 = false;
164
165 if (tegra_pending_sgi())
166 WRITE_ONCE(abort_flag, true);
167
168 cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
169
170 if (abort_flag) {
171 cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
172 abort_flag = false; /* clean flag for next coming */
173 return -EINTR;
174 }
175
176 local_fiq_disable();
177
178 tegra_set_cpu_in_lp2();
179 cpu_pm_enter();
180
181 if (dev->cpu == 0)
182 entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
183 else
184 entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
185
186 cpu_pm_exit();
187 tegra_clear_cpu_in_lp2();
188
189 local_fiq_enable();
190
191 smp_rmb();
192
193 return entered_lp2 ? index : 0;
194 }
195 #endif
196
197 /*
198 * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
199 * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
200 * this, simply disable LP2 if the PCI driver and DT node are both enabled.
201 */
tegra20_cpuidle_pcie_irqs_in_use(void)202 void tegra20_cpuidle_pcie_irqs_in_use(void)
203 {
204 pr_info_once(
205 "Disabling cpuidle LP2 state, since PCIe IRQs are in use\n");
206 tegra_idle_driver.states[1].disabled = true;
207 }
208
tegra20_cpuidle_init(void)209 int __init tegra20_cpuidle_init(void)
210 {
211 return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
212 }
213
