1 /*
2 * VGICv3 MMIO handling functions
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/irqchip/arm-gic-v3.h>
15 #include <linux/kvm.h>
16 #include <linux/kvm_host.h>
17 #include <kvm/iodev.h>
18 #include <kvm/arm_vgic.h>
19
20 #include <asm/kvm_emulate.h>
21 #include <asm/kvm_arm.h>
22 #include <asm/kvm_mmu.h>
23
24 #include "vgic.h"
25 #include "vgic-mmio.h"
26
27 /* extract @num bytes at @offset bytes offset in data */
extract_bytes(u64 data,unsigned int offset,unsigned int num)28 unsigned long extract_bytes(u64 data, unsigned int offset,
29 unsigned int num)
30 {
31 return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
32 }
33
34 /* allows updates of any half of a 64-bit register (or the whole thing) */
update_64bit_reg(u64 reg,unsigned int offset,unsigned int len,unsigned long val)35 u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
36 unsigned long val)
37 {
38 int lower = (offset & 4) * 8;
39 int upper = lower + 8 * len - 1;
40
41 reg &= ~GENMASK_ULL(upper, lower);
42 val &= GENMASK_ULL(len * 8 - 1, 0);
43
44 return reg | ((u64)val << lower);
45 }
46
vgic_has_its(struct kvm * kvm)47 bool vgic_has_its(struct kvm *kvm)
48 {
49 struct vgic_dist *dist = &kvm->arch.vgic;
50
51 if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
52 return false;
53
54 return dist->has_its;
55 }
56
vgic_supports_direct_msis(struct kvm * kvm)57 bool vgic_supports_direct_msis(struct kvm *kvm)
58 {
59 return kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm);
60 }
61
62 /*
63 * The Revision field in the IIDR have the following meanings:
64 *
65 * Revision 2: Interrupt groups are guest-configurable and signaled using
66 * their configured groups.
67 */
68
vgic_mmio_read_v3_misc(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len)69 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
70 gpa_t addr, unsigned int len)
71 {
72 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
73 u32 value = 0;
74
75 switch (addr & 0x0c) {
76 case GICD_CTLR:
77 if (vgic->enabled)
78 value |= GICD_CTLR_ENABLE_SS_G1;
79 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
80 break;
81 case GICD_TYPER:
82 value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
83 value = (value >> 5) - 1;
84 if (vgic_has_its(vcpu->kvm)) {
85 value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;
86 value |= GICD_TYPER_LPIS;
87 } else {
88 value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
89 }
90 break;
91 case GICD_IIDR:
92 value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
93 (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
94 (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT);
95 break;
96 default:
97 return 0;
98 }
99
100 return value;
101 }
102
vgic_mmio_write_v3_misc(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len,unsigned long val)103 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
104 gpa_t addr, unsigned int len,
105 unsigned long val)
106 {
107 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
108 bool was_enabled = dist->enabled;
109
110 switch (addr & 0x0c) {
111 case GICD_CTLR:
112 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
113
114 if (!was_enabled && dist->enabled)
115 vgic_kick_vcpus(vcpu->kvm);
116 break;
117 case GICD_TYPER:
118 case GICD_IIDR:
119 return;
120 }
121 }
122
vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len,unsigned long val)123 static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu,
124 gpa_t addr, unsigned int len,
125 unsigned long val)
126 {
127 switch (addr & 0x0c) {
128 case GICD_IIDR:
129 if (val != vgic_mmio_read_v3_misc(vcpu, addr, len))
130 return -EINVAL;
131 }
132
133 vgic_mmio_write_v3_misc(vcpu, addr, len, val);
134 return 0;
135 }
136
vgic_mmio_read_irouter(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len)137 static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
138 gpa_t addr, unsigned int len)
139 {
140 int intid = VGIC_ADDR_TO_INTID(addr, 64);
141 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
142 unsigned long ret = 0;
143
144 if (!irq)
145 return 0;
146
147 /* The upper word is RAZ for us. */
148 if (!(addr & 4))
149 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
150
151 vgic_put_irq(vcpu->kvm, irq);
152 return ret;
153 }
154
vgic_mmio_write_irouter(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len,unsigned long val)155 static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
156 gpa_t addr, unsigned int len,
157 unsigned long val)
158 {
159 int intid = VGIC_ADDR_TO_INTID(addr, 64);
160 struct vgic_irq *irq;
161 unsigned long flags;
162
163 /* The upper word is WI for us since we don't implement Aff3. */
164 if (addr & 4)
165 return;
166
167 irq = vgic_get_irq(vcpu->kvm, NULL, intid);
168
169 if (!irq)
170 return;
171
172 spin_lock_irqsave(&irq->irq_lock, flags);
173
174 /* We only care about and preserve Aff0, Aff1 and Aff2. */
175 irq->mpidr = val & GENMASK(23, 0);
176 irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
177
178 spin_unlock_irqrestore(&irq->irq_lock, flags);
179 vgic_put_irq(vcpu->kvm, irq);
180 }
181
vgic_mmio_read_v3r_ctlr(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len)182 static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu,
183 gpa_t addr, unsigned int len)
184 {
185 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
186
187 return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0;
188 }
189
190
vgic_mmio_write_v3r_ctlr(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len,unsigned long val)191 static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
192 gpa_t addr, unsigned int len,
193 unsigned long val)
194 {
195 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
196 bool was_enabled = vgic_cpu->lpis_enabled;
197
198 if (!vgic_has_its(vcpu->kvm))
199 return;
200
201 vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;
202
203 if (!was_enabled && vgic_cpu->lpis_enabled)
204 vgic_enable_lpis(vcpu);
205 }
206
vgic_mmio_read_v3r_typer(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len)207 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
208 gpa_t addr, unsigned int len)
209 {
210 unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
211 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
212 struct vgic_redist_region *rdreg = vgic_cpu->rdreg;
213 int target_vcpu_id = vcpu->vcpu_id;
214 gpa_t last_rdist_typer = rdreg->base + GICR_TYPER +
215 (rdreg->free_index - 1) * KVM_VGIC_V3_REDIST_SIZE;
216 u64 value;
217
218 value = (u64)(mpidr & GENMASK(23, 0)) << 32;
219 value |= ((target_vcpu_id & 0xffff) << 8);
220
221 if (addr == last_rdist_typer)
222 value |= GICR_TYPER_LAST;
223 if (vgic_has_its(vcpu->kvm))
224 value |= GICR_TYPER_PLPIS;
225
226 return extract_bytes(value, addr & 7, len);
227 }
228
vgic_mmio_read_v3r_iidr(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len)229 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
230 gpa_t addr, unsigned int len)
231 {
232 return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
233 }
234
vgic_mmio_read_v3_idregs(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len)235 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
236 gpa_t addr, unsigned int len)
237 {
238 switch (addr & 0xffff) {
239 case GICD_PIDR2:
240 /* report a GICv3 compliant implementation */
241 return 0x3b;
242 }
243
244 return 0;
245 }
246
vgic_v3_uaccess_read_pending(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len)247 static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
248 gpa_t addr, unsigned int len)
249 {
250 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
251 u32 value = 0;
252 int i;
253
254 /*
255 * pending state of interrupt is latched in pending_latch variable.
256 * Userspace will save and restore pending state and line_level
257 * separately.
258 * Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
259 * for handling of ISPENDR and ICPENDR.
260 */
261 for (i = 0; i < len * 8; i++) {
262 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
263
264 if (irq->pending_latch)
265 value |= (1U << i);
266
267 vgic_put_irq(vcpu->kvm, irq);
268 }
269
270 return value;
271 }
272
vgic_v3_uaccess_write_pending(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len,unsigned long val)273 static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
274 gpa_t addr, unsigned int len,
275 unsigned long val)
276 {
277 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
278 int i;
279 unsigned long flags;
280
281 for (i = 0; i < len * 8; i++) {
282 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
283
284 spin_lock_irqsave(&irq->irq_lock, flags);
285 if (test_bit(i, &val)) {
286 /*
287 * pending_latch is set irrespective of irq type
288 * (level or edge) to avoid dependency that VM should
289 * restore irq config before pending info.
290 */
291 irq->pending_latch = true;
292 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
293 } else {
294 irq->pending_latch = false;
295 spin_unlock_irqrestore(&irq->irq_lock, flags);
296 }
297
298 vgic_put_irq(vcpu->kvm, irq);
299 }
300
301 return 0;
302 }
303
304 /* We want to avoid outer shareable. */
vgic_sanitise_shareability(u64 field)305 u64 vgic_sanitise_shareability(u64 field)
306 {
307 switch (field) {
308 case GIC_BASER_OuterShareable:
309 return GIC_BASER_InnerShareable;
310 default:
311 return field;
312 }
313 }
314
315 /* Avoid any inner non-cacheable mapping. */
vgic_sanitise_inner_cacheability(u64 field)316 u64 vgic_sanitise_inner_cacheability(u64 field)
317 {
318 switch (field) {
319 case GIC_BASER_CACHE_nCnB:
320 case GIC_BASER_CACHE_nC:
321 return GIC_BASER_CACHE_RaWb;
322 default:
323 return field;
324 }
325 }
326
327 /* Non-cacheable or same-as-inner are OK. */
vgic_sanitise_outer_cacheability(u64 field)328 u64 vgic_sanitise_outer_cacheability(u64 field)
329 {
330 switch (field) {
331 case GIC_BASER_CACHE_SameAsInner:
332 case GIC_BASER_CACHE_nC:
333 return field;
334 default:
335 return GIC_BASER_CACHE_nC;
336 }
337 }
338
vgic_sanitise_field(u64 reg,u64 field_mask,int field_shift,u64 (* sanitise_fn)(u64))339 u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
340 u64 (*sanitise_fn)(u64))
341 {
342 u64 field = (reg & field_mask) >> field_shift;
343
344 field = sanitise_fn(field) << field_shift;
345 return (reg & ~field_mask) | field;
346 }
347
348 #define PROPBASER_RES0_MASK \
349 (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))
350 #define PENDBASER_RES0_MASK \
351 (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \
352 GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))
353
vgic_sanitise_pendbaser(u64 reg)354 static u64 vgic_sanitise_pendbaser(u64 reg)
355 {
356 reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
357 GICR_PENDBASER_SHAREABILITY_SHIFT,
358 vgic_sanitise_shareability);
359 reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
360 GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
361 vgic_sanitise_inner_cacheability);
362 reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
363 GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
364 vgic_sanitise_outer_cacheability);
365
366 reg &= ~PENDBASER_RES0_MASK;
367 reg &= ~GENMASK_ULL(51, 48);
368
369 return reg;
370 }
371
vgic_sanitise_propbaser(u64 reg)372 static u64 vgic_sanitise_propbaser(u64 reg)
373 {
374 reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
375 GICR_PROPBASER_SHAREABILITY_SHIFT,
376 vgic_sanitise_shareability);
377 reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
378 GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
379 vgic_sanitise_inner_cacheability);
380 reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
381 GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
382 vgic_sanitise_outer_cacheability);
383
384 reg &= ~PROPBASER_RES0_MASK;
385 reg &= ~GENMASK_ULL(51, 48);
386 return reg;
387 }
388
vgic_mmio_read_propbase(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len)389 static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu,
390 gpa_t addr, unsigned int len)
391 {
392 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
393
394 return extract_bytes(dist->propbaser, addr & 7, len);
395 }
396
vgic_mmio_write_propbase(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len,unsigned long val)397 static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu,
398 gpa_t addr, unsigned int len,
399 unsigned long val)
400 {
401 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
402 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
403 u64 old_propbaser, propbaser;
404
405 /* Storing a value with LPIs already enabled is undefined */
406 if (vgic_cpu->lpis_enabled)
407 return;
408
409 do {
410 old_propbaser = READ_ONCE(dist->propbaser);
411 propbaser = old_propbaser;
412 propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
413 propbaser = vgic_sanitise_propbaser(propbaser);
414 } while (cmpxchg64(&dist->propbaser, old_propbaser,
415 propbaser) != old_propbaser);
416 }
417
vgic_mmio_read_pendbase(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len)418 static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
419 gpa_t addr, unsigned int len)
420 {
421 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
422
423 return extract_bytes(vgic_cpu->pendbaser, addr & 7, len);
424 }
425
vgic_mmio_write_pendbase(struct kvm_vcpu * vcpu,gpa_t addr,unsigned int len,unsigned long val)426 static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
427 gpa_t addr, unsigned int len,
428 unsigned long val)
429 {
430 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
431 u64 old_pendbaser, pendbaser;
432
433 /* Storing a value with LPIs already enabled is undefined */
434 if (vgic_cpu->lpis_enabled)
435 return;
436
437 do {
438 old_pendbaser = READ_ONCE(vgic_cpu->pendbaser);
439 pendbaser = old_pendbaser;
440 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
441 pendbaser = vgic_sanitise_pendbaser(pendbaser);
442 } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser,
443 pendbaser) != old_pendbaser);
444 }
445
446 /*
447 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
448 * redistributors, while SPIs are covered by registers in the distributor
449 * block. Trying to set private IRQs in this block gets ignored.
450 * We take some special care here to fix the calculation of the register
451 * offset.
452 */
453 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
454 { \
455 .reg_offset = off, \
456 .bits_per_irq = bpi, \
457 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
458 .access_flags = acc, \
459 .read = vgic_mmio_read_raz, \
460 .write = vgic_mmio_write_wi, \
461 }, { \
462 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
463 .bits_per_irq = bpi, \
464 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \
465 .access_flags = acc, \
466 .read = rd, \
467 .write = wr, \
468 .uaccess_read = ur, \
469 .uaccess_write = uw, \
470 }
471
472 static const struct vgic_register_region vgic_v3_dist_registers[] = {
473 REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,
474 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
475 NULL, vgic_mmio_uaccess_write_v3_misc,
476 16, VGIC_ACCESS_32bit),
477 REGISTER_DESC_WITH_LENGTH(GICD_STATUSR,
478 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
479 VGIC_ACCESS_32bit),
480 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
481 vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1,
482 VGIC_ACCESS_32bit),
483 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
484 vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,
485 VGIC_ACCESS_32bit),
486 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
487 vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,
488 VGIC_ACCESS_32bit),
489 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
490 vgic_mmio_read_pending, vgic_mmio_write_spending,
491 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
492 VGIC_ACCESS_32bit),
493 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
494 vgic_mmio_read_pending, vgic_mmio_write_cpending,
495 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1,
496 VGIC_ACCESS_32bit),
497 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
498 vgic_mmio_read_active, vgic_mmio_write_sactive,
499 NULL, vgic_mmio_uaccess_write_sactive, 1,
500 VGIC_ACCESS_32bit),
501 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
502 vgic_mmio_read_active, vgic_mmio_write_cactive,
503 NULL, vgic_mmio_uaccess_write_cactive,
504 1, VGIC_ACCESS_32bit),
505 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
506 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
507 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
508 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
509 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
510 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
511 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
512 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
513 VGIC_ACCESS_32bit),
514 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
515 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
516 VGIC_ACCESS_32bit),
517 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
518 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
519 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
520 REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
521 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
522 VGIC_ACCESS_32bit),
523 };
524
525 static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
526 REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
527 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
528 VGIC_ACCESS_32bit),
529 REGISTER_DESC_WITH_LENGTH(GICR_STATUSR,
530 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
531 VGIC_ACCESS_32bit),
532 REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
533 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
534 VGIC_ACCESS_32bit),
535 REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
536 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
537 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
538 REGISTER_DESC_WITH_LENGTH(GICR_WAKER,
539 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
540 VGIC_ACCESS_32bit),
541 REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
542 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
543 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
544 REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
545 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
546 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
547 REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
548 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
549 VGIC_ACCESS_32bit),
550 };
551
552 static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
553 REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
554 vgic_mmio_read_group, vgic_mmio_write_group, 4,
555 VGIC_ACCESS_32bit),
556 REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
557 vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
558 VGIC_ACCESS_32bit),
559 REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
560 vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
561 VGIC_ACCESS_32bit),
562 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISPENDR0,
563 vgic_mmio_read_pending, vgic_mmio_write_spending,
564 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
565 VGIC_ACCESS_32bit),
566 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICPENDR0,
567 vgic_mmio_read_pending, vgic_mmio_write_cpending,
568 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4,
569 VGIC_ACCESS_32bit),
570 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISACTIVER0,
571 vgic_mmio_read_active, vgic_mmio_write_sactive,
572 NULL, vgic_mmio_uaccess_write_sactive,
573 4, VGIC_ACCESS_32bit),
574 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICACTIVER0,
575 vgic_mmio_read_active, vgic_mmio_write_cactive,
576 NULL, vgic_mmio_uaccess_write_cactive,
577 4, VGIC_ACCESS_32bit),
578 REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
579 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
580 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
581 REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
582 vgic_mmio_read_config, vgic_mmio_write_config, 8,
583 VGIC_ACCESS_32bit),
584 REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
585 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
586 VGIC_ACCESS_32bit),
587 REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
588 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
589 VGIC_ACCESS_32bit),
590 };
591
vgic_v3_init_dist_iodev(struct vgic_io_device * dev)592 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
593 {
594 dev->regions = vgic_v3_dist_registers;
595 dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
596
597 kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
598
599 return SZ_64K;
600 }
601
602 /**
603 * vgic_register_redist_iodev - register a single redist iodev
604 * @vcpu: The VCPU to which the redistributor belongs
605 *
606 * Register a KVM iodev for this VCPU's redistributor using the address
607 * provided.
608 *
609 * Return 0 on success, -ERRNO otherwise.
610 */
vgic_register_redist_iodev(struct kvm_vcpu * vcpu)611 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu)
612 {
613 struct kvm *kvm = vcpu->kvm;
614 struct vgic_dist *vgic = &kvm->arch.vgic;
615 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
616 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
617 struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
618 struct vgic_redist_region *rdreg;
619 gpa_t rd_base, sgi_base;
620 int ret;
621
622 if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr))
623 return 0;
624
625 /*
626 * We may be creating VCPUs before having set the base address for the
627 * redistributor region, in which case we will come back to this
628 * function for all VCPUs when the base address is set. Just return
629 * without doing any work for now.
630 */
631 rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions);
632 if (!rdreg)
633 return 0;
634
635 if (!vgic_v3_check_base(kvm))
636 return -EINVAL;
637
638 vgic_cpu->rdreg = rdreg;
639
640 rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE;
641 sgi_base = rd_base + SZ_64K;
642
643 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
644 rd_dev->base_addr = rd_base;
645 rd_dev->iodev_type = IODEV_REDIST;
646 rd_dev->regions = vgic_v3_rdbase_registers;
647 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
648 rd_dev->redist_vcpu = vcpu;
649
650 mutex_lock(&kvm->slots_lock);
651 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
652 SZ_64K, &rd_dev->dev);
653 mutex_unlock(&kvm->slots_lock);
654
655 if (ret)
656 return ret;
657
658 kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
659 sgi_dev->base_addr = sgi_base;
660 sgi_dev->iodev_type = IODEV_REDIST;
661 sgi_dev->regions = vgic_v3_sgibase_registers;
662 sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
663 sgi_dev->redist_vcpu = vcpu;
664
665 mutex_lock(&kvm->slots_lock);
666 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
667 SZ_64K, &sgi_dev->dev);
668 if (ret) {
669 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
670 &rd_dev->dev);
671 goto out;
672 }
673
674 rdreg->free_index++;
675 out:
676 mutex_unlock(&kvm->slots_lock);
677 return ret;
678 }
679
vgic_unregister_redist_iodev(struct kvm_vcpu * vcpu)680 static void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu)
681 {
682 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
683 struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
684
685 kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev);
686 kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &sgi_dev->dev);
687 }
688
vgic_register_all_redist_iodevs(struct kvm * kvm)689 static int vgic_register_all_redist_iodevs(struct kvm *kvm)
690 {
691 struct kvm_vcpu *vcpu;
692 int c, ret = 0;
693
694 kvm_for_each_vcpu(c, vcpu, kvm) {
695 ret = vgic_register_redist_iodev(vcpu);
696 if (ret)
697 break;
698 }
699
700 if (ret) {
701 /* The current c failed, so we start with the previous one. */
702 mutex_lock(&kvm->slots_lock);
703 for (c--; c >= 0; c--) {
704 vcpu = kvm_get_vcpu(kvm, c);
705 vgic_unregister_redist_iodev(vcpu);
706 }
707 mutex_unlock(&kvm->slots_lock);
708 }
709
710 return ret;
711 }
712
713 /**
714 * vgic_v3_insert_redist_region - Insert a new redistributor region
715 *
716 * Performs various checks before inserting the rdist region in the list.
717 * Those tests depend on whether the size of the rdist region is known
718 * (ie. count != 0). The list is sorted by rdist region index.
719 *
720 * @kvm: kvm handle
721 * @index: redist region index
722 * @base: base of the new rdist region
723 * @count: number of redistributors the region is made of (0 in the old style
724 * single region, whose size is induced from the number of vcpus)
725 *
726 * Return 0 on success, < 0 otherwise
727 */
vgic_v3_insert_redist_region(struct kvm * kvm,uint32_t index,gpa_t base,uint32_t count)728 static int vgic_v3_insert_redist_region(struct kvm *kvm, uint32_t index,
729 gpa_t base, uint32_t count)
730 {
731 struct vgic_dist *d = &kvm->arch.vgic;
732 struct vgic_redist_region *rdreg;
733 struct list_head *rd_regions = &d->rd_regions;
734 size_t size = count * KVM_VGIC_V3_REDIST_SIZE;
735 int ret;
736
737 /* single rdist region already set ?*/
738 if (!count && !list_empty(rd_regions))
739 return -EINVAL;
740
741 /* cross the end of memory ? */
742 if (base + size < base)
743 return -EINVAL;
744
745 if (list_empty(rd_regions)) {
746 if (index != 0)
747 return -EINVAL;
748 } else {
749 rdreg = list_last_entry(rd_regions,
750 struct vgic_redist_region, list);
751 if (index != rdreg->index + 1)
752 return -EINVAL;
753
754 /* Cannot add an explicitly sized regions after legacy region */
755 if (!rdreg->count)
756 return -EINVAL;
757 }
758
759 /*
760 * For legacy single-region redistributor regions (!count),
761 * check that the redistributor region does not overlap with the
762 * distributor's address space.
763 */
764 if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
765 vgic_dist_overlap(kvm, base, size))
766 return -EINVAL;
767
768 /* collision with any other rdist region? */
769 if (vgic_v3_rdist_overlap(kvm, base, size))
770 return -EINVAL;
771
772 rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL);
773 if (!rdreg)
774 return -ENOMEM;
775
776 rdreg->base = VGIC_ADDR_UNDEF;
777
778 ret = vgic_check_ioaddr(kvm, &rdreg->base, base, SZ_64K);
779 if (ret)
780 goto free;
781
782 rdreg->base = base;
783 rdreg->count = count;
784 rdreg->free_index = 0;
785 rdreg->index = index;
786
787 list_add_tail(&rdreg->list, rd_regions);
788 return 0;
789 free:
790 kfree(rdreg);
791 return ret;
792 }
793
vgic_v3_set_redist_base(struct kvm * kvm,u32 index,u64 addr,u32 count)794 int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count)
795 {
796 int ret;
797
798 ret = vgic_v3_insert_redist_region(kvm, index, addr, count);
799 if (ret)
800 return ret;
801
802 /*
803 * Register iodevs for each existing VCPU. Adding more VCPUs
804 * afterwards will register the iodevs when needed.
805 */
806 ret = vgic_register_all_redist_iodevs(kvm);
807 if (ret)
808 return ret;
809
810 return 0;
811 }
812
vgic_v3_has_attr_regs(struct kvm_device * dev,struct kvm_device_attr * attr)813 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
814 {
815 const struct vgic_register_region *region;
816 struct vgic_io_device iodev;
817 struct vgic_reg_attr reg_attr;
818 struct kvm_vcpu *vcpu;
819 gpa_t addr;
820 int ret;
821
822 ret = vgic_v3_parse_attr(dev, attr, ®_attr);
823 if (ret)
824 return ret;
825
826 vcpu = reg_attr.vcpu;
827 addr = reg_attr.addr;
828
829 switch (attr->group) {
830 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
831 iodev.regions = vgic_v3_dist_registers;
832 iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
833 iodev.base_addr = 0;
834 break;
835 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{
836 iodev.regions = vgic_v3_rdbase_registers;
837 iodev.nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
838 iodev.base_addr = 0;
839 break;
840 }
841 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
842 u64 reg, id;
843
844 id = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
845 return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, ®);
846 }
847 default:
848 return -ENXIO;
849 }
850
851 /* We only support aligned 32-bit accesses. */
852 if (addr & 3)
853 return -ENXIO;
854
855 region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
856 if (!region)
857 return -ENXIO;
858
859 return 0;
860 }
861 /*
862 * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
863 * generation register ICC_SGI1R_EL1) with a given VCPU.
864 * If the VCPU's MPIDR matches, return the level0 affinity, otherwise
865 * return -1.
866 */
match_mpidr(u64 sgi_aff,u16 sgi_cpu_mask,struct kvm_vcpu * vcpu)867 static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
868 {
869 unsigned long affinity;
870 int level0;
871
872 /*
873 * Split the current VCPU's MPIDR into affinity level 0 and the
874 * rest as this is what we have to compare against.
875 */
876 affinity = kvm_vcpu_get_mpidr_aff(vcpu);
877 level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
878 affinity &= ~MPIDR_LEVEL_MASK;
879
880 /* bail out if the upper three levels don't match */
881 if (sgi_aff != affinity)
882 return -1;
883
884 /* Is this VCPU's bit set in the mask ? */
885 if (!(sgi_cpu_mask & BIT(level0)))
886 return -1;
887
888 return level0;
889 }
890
891 /*
892 * The ICC_SGI* registers encode the affinity differently from the MPIDR,
893 * so provide a wrapper to use the existing defines to isolate a certain
894 * affinity level.
895 */
896 #define SGI_AFFINITY_LEVEL(reg, level) \
897 ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
898 >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
899
900 /**
901 * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
902 * @vcpu: The VCPU requesting a SGI
903 * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU
904 * @allow_group1: Does the sysreg access allow generation of G1 SGIs
905 *
906 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
907 * This will trap in sys_regs.c and call this function.
908 * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
909 * target processors as well as a bitmask of 16 Aff0 CPUs.
910 * If the interrupt routing mode bit is not set, we iterate over all VCPUs to
911 * check for matching ones. If this bit is set, we signal all, but not the
912 * calling VCPU.
913 */
vgic_v3_dispatch_sgi(struct kvm_vcpu * vcpu,u64 reg,bool allow_group1)914 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1)
915 {
916 struct kvm *kvm = vcpu->kvm;
917 struct kvm_vcpu *c_vcpu;
918 u16 target_cpus;
919 u64 mpidr;
920 int sgi, c;
921 int vcpu_id = vcpu->vcpu_id;
922 bool broadcast;
923 unsigned long flags;
924
925 sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
926 broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
927 target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
928 mpidr = SGI_AFFINITY_LEVEL(reg, 3);
929 mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
930 mpidr |= SGI_AFFINITY_LEVEL(reg, 1);
931
932 /*
933 * We iterate over all VCPUs to find the MPIDRs matching the request.
934 * If we have handled one CPU, we clear its bit to detect early
935 * if we are already finished. This avoids iterating through all
936 * VCPUs when most of the times we just signal a single VCPU.
937 */
938 kvm_for_each_vcpu(c, c_vcpu, kvm) {
939 struct vgic_irq *irq;
940
941 /* Exit early if we have dealt with all requested CPUs */
942 if (!broadcast && target_cpus == 0)
943 break;
944
945 /* Don't signal the calling VCPU */
946 if (broadcast && c == vcpu_id)
947 continue;
948
949 if (!broadcast) {
950 int level0;
951
952 level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
953 if (level0 == -1)
954 continue;
955
956 /* remove this matching VCPU from the mask */
957 target_cpus &= ~BIT(level0);
958 }
959
960 irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
961
962 spin_lock_irqsave(&irq->irq_lock, flags);
963
964 /*
965 * An access targetting Group0 SGIs can only generate
966 * those, while an access targetting Group1 SGIs can
967 * generate interrupts of either group.
968 */
969 if (!irq->group || allow_group1) {
970 irq->pending_latch = true;
971 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
972 } else {
973 spin_unlock_irqrestore(&irq->irq_lock, flags);
974 }
975
976 vgic_put_irq(vcpu->kvm, irq);
977 }
978 }
979
vgic_v3_dist_uaccess(struct kvm_vcpu * vcpu,bool is_write,int offset,u32 * val)980 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
981 int offset, u32 *val)
982 {
983 struct vgic_io_device dev = {
984 .regions = vgic_v3_dist_registers,
985 .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers),
986 };
987
988 return vgic_uaccess(vcpu, &dev, is_write, offset, val);
989 }
990
vgic_v3_redist_uaccess(struct kvm_vcpu * vcpu,bool is_write,int offset,u32 * val)991 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
992 int offset, u32 *val)
993 {
994 struct vgic_io_device rd_dev = {
995 .regions = vgic_v3_rdbase_registers,
996 .nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers),
997 };
998
999 struct vgic_io_device sgi_dev = {
1000 .regions = vgic_v3_sgibase_registers,
1001 .nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers),
1002 };
1003
1004 /* SGI_base is the next 64K frame after RD_base */
1005 if (offset >= SZ_64K)
1006 return vgic_uaccess(vcpu, &sgi_dev, is_write, offset - SZ_64K,
1007 val);
1008 else
1009 return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
1010 }
1011
vgic_v3_line_level_info_uaccess(struct kvm_vcpu * vcpu,bool is_write,u32 intid,u64 * val)1012 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
1013 u32 intid, u64 *val)
1014 {
1015 if (intid % 32)
1016 return -EINVAL;
1017
1018 if (is_write)
1019 vgic_write_irq_line_level_info(vcpu, intid, *val);
1020 else
1021 *val = vgic_read_irq_line_level_info(vcpu, intid);
1022
1023 return 0;
1024 }
1025
