1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Ethernet driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #ifndef OTX2_COMMON_H
9 #define OTX2_COMMON_H
10
11 #include <linux/ethtool.h>
12 #include <linux/pci.h>
13 #include <linux/iommu.h>
14 #include <linux/net_tstamp.h>
15 #include <linux/ptp_clock_kernel.h>
16 #include <linux/timecounter.h>
17 #include <linux/soc/marvell/octeontx2/asm.h>
18 #include <net/pkt_cls.h>
19 #include <net/devlink.h>
20 #include <linux/time64.h>
21 #include <linux/dim.h>
22 #include <uapi/linux/if_macsec.h>
23
24 #include <mbox.h>
25 #include <npc.h>
26 #include "otx2_reg.h"
27 #include "otx2_txrx.h"
28 #include "otx2_devlink.h"
29 #include <rvu_trace.h>
30
31 /* PCI device IDs */
32 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063
33 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064
34 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8
35
36 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200
37 #define PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF 0xBD00
38
39 /* PCI BAR nos */
40 #define PCI_CFG_REG_BAR_NUM 2
41 #define PCI_MBOX_BAR_NUM 4
42
43 #define NAME_SIZE 32
44
45 #ifdef CONFIG_DCB
46 /* Max priority supported for PFC */
47 #define NIX_PF_PFC_PRIO_MAX 8
48 #endif
49
50 enum arua_mapped_qtypes {
51 AURA_NIX_RQ,
52 AURA_NIX_SQ,
53 };
54
55 /* NIX LF interrupts range*/
56 #define NIX_LF_QINT_VEC_START 0x00
57 #define NIX_LF_CINT_VEC_START 0x40
58 #define NIX_LF_GINT_VEC 0x80
59 #define NIX_LF_ERR_VEC 0x81
60 #define NIX_LF_POISON_VEC 0x82
61
62 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */
63 #define SEND_CQ_SKID 2000
64
65 #define OTX2_GET_RX_STATS(reg) \
66 otx2_read64(pfvf, NIX_LF_RX_STATX(reg))
67 #define OTX2_GET_TX_STATS(reg) \
68 otx2_read64(pfvf, NIX_LF_TX_STATX(reg))
69
70 struct otx2_lmt_info {
71 u64 lmt_addr;
72 u16 lmt_id;
73 };
74 /* RSS configuration */
75 struct otx2_rss_ctx {
76 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE];
77 };
78
79 struct otx2_rss_info {
80 u8 enable;
81 u32 flowkey_cfg;
82 u16 rss_size;
83 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */
84 u8 key[RSS_HASH_KEY_SIZE];
85 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS];
86 };
87
88 /* NIX (or NPC) RX errors */
89 enum otx2_errlvl {
90 NPC_ERRLVL_RE,
91 NPC_ERRLVL_LID_LA,
92 NPC_ERRLVL_LID_LB,
93 NPC_ERRLVL_LID_LC,
94 NPC_ERRLVL_LID_LD,
95 NPC_ERRLVL_LID_LE,
96 NPC_ERRLVL_LID_LF,
97 NPC_ERRLVL_LID_LG,
98 NPC_ERRLVL_LID_LH,
99 NPC_ERRLVL_NIX = 0x0F,
100 };
101
102 enum otx2_errcodes_re {
103 /* NPC_ERRLVL_RE errcodes */
104 ERRCODE_FCS = 0x7,
105 ERRCODE_FCS_RCV = 0x8,
106 ERRCODE_UNDERSIZE = 0x10,
107 ERRCODE_OVERSIZE = 0x11,
108 ERRCODE_OL2_LEN_MISMATCH = 0x12,
109 /* NPC_ERRLVL_NIX errcodes */
110 ERRCODE_OL3_LEN = 0x10,
111 ERRCODE_OL4_LEN = 0x11,
112 ERRCODE_OL4_CSUM = 0x12,
113 ERRCODE_IL3_LEN = 0x20,
114 ERRCODE_IL4_LEN = 0x21,
115 ERRCODE_IL4_CSUM = 0x22,
116 };
117
118 /* NIX TX stats */
119 enum nix_stat_lf_tx {
120 TX_UCAST = 0x0,
121 TX_BCAST = 0x1,
122 TX_MCAST = 0x2,
123 TX_DROP = 0x3,
124 TX_OCTS = 0x4,
125 TX_STATS_ENUM_LAST,
126 };
127
128 /* NIX RX stats */
129 enum nix_stat_lf_rx {
130 RX_OCTS = 0x0,
131 RX_UCAST = 0x1,
132 RX_BCAST = 0x2,
133 RX_MCAST = 0x3,
134 RX_DROP = 0x4,
135 RX_DROP_OCTS = 0x5,
136 RX_FCS = 0x6,
137 RX_ERR = 0x7,
138 RX_DRP_BCAST = 0x8,
139 RX_DRP_MCAST = 0x9,
140 RX_DRP_L3BCAST = 0xa,
141 RX_DRP_L3MCAST = 0xb,
142 RX_STATS_ENUM_LAST,
143 };
144
145 struct otx2_dev_stats {
146 u64 rx_bytes;
147 u64 rx_frames;
148 u64 rx_ucast_frames;
149 u64 rx_bcast_frames;
150 u64 rx_mcast_frames;
151 u64 rx_drops;
152
153 u64 tx_bytes;
154 u64 tx_frames;
155 u64 tx_ucast_frames;
156 u64 tx_bcast_frames;
157 u64 tx_mcast_frames;
158 u64 tx_drops;
159 };
160
161 /* Driver counted stats */
162 struct otx2_drv_stats {
163 atomic_t rx_fcs_errs;
164 atomic_t rx_oversize_errs;
165 atomic_t rx_undersize_errs;
166 atomic_t rx_csum_errs;
167 atomic_t rx_len_errs;
168 atomic_t rx_other_errs;
169 };
170
171 struct mbox {
172 struct otx2_mbox mbox;
173 struct work_struct mbox_wrk;
174 struct otx2_mbox mbox_up;
175 struct work_struct mbox_up_wrk;
176 struct otx2_nic *pfvf;
177 void *bbuf_base; /* Bounce buffer for mbox memory */
178 struct mutex lock; /* serialize mailbox access */
179 int num_msgs; /* mbox number of messages */
180 int up_num_msgs; /* mbox_up number of messages */
181 };
182
183 struct otx2_hw {
184 struct pci_dev *pdev;
185 struct otx2_rss_info rss_info;
186 u16 rx_queues;
187 u16 tx_queues;
188 u16 xdp_queues;
189 u16 tot_tx_queues;
190 u16 max_queues;
191 u16 pool_cnt;
192 u16 rqpool_cnt;
193 u16 sqpool_cnt;
194
195 #define OTX2_DEFAULT_RBUF_LEN 2048
196 u16 rbuf_len;
197 u32 xqe_size;
198
199 /* NPA */
200 u32 stack_pg_ptrs; /* No of ptrs per stack page */
201 u32 stack_pg_bytes; /* Size of stack page */
202 u16 sqb_size;
203
204 /* NIX */
205 u8 txschq_link_cfg_lvl;
206 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
207 u16 matchall_ipolicer;
208 u32 dwrr_mtu;
209
210 /* HW settings, coalescing etc */
211 u16 rx_chan_base;
212 u16 tx_chan_base;
213 u16 cq_qcount_wait;
214 u16 cq_ecount_wait;
215 u16 rq_skid;
216 u8 cq_time_wait;
217
218 /* Segmentation */
219 u8 lso_tsov4_idx;
220 u8 lso_tsov6_idx;
221 u8 lso_udpv4_idx;
222 u8 lso_udpv6_idx;
223
224 /* RSS */
225 u8 flowkey_alg_idx;
226
227 /* MSI-X */
228 u8 cint_cnt; /* CQ interrupt count */
229 u16 npa_msixoff; /* Offset of NPA vectors */
230 u16 nix_msixoff; /* Offset of NIX vectors */
231 char *irq_name;
232 cpumask_var_t *affinity_mask;
233
234 /* Stats */
235 struct otx2_dev_stats dev_stats;
236 struct otx2_drv_stats drv_stats;
237 u64 cgx_rx_stats[CGX_RX_STATS_COUNT];
238 u64 cgx_tx_stats[CGX_TX_STATS_COUNT];
239 u64 cgx_fec_corr_blks;
240 u64 cgx_fec_uncorr_blks;
241 u8 cgx_links; /* No. of CGX links present in HW */
242 u8 lbk_links; /* No. of LBK links present in HW */
243 u8 tx_link; /* Transmit channel link number */
244 #define HW_TSO 0
245 #define CN10K_MBOX 1
246 #define CN10K_LMTST 2
247 #define CN10K_RPM 3
248 #define CN10K_PTP_ONESTEP 4
249 #define CN10K_HW_MACSEC 5
250 unsigned long cap_flag;
251
252 #define LMT_LINE_SIZE 128
253 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */
254 u64 *lmt_base;
255 struct otx2_lmt_info __percpu *lmt_info;
256 };
257
258 enum vfperm {
259 OTX2_RESET_VF_PERM,
260 OTX2_TRUSTED_VF,
261 };
262
263 struct otx2_vf_config {
264 struct otx2_nic *pf;
265 struct delayed_work link_event_work;
266 bool intf_down; /* interface was either configured or not */
267 u8 mac[ETH_ALEN];
268 u16 vlan;
269 int tx_vtag_idx;
270 bool trusted;
271 };
272
273 struct flr_work {
274 struct work_struct work;
275 struct otx2_nic *pf;
276 };
277
278 struct refill_work {
279 struct delayed_work pool_refill_work;
280 struct otx2_nic *pf;
281 };
282
283 /* PTPv2 originTimestamp structure */
284 struct ptpv2_tstamp {
285 __be16 seconds_msb; /* 16 bits + */
286 __be32 seconds_lsb; /* 32 bits = 48 bits*/
287 __be32 nanoseconds;
288 } __packed;
289
290 struct otx2_ptp {
291 struct ptp_clock_info ptp_info;
292 struct ptp_clock *ptp_clock;
293 struct otx2_nic *nic;
294
295 struct cyclecounter cycle_counter;
296 struct timecounter time_counter;
297
298 struct delayed_work extts_work;
299 u64 last_extts;
300 u64 thresh;
301
302 struct ptp_pin_desc extts_config;
303 u64 (*convert_rx_ptp_tstmp)(u64 timestamp);
304 u64 (*convert_tx_ptp_tstmp)(u64 timestamp);
305 struct delayed_work synctstamp_work;
306 u64 tstamp;
307 u32 base_ns;
308 };
309
310 #define OTX2_HW_TIMESTAMP_LEN 8
311
312 struct otx2_mac_table {
313 u8 addr[ETH_ALEN];
314 u16 mcam_entry;
315 bool inuse;
316 };
317
318 struct otx2_flow_config {
319 u16 *flow_ent;
320 u16 *def_ent;
321 u16 nr_flows;
322 #define OTX2_DEFAULT_FLOWCOUNT 16
323 #define OTX2_MAX_UNICAST_FLOWS 8
324 #define OTX2_MAX_VLAN_FLOWS 1
325 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT
326 #define OTX2_MCAM_COUNT (OTX2_DEFAULT_FLOWCOUNT + \
327 OTX2_MAX_UNICAST_FLOWS + \
328 OTX2_MAX_VLAN_FLOWS)
329 u16 unicast_offset;
330 u16 rx_vlan_offset;
331 u16 vf_vlan_offset;
332 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */
333 #define OTX2_VF_VLAN_RX_INDEX 0
334 #define OTX2_VF_VLAN_TX_INDEX 1
335 u16 max_flows;
336 u8 dmacflt_max_flows;
337 u32 *bmap_to_dmacindex;
338 unsigned long *dmacflt_bmap;
339 struct list_head flow_list;
340 };
341
342 struct otx2_tc_info {
343 /* hash table to store TC offloaded flows */
344 struct rhashtable flow_table;
345 struct rhashtable_params flow_ht_params;
346 unsigned long *tc_entries_bitmap;
347 };
348
349 struct dev_hw_ops {
350 int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura);
351 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq,
352 int size, int qidx);
353 void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq);
354 void (*aura_freeptr)(void *dev, int aura, u64 buf);
355 };
356
357 #define CN10K_MCS_SA_PER_SC 4
358
359 /* Stats which need to be accumulated in software because
360 * of shared counters in hardware.
361 */
362 struct cn10k_txsc_stats {
363 u64 InPktsUntagged;
364 u64 InPktsNoTag;
365 u64 InPktsBadTag;
366 u64 InPktsUnknownSCI;
367 u64 InPktsNoSCI;
368 u64 InPktsOverrun;
369 };
370
371 struct cn10k_rxsc_stats {
372 u64 InOctetsValidated;
373 u64 InOctetsDecrypted;
374 u64 InPktsUnchecked;
375 u64 InPktsDelayed;
376 u64 InPktsOK;
377 u64 InPktsInvalid;
378 u64 InPktsLate;
379 u64 InPktsNotValid;
380 u64 InPktsNotUsingSA;
381 u64 InPktsUnusedSA;
382 };
383
384 struct cn10k_mcs_txsc {
385 struct macsec_secy *sw_secy;
386 struct cn10k_txsc_stats stats;
387 struct list_head entry;
388 enum macsec_validation_type last_validate_frames;
389 bool last_protect_frames;
390 u16 hw_secy_id_tx;
391 u16 hw_secy_id_rx;
392 u16 hw_flow_id;
393 u16 hw_sc_id;
394 u16 hw_sa_id[CN10K_MCS_SA_PER_SC];
395 u8 sa_bmap;
396 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN];
397 u8 encoding_sa;
398 };
399
400 struct cn10k_mcs_rxsc {
401 struct macsec_secy *sw_secy;
402 struct macsec_rx_sc *sw_rxsc;
403 struct cn10k_rxsc_stats stats;
404 struct list_head entry;
405 u16 hw_flow_id;
406 u16 hw_sc_id;
407 u16 hw_sa_id[CN10K_MCS_SA_PER_SC];
408 u8 sa_bmap;
409 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN];
410 };
411
412 struct cn10k_mcs_cfg {
413 struct list_head txsc_list;
414 struct list_head rxsc_list;
415 };
416
417 struct otx2_nic {
418 void __iomem *reg_base;
419 struct net_device *netdev;
420 struct dev_hw_ops *hw_ops;
421 void *iommu_domain;
422 u16 tx_max_pktlen;
423 u16 rbsize; /* Receive buffer size */
424
425 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0)
426 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1)
427 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2)
428 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3)
429 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4)
430 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5)
431 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6)
432 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7)
433 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8)
434 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9)
435 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10)
436 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11)
437 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12)
438 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13)
439 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14)
440 #define OTX2_FLAG_PTP_ONESTEP_SYNC BIT_ULL(15)
441 #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16)
442 u64 flags;
443 u64 *cq_op_addr;
444
445 struct bpf_prog *xdp_prog;
446 struct otx2_qset qset;
447 struct otx2_hw hw;
448 struct pci_dev *pdev;
449 struct device *dev;
450
451 /* Mbox */
452 struct mbox mbox;
453 struct mbox *mbox_pfvf;
454 struct workqueue_struct *mbox_wq;
455 struct workqueue_struct *mbox_pfvf_wq;
456
457 u8 total_vfs;
458 u16 pcifunc; /* RVU PF_FUNC */
459 u16 bpid[NIX_MAX_BPID_CHAN];
460 struct otx2_vf_config *vf_configs;
461 struct cgx_link_user_info linfo;
462
463 /* NPC MCAM */
464 struct otx2_flow_config *flow_cfg;
465 struct otx2_mac_table *mac_table;
466 struct otx2_tc_info tc_info;
467
468 u64 reset_count;
469 struct work_struct reset_task;
470 struct workqueue_struct *flr_wq;
471 struct flr_work *flr_wrk;
472 struct refill_work *refill_wrk;
473 struct workqueue_struct *otx2_wq;
474 struct work_struct rx_mode_work;
475
476 /* Ethtool stuff */
477 u32 msg_enable;
478
479 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */
480 int nix_blkaddr;
481 /* LMTST Lines info */
482 struct qmem *dync_lmt;
483 u16 tot_lmt_lines;
484 u16 npa_lmt_lines;
485 u32 nix_lmt_size;
486
487 struct otx2_ptp *ptp;
488 struct hwtstamp_config tstamp;
489
490 unsigned long rq_bmap;
491
492 /* Devlink */
493 struct otx2_devlink *dl;
494 #ifdef CONFIG_DCB
495 /* PFC */
496 u8 pfc_en;
497 u8 *queue_to_pfc_map;
498 u16 pfc_schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
499 bool pfc_alloc_status[NIX_PF_PFC_PRIO_MAX];
500 #endif
501
502 /* napi event count. It is needed for adaptive irq coalescing. */
503 u32 napi_events;
504
505 #if IS_ENABLED(CONFIG_MACSEC)
506 struct cn10k_mcs_cfg *macsec_cfg;
507 #endif
508 };
509
is_otx2_lbkvf(struct pci_dev * pdev)510 static inline bool is_otx2_lbkvf(struct pci_dev *pdev)
511 {
512 return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF;
513 }
514
is_96xx_A0(struct pci_dev * pdev)515 static inline bool is_96xx_A0(struct pci_dev *pdev)
516 {
517 return (pdev->revision == 0x00) &&
518 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF);
519 }
520
is_96xx_B0(struct pci_dev * pdev)521 static inline bool is_96xx_B0(struct pci_dev *pdev)
522 {
523 return (pdev->revision == 0x01) &&
524 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF);
525 }
526
527 /* REVID for PCIe devices.
528 * Bits 0..1: minor pass, bit 3..2: major pass
529 * bits 7..4: midr id
530 */
531 #define PCI_REVISION_ID_96XX 0x00
532 #define PCI_REVISION_ID_95XX 0x10
533 #define PCI_REVISION_ID_95XXN 0x20
534 #define PCI_REVISION_ID_98XX 0x30
535 #define PCI_REVISION_ID_95XXMM 0x40
536 #define PCI_REVISION_ID_95XXO 0xE0
537
is_dev_otx2(struct pci_dev * pdev)538 static inline bool is_dev_otx2(struct pci_dev *pdev)
539 {
540 u8 midr = pdev->revision & 0xF0;
541
542 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
543 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
544 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
545 }
546
is_dev_cn10kb(struct pci_dev * pdev)547 static inline bool is_dev_cn10kb(struct pci_dev *pdev)
548 {
549 return pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF;
550 }
551
otx2_setup_dev_hw_settings(struct otx2_nic * pfvf)552 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf)
553 {
554 struct otx2_hw *hw = &pfvf->hw;
555
556 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT;
557 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT;
558 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT;
559
560 __set_bit(HW_TSO, &hw->cap_flag);
561
562 if (is_96xx_A0(pfvf->pdev)) {
563 __clear_bit(HW_TSO, &hw->cap_flag);
564
565 /* Time based irq coalescing is not supported */
566 pfvf->hw.cq_qcount_wait = 0x0;
567
568 /* Due to HW issue previous silicons required minimum
569 * 600 unused CQE to avoid CQ overflow.
570 */
571 pfvf->hw.rq_skid = 600;
572 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K);
573 }
574 if (is_96xx_B0(pfvf->pdev))
575 __clear_bit(HW_TSO, &hw->cap_flag);
576
577 if (!is_dev_otx2(pfvf->pdev)) {
578 __set_bit(CN10K_MBOX, &hw->cap_flag);
579 __set_bit(CN10K_LMTST, &hw->cap_flag);
580 __set_bit(CN10K_RPM, &hw->cap_flag);
581 __set_bit(CN10K_PTP_ONESTEP, &hw->cap_flag);
582 }
583
584 if (is_dev_cn10kb(pfvf->pdev))
585 __set_bit(CN10K_HW_MACSEC, &hw->cap_flag);
586 }
587
588 /* Register read/write APIs */
otx2_get_regaddr(struct otx2_nic * nic,u64 offset)589 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset)
590 {
591 u64 blkaddr;
592
593 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) {
594 case BLKTYPE_NIX:
595 blkaddr = nic->nix_blkaddr;
596 break;
597 case BLKTYPE_NPA:
598 blkaddr = BLKADDR_NPA;
599 break;
600 default:
601 blkaddr = BLKADDR_RVUM;
602 break;
603 }
604
605 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT);
606 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT);
607
608 return nic->reg_base + offset;
609 }
610
otx2_write64(struct otx2_nic * nic,u64 offset,u64 val)611 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val)
612 {
613 void __iomem *addr = otx2_get_regaddr(nic, offset);
614
615 writeq(val, addr);
616 }
617
otx2_read64(struct otx2_nic * nic,u64 offset)618 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset)
619 {
620 void __iomem *addr = otx2_get_regaddr(nic, offset);
621
622 return readq(addr);
623 }
624
625 /* Mbox bounce buffer APIs */
otx2_mbox_bbuf_init(struct mbox * mbox,struct pci_dev * pdev)626 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev)
627 {
628 struct otx2_mbox *otx2_mbox;
629 struct otx2_mbox_dev *mdev;
630
631 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL);
632 if (!mbox->bbuf_base)
633 return -ENOMEM;
634
635 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF
636 * prepare all mbox messages in bounce buffer instead of directly
637 * in hw mbox memory.
638 */
639 otx2_mbox = &mbox->mbox;
640 mdev = &otx2_mbox->dev[0];
641 mdev->mbase = mbox->bbuf_base;
642
643 otx2_mbox = &mbox->mbox_up;
644 mdev = &otx2_mbox->dev[0];
645 mdev->mbase = mbox->bbuf_base;
646 return 0;
647 }
648
otx2_sync_mbox_bbuf(struct otx2_mbox * mbox,int devid)649 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid)
650 {
651 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
652 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE);
653 struct otx2_mbox_dev *mdev = &mbox->dev[devid];
654 struct mbox_hdr *hdr;
655 u64 msg_size;
656
657 if (mdev->mbase == hw_mbase)
658 return;
659
660 hdr = hw_mbase + mbox->rx_start;
661 msg_size = hdr->msg_size;
662
663 if (msg_size > mbox->rx_size - msgs_offset)
664 msg_size = mbox->rx_size - msgs_offset;
665
666 /* Copy mbox messages from mbox memory to bounce buffer */
667 memcpy(mdev->mbase + mbox->rx_start,
668 hw_mbase + mbox->rx_start, msg_size + msgs_offset);
669 }
670
671 /* With the absence of API for 128-bit IO memory access for arm64,
672 * implement required operations at place.
673 */
674 #if defined(CONFIG_ARM64)
otx2_write128(u64 lo,u64 hi,void __iomem * addr)675 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr)
676 {
677 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!"
678 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr));
679 }
680
otx2_atomic64_add(u64 incr,u64 * ptr)681 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr)
682 {
683 u64 result;
684
685 __asm__ volatile(".cpu generic+lse\n"
686 "ldadd %x[i], %x[r], [%[b]]"
687 : [r]"=r"(result), "+m"(*ptr)
688 : [i]"r"(incr), [b]"r"(ptr)
689 : "memory");
690 return result;
691 }
692
693 #else
694 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr)
695 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; })
696 #endif
697
__cn10k_aura_freeptr(struct otx2_nic * pfvf,u64 aura,u64 * ptrs,u64 num_ptrs)698 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura,
699 u64 *ptrs, u64 num_ptrs)
700 {
701 struct otx2_lmt_info *lmt_info;
702 u64 size = 0, count_eot = 0;
703 u64 tar_addr, val = 0;
704
705 lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id());
706 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0);
707 /* LMTID is same as AURA Id */
708 val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63);
709 /* Set if [127:64] of last 128bit word has a valid pointer */
710 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL;
711 /* Set AURA ID to free pointer */
712 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF);
713 /* Target address for LMTST flush tells HW how many 128bit
714 * words are valid from NPA_LF_AURA_BATCH_FREE0.
715 *
716 * tar_addr[6:4] is LMTST size-1 in units of 128b.
717 */
718 if (num_ptrs > 2) {
719 size = (sizeof(u64) * num_ptrs) / 16;
720 if (!count_eot)
721 size++;
722 tar_addr |= ((size - 1) & 0x7) << 4;
723 }
724 dma_wmb();
725 memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs);
726 /* Perform LMTST flush */
727 cn10k_lmt_flush(val, tar_addr);
728 }
729
cn10k_aura_freeptr(void * dev,int aura,u64 buf)730 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf)
731 {
732 struct otx2_nic *pfvf = dev;
733 u64 ptrs[2];
734
735 ptrs[1] = buf;
736 /* Free only one buffer at time during init and teardown */
737 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2);
738 }
739
740 /* Alloc pointer from pool/aura */
otx2_aura_allocptr(struct otx2_nic * pfvf,int aura)741 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura)
742 {
743 u64 *ptr = (u64 *)otx2_get_regaddr(pfvf,
744 NPA_LF_AURA_OP_ALLOCX(0));
745 u64 incr = (u64)aura | BIT_ULL(63);
746
747 return otx2_atomic64_add(incr, ptr);
748 }
749
750 /* Free pointer to a pool/aura */
otx2_aura_freeptr(void * dev,int aura,u64 buf)751 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf)
752 {
753 struct otx2_nic *pfvf = dev;
754 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0);
755
756 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr);
757 }
758
otx2_get_pool_idx(struct otx2_nic * pfvf,int type,int idx)759 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx)
760 {
761 if (type == AURA_NIX_SQ)
762 return pfvf->hw.rqpool_cnt + idx;
763
764 /* AURA_NIX_RQ */
765 return idx;
766 }
767
768 /* Mbox APIs */
otx2_sync_mbox_msg(struct mbox * mbox)769 static inline int otx2_sync_mbox_msg(struct mbox *mbox)
770 {
771 int err;
772
773 if (!otx2_mbox_nonempty(&mbox->mbox, 0))
774 return 0;
775 otx2_mbox_msg_send(&mbox->mbox, 0);
776 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0);
777 if (err)
778 return err;
779
780 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0);
781 }
782
otx2_sync_mbox_up_msg(struct mbox * mbox,int devid)783 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid)
784 {
785 int err;
786
787 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid))
788 return 0;
789 otx2_mbox_msg_send(&mbox->mbox_up, devid);
790 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid);
791 if (err)
792 return err;
793
794 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid);
795 }
796
797 /* Use this API to send mbox msgs in atomic context
798 * where sleeping is not allowed
799 */
otx2_sync_mbox_msg_busy_poll(struct mbox * mbox)800 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox)
801 {
802 int err;
803
804 if (!otx2_mbox_nonempty(&mbox->mbox, 0))
805 return 0;
806 otx2_mbox_msg_send(&mbox->mbox, 0);
807 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0);
808 if (err)
809 return err;
810
811 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0);
812 }
813
814 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
815 static struct _req_type __maybe_unused \
816 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \
817 { \
818 struct _req_type *req; \
819 \
820 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
821 &mbox->mbox, 0, sizeof(struct _req_type), \
822 sizeof(struct _rsp_type)); \
823 if (!req) \
824 return NULL; \
825 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
826 req->hdr.id = _id; \
827 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \
828 return req; \
829 }
830
831 MBOX_MESSAGES
832 #undef M
833
834 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
835 int \
836 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \
837 struct _req_type *req, \
838 struct _rsp_type *rsp); \
839
840 MBOX_UP_CGX_MESSAGES
841 MBOX_UP_MCS_MESSAGES
842 #undef M
843
844 /* Time to wait before watchdog kicks off */
845 #define OTX2_TX_TIMEOUT (100 * HZ)
846
847 #define RVU_PFVF_PF_SHIFT 10
848 #define RVU_PFVF_PF_MASK 0x3F
849 #define RVU_PFVF_FUNC_SHIFT 0
850 #define RVU_PFVF_FUNC_MASK 0x3FF
851
is_otx2_vf(u16 pcifunc)852 static inline bool is_otx2_vf(u16 pcifunc)
853 {
854 return !!(pcifunc & RVU_PFVF_FUNC_MASK);
855 }
856
rvu_get_pf(u16 pcifunc)857 static inline int rvu_get_pf(u16 pcifunc)
858 {
859 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
860 }
861
otx2_dma_map_page(struct otx2_nic * pfvf,struct page * page,size_t offset,size_t size,enum dma_data_direction dir)862 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf,
863 struct page *page,
864 size_t offset, size_t size,
865 enum dma_data_direction dir)
866 {
867 dma_addr_t iova;
868
869 iova = dma_map_page_attrs(pfvf->dev, page,
870 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC);
871 if (unlikely(dma_mapping_error(pfvf->dev, iova)))
872 return (dma_addr_t)NULL;
873 return iova;
874 }
875
otx2_dma_unmap_page(struct otx2_nic * pfvf,dma_addr_t addr,size_t size,enum dma_data_direction dir)876 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf,
877 dma_addr_t addr, size_t size,
878 enum dma_data_direction dir)
879 {
880 dma_unmap_page_attrs(pfvf->dev, addr, size,
881 dir, DMA_ATTR_SKIP_CPU_SYNC);
882 }
883
otx2_get_smq_idx(struct otx2_nic * pfvf,u16 qidx)884 static inline u16 otx2_get_smq_idx(struct otx2_nic *pfvf, u16 qidx)
885 {
886 #ifdef CONFIG_DCB
887 if (qidx < NIX_PF_PFC_PRIO_MAX && pfvf->pfc_alloc_status[qidx])
888 return pfvf->pfc_schq_list[NIX_TXSCH_LVL_SMQ][qidx];
889 #endif
890
891 return pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0];
892 }
893
894 /* MSI-X APIs */
895 void otx2_free_cints(struct otx2_nic *pfvf, int n);
896 void otx2_set_cints_affinity(struct otx2_nic *pfvf);
897 int otx2_set_mac_address(struct net_device *netdev, void *p);
898 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu);
899 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq);
900 void otx2_get_mac_from_af(struct net_device *netdev);
901 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx);
902 int otx2_config_pause_frm(struct otx2_nic *pfvf);
903 void otx2_setup_segmentation(struct otx2_nic *pfvf);
904
905 /* RVU block related APIs */
906 int otx2_attach_npa_nix(struct otx2_nic *pfvf);
907 int otx2_detach_resources(struct mbox *mbox);
908 int otx2_config_npa(struct otx2_nic *pfvf);
909 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf);
910 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf);
911 void otx2_aura_pool_free(struct otx2_nic *pfvf);
912 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type);
913 void otx2_sq_free_sqbs(struct otx2_nic *pfvf);
914 int otx2_config_nix(struct otx2_nic *pfvf);
915 int otx2_config_nix_queues(struct otx2_nic *pfvf);
916 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool pfc_en);
917 int otx2_txsch_alloc(struct otx2_nic *pfvf);
918 int otx2_txschq_stop(struct otx2_nic *pfvf);
919 void otx2_sqb_flush(struct otx2_nic *pfvf);
920 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
921 dma_addr_t *dma);
922 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable);
923 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa);
924 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable);
925 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
926 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
927 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);
928 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);
929 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,
930 dma_addr_t *dma);
931
932 /* RSS configuration APIs*/
933 int otx2_rss_init(struct otx2_nic *pfvf);
934 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf);
935 void otx2_set_rss_key(struct otx2_nic *pfvf);
936 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id);
937
938 /* Mbox handlers */
939 void mbox_handler_msix_offset(struct otx2_nic *pfvf,
940 struct msix_offset_rsp *rsp);
941 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
942 struct npa_lf_alloc_rsp *rsp);
943 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
944 struct nix_lf_alloc_rsp *rsp);
945 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf,
946 struct nix_txsch_alloc_rsp *rsp);
947 void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
948 struct cgx_stats_rsp *rsp);
949 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf,
950 struct cgx_fec_stats_rsp *rsp);
951 void otx2_set_fec_stats_count(struct otx2_nic *pfvf);
952 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf,
953 struct nix_bp_cfg_rsp *rsp);
954
955 /* Device stats APIs */
956 void otx2_get_dev_stats(struct otx2_nic *pfvf);
957 void otx2_get_stats64(struct net_device *netdev,
958 struct rtnl_link_stats64 *stats);
959 void otx2_update_lmac_stats(struct otx2_nic *pfvf);
960 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf);
961 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx);
962 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx);
963 void otx2_set_ethtool_ops(struct net_device *netdev);
964 void otx2vf_set_ethtool_ops(struct net_device *netdev);
965
966 int otx2_open(struct net_device *netdev);
967 int otx2_stop(struct net_device *netdev);
968 int otx2_set_real_num_queues(struct net_device *netdev,
969 int tx_queues, int rx_queues);
970 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd);
971 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr);
972
973 /* MCAM filter related APIs */
974 int otx2_mcam_flow_init(struct otx2_nic *pf);
975 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf);
976 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count);
977 void otx2_mcam_flow_del(struct otx2_nic *pf);
978 int otx2_destroy_ntuple_flows(struct otx2_nic *pf);
979 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf);
980 int otx2_get_flow(struct otx2_nic *pfvf,
981 struct ethtool_rxnfc *nfc, u32 location);
982 int otx2_get_all_flows(struct otx2_nic *pfvf,
983 struct ethtool_rxnfc *nfc, u32 *rule_locs);
984 int otx2_add_flow(struct otx2_nic *pfvf,
985 struct ethtool_rxnfc *nfc);
986 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location);
987 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg);
988 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id);
989 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac);
990 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac);
991 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable);
992 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf);
993 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx);
994 u16 otx2_get_max_mtu(struct otx2_nic *pfvf);
995 int otx2_handle_ntuple_tc_features(struct net_device *netdev,
996 netdev_features_t features);
997 int otx2_smq_flush(struct otx2_nic *pfvf, int smq);
998
999 /* tc support */
1000 int otx2_init_tc(struct otx2_nic *nic);
1001 void otx2_shutdown_tc(struct otx2_nic *nic);
1002 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type,
1003 void *type_data);
1004 int otx2_tc_alloc_ent_bitmap(struct otx2_nic *nic);
1005 /* CGX/RPM DMAC filters support */
1006 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf);
1007 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u32 bit_pos);
1008 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u32 bit_pos);
1009 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u32 bit_pos);
1010 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf);
1011 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf);
1012
1013 #ifdef CONFIG_DCB
1014 /* DCB support*/
1015 void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx, bool pfc_enable);
1016 int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf);
1017 int otx2_dcbnl_set_ops(struct net_device *dev);
1018 /* PFC support */
1019 int otx2_pfc_txschq_config(struct otx2_nic *pfvf);
1020 int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf);
1021 int otx2_pfc_txschq_update(struct otx2_nic *pfvf);
1022 int otx2_pfc_txschq_stop(struct otx2_nic *pfvf);
1023 #endif
1024
1025 #if IS_ENABLED(CONFIG_MACSEC)
1026 /* MACSEC offload support */
1027 int cn10k_mcs_init(struct otx2_nic *pfvf);
1028 void cn10k_mcs_free(struct otx2_nic *pfvf);
1029 void cn10k_handle_mcs_event(struct otx2_nic *pfvf, struct mcs_intr_info *event);
1030 #else
cn10k_mcs_init(struct otx2_nic * pfvf)1031 static inline int cn10k_mcs_init(struct otx2_nic *pfvf) { return 0; }
cn10k_mcs_free(struct otx2_nic * pfvf)1032 static inline void cn10k_mcs_free(struct otx2_nic *pfvf) {}
cn10k_handle_mcs_event(struct otx2_nic * pfvf,struct mcs_intr_info * event)1033 static inline void cn10k_handle_mcs_event(struct otx2_nic *pfvf,
1034 struct mcs_intr_info *event)
1035 {}
1036 #endif /* CONFIG_MACSEC */
1037
1038 #endif /* OTX2_COMMON_H */
1039
