1 /*
2 * Copyright (C) Icenowy Zheng <icenowy@aosc.io>
3 *
4 * Based on sun4i_layer.h, which is:
5 * Copyright (C) 2015 Free Electrons
6 * Copyright (C) 2015 NextThing Co
7 *
8 * Maxime Ripard <maxime.ripard@free-electrons.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 */
15
16 #include <drm/drm_atomic.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_fb_cma_helper.h>
21 #include <drm/drm_gem_cma_helper.h>
22 #include <drm/drm_plane_helper.h>
23 #include <drm/drmP.h>
24
25 #include "sun8i_ui_layer.h"
26 #include "sun8i_mixer.h"
27 #include "sun8i_ui_scaler.h"
28
sun8i_ui_layer_enable(struct sun8i_mixer * mixer,int channel,int overlay,bool enable,unsigned int zpos,unsigned int old_zpos)29 static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel,
30 int overlay, bool enable, unsigned int zpos,
31 unsigned int old_zpos)
32 {
33 u32 val;
34
35 DRM_DEBUG_DRIVER("%sabling channel %d overlay %d\n",
36 enable ? "En" : "Dis", channel, overlay);
37
38 if (enable)
39 val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN;
40 else
41 val = 0;
42
43 regmap_update_bits(mixer->engine.regs,
44 SUN8I_MIXER_CHAN_UI_LAYER_ATTR(channel, overlay),
45 SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val);
46
47 if (!enable || zpos != old_zpos) {
48 regmap_update_bits(mixer->engine.regs,
49 SUN8I_MIXER_BLEND_PIPE_CTL,
50 SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
51 0);
52
53 regmap_update_bits(mixer->engine.regs,
54 SUN8I_MIXER_BLEND_ROUTE,
55 SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
56 0);
57 }
58
59 if (enable) {
60 val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
61
62 regmap_update_bits(mixer->engine.regs,
63 SUN8I_MIXER_BLEND_PIPE_CTL, val, val);
64
65 val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
66
67 regmap_update_bits(mixer->engine.regs,
68 SUN8I_MIXER_BLEND_ROUTE,
69 SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
70 val);
71 }
72 }
73
sun8i_ui_layer_update_coord(struct sun8i_mixer * mixer,int channel,int overlay,struct drm_plane * plane,unsigned int zpos)74 static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
75 int overlay, struct drm_plane *plane,
76 unsigned int zpos)
77 {
78 struct drm_plane_state *state = plane->state;
79 u32 src_w, src_h, dst_w, dst_h;
80 u32 outsize, insize;
81 u32 hphase, vphase;
82
83 DRM_DEBUG_DRIVER("Updating UI channel %d overlay %d\n",
84 channel, overlay);
85
86 src_w = drm_rect_width(&state->src) >> 16;
87 src_h = drm_rect_height(&state->src) >> 16;
88 dst_w = drm_rect_width(&state->dst);
89 dst_h = drm_rect_height(&state->dst);
90
91 hphase = state->src.x1 & 0xffff;
92 vphase = state->src.y1 & 0xffff;
93
94 insize = SUN8I_MIXER_SIZE(src_w, src_h);
95 outsize = SUN8I_MIXER_SIZE(dst_w, dst_h);
96
97 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
98 bool interlaced = false;
99 u32 val;
100
101 DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
102 dst_w, dst_h);
103 regmap_write(mixer->engine.regs,
104 SUN8I_MIXER_GLOBAL_SIZE,
105 outsize);
106 regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_OUTSIZE,
107 outsize);
108
109 if (state->crtc)
110 interlaced = state->crtc->state->adjusted_mode.flags
111 & DRM_MODE_FLAG_INTERLACE;
112
113 if (interlaced)
114 val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED;
115 else
116 val = 0;
117
118 regmap_update_bits(mixer->engine.regs,
119 SUN8I_MIXER_BLEND_OUTCTL,
120 SUN8I_MIXER_BLEND_OUTCTL_INTERLACED,
121 val);
122
123 DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
124 interlaced ? "on" : "off");
125 }
126
127 /* Set height and width */
128 DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
129 state->src.x1 >> 16, state->src.y1 >> 16);
130 DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
131 regmap_write(mixer->engine.regs,
132 SUN8I_MIXER_CHAN_UI_LAYER_SIZE(channel, overlay),
133 insize);
134 regmap_write(mixer->engine.regs,
135 SUN8I_MIXER_CHAN_UI_OVL_SIZE(channel),
136 insize);
137
138 if (insize != outsize || hphase || vphase) {
139 u32 hscale, vscale;
140
141 DRM_DEBUG_DRIVER("HW scaling is enabled\n");
142
143 hscale = state->src_w / state->crtc_w;
144 vscale = state->src_h / state->crtc_h;
145
146 sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, dst_w,
147 dst_h, hscale, vscale, hphase, vphase);
148 sun8i_ui_scaler_enable(mixer, channel, true);
149 } else {
150 DRM_DEBUG_DRIVER("HW scaling is not needed\n");
151 sun8i_ui_scaler_enable(mixer, channel, false);
152 }
153
154 /* Set base coordinates */
155 DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
156 state->dst.x1, state->dst.y1);
157 DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
158 regmap_write(mixer->engine.regs,
159 SUN8I_MIXER_BLEND_ATTR_COORD(zpos),
160 SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
161 regmap_write(mixer->engine.regs,
162 SUN8I_MIXER_BLEND_ATTR_INSIZE(zpos),
163 outsize);
164
165 return 0;
166 }
167
sun8i_ui_layer_update_formats(struct sun8i_mixer * mixer,int channel,int overlay,struct drm_plane * plane)168 static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel,
169 int overlay, struct drm_plane *plane)
170 {
171 struct drm_plane_state *state = plane->state;
172 const struct de2_fmt_info *fmt_info;
173 u32 val;
174
175 fmt_info = sun8i_mixer_format_info(state->fb->format->format);
176 if (!fmt_info || !fmt_info->rgb) {
177 DRM_DEBUG_DRIVER("Invalid format\n");
178 return -EINVAL;
179 }
180
181 val = fmt_info->de2_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET;
182 regmap_update_bits(mixer->engine.regs,
183 SUN8I_MIXER_CHAN_UI_LAYER_ATTR(channel, overlay),
184 SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val);
185
186 return 0;
187 }
188
sun8i_ui_layer_update_buffer(struct sun8i_mixer * mixer,int channel,int overlay,struct drm_plane * plane)189 static int sun8i_ui_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
190 int overlay, struct drm_plane *plane)
191 {
192 struct drm_plane_state *state = plane->state;
193 struct drm_framebuffer *fb = state->fb;
194 struct drm_gem_cma_object *gem;
195 dma_addr_t paddr;
196 int bpp;
197
198 /* Get the physical address of the buffer in memory */
199 gem = drm_fb_cma_get_gem_obj(fb, 0);
200
201 DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
202
203 /* Compute the start of the displayed memory */
204 bpp = fb->format->cpp[0];
205 paddr = gem->paddr + fb->offsets[0];
206
207 /* Fixup framebuffer address for src coordinates */
208 paddr += (state->src.x1 >> 16) * bpp;
209 paddr += (state->src.y1 >> 16) * fb->pitches[0];
210
211 /* Set the line width */
212 DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]);
213 regmap_write(mixer->engine.regs,
214 SUN8I_MIXER_CHAN_UI_LAYER_PITCH(channel, overlay),
215 fb->pitches[0]);
216
217 DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
218
219 regmap_write(mixer->engine.regs,
220 SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(channel, overlay),
221 lower_32_bits(paddr));
222
223 return 0;
224 }
225
sun8i_ui_layer_atomic_check(struct drm_plane * plane,struct drm_plane_state * state)226 static int sun8i_ui_layer_atomic_check(struct drm_plane *plane,
227 struct drm_plane_state *state)
228 {
229 struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
230 struct drm_crtc *crtc = state->crtc;
231 struct drm_crtc_state *crtc_state;
232 int min_scale, max_scale;
233
234 if (!crtc)
235 return 0;
236
237 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
238 if (WARN_ON(!crtc_state))
239 return -EINVAL;
240
241 min_scale = DRM_PLANE_HELPER_NO_SCALING;
242 max_scale = DRM_PLANE_HELPER_NO_SCALING;
243
244 if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) {
245 min_scale = SUN8I_UI_SCALER_SCALE_MIN;
246 max_scale = SUN8I_UI_SCALER_SCALE_MAX;
247 }
248
249 return drm_atomic_helper_check_plane_state(state, crtc_state,
250 min_scale, max_scale,
251 true, true);
252 }
253
sun8i_ui_layer_atomic_disable(struct drm_plane * plane,struct drm_plane_state * old_state)254 static void sun8i_ui_layer_atomic_disable(struct drm_plane *plane,
255 struct drm_plane_state *old_state)
256 {
257 struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
258 unsigned int old_zpos = old_state->normalized_zpos;
259 struct sun8i_mixer *mixer = layer->mixer;
260
261 sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
262 old_zpos);
263 }
264
sun8i_ui_layer_atomic_update(struct drm_plane * plane,struct drm_plane_state * old_state)265 static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
266 struct drm_plane_state *old_state)
267 {
268 struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
269 unsigned int zpos = plane->state->normalized_zpos;
270 unsigned int old_zpos = old_state->normalized_zpos;
271 struct sun8i_mixer *mixer = layer->mixer;
272
273 if (!plane->state->visible) {
274 sun8i_ui_layer_enable(mixer, layer->channel,
275 layer->overlay, false, 0, old_zpos);
276 return;
277 }
278
279 sun8i_ui_layer_update_coord(mixer, layer->channel,
280 layer->overlay, plane, zpos);
281 sun8i_ui_layer_update_formats(mixer, layer->channel,
282 layer->overlay, plane);
283 sun8i_ui_layer_update_buffer(mixer, layer->channel,
284 layer->overlay, plane);
285 sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay,
286 true, zpos, old_zpos);
287 }
288
289 static struct drm_plane_helper_funcs sun8i_ui_layer_helper_funcs = {
290 .atomic_check = sun8i_ui_layer_atomic_check,
291 .atomic_disable = sun8i_ui_layer_atomic_disable,
292 .atomic_update = sun8i_ui_layer_atomic_update,
293 };
294
295 static const struct drm_plane_funcs sun8i_ui_layer_funcs = {
296 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
297 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
298 .destroy = drm_plane_cleanup,
299 .disable_plane = drm_atomic_helper_disable_plane,
300 .reset = drm_atomic_helper_plane_reset,
301 .update_plane = drm_atomic_helper_update_plane,
302 };
303
304 static const u32 sun8i_ui_layer_formats[] = {
305 DRM_FORMAT_ABGR1555,
306 DRM_FORMAT_ABGR4444,
307 DRM_FORMAT_ABGR8888,
308 DRM_FORMAT_ARGB1555,
309 DRM_FORMAT_ARGB4444,
310 DRM_FORMAT_ARGB8888,
311 DRM_FORMAT_BGR565,
312 DRM_FORMAT_BGR888,
313 DRM_FORMAT_BGRA5551,
314 DRM_FORMAT_BGRA4444,
315 DRM_FORMAT_BGRA8888,
316 DRM_FORMAT_BGRX8888,
317 DRM_FORMAT_RGB565,
318 DRM_FORMAT_RGB888,
319 DRM_FORMAT_RGBA4444,
320 DRM_FORMAT_RGBA5551,
321 DRM_FORMAT_RGBA8888,
322 DRM_FORMAT_RGBX8888,
323 DRM_FORMAT_XBGR8888,
324 DRM_FORMAT_XRGB8888,
325 };
326
sun8i_ui_layer_init_one(struct drm_device * drm,struct sun8i_mixer * mixer,int index)327 struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
328 struct sun8i_mixer *mixer,
329 int index)
330 {
331 enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
332 int channel = mixer->cfg->vi_num + index;
333 struct sun8i_ui_layer *layer;
334 unsigned int plane_cnt;
335 int ret;
336
337 layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL);
338 if (!layer)
339 return ERR_PTR(-ENOMEM);
340
341 if (index == 0)
342 type = DRM_PLANE_TYPE_PRIMARY;
343
344 /* possible crtcs are set later */
345 ret = drm_universal_plane_init(drm, &layer->plane, 0,
346 &sun8i_ui_layer_funcs,
347 sun8i_ui_layer_formats,
348 ARRAY_SIZE(sun8i_ui_layer_formats),
349 NULL, type, NULL);
350 if (ret) {
351 dev_err(drm->dev, "Couldn't initialize layer\n");
352 return ERR_PTR(ret);
353 }
354
355 plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num;
356
357 ret = drm_plane_create_zpos_property(&layer->plane, channel,
358 0, plane_cnt - 1);
359 if (ret) {
360 dev_err(drm->dev, "Couldn't add zpos property\n");
361 return ERR_PTR(ret);
362 }
363
364 drm_plane_helper_add(&layer->plane, &sun8i_ui_layer_helper_funcs);
365 layer->mixer = mixer;
366 layer->channel = channel;
367 layer->overlay = 0;
368
369 return layer;
370 }
371
